c313d0b712
initial implementation of intrinsic parsing
...
llvm-svn: 26495
2006-03-03 02:32:46 +00:00
73fbe145fd
remove out of date comment
...
llvm-svn: 26492
2006-03-03 02:04:07 +00:00
1edf15e48e
Add support for "-Ifoo" in addition to "-I foo"
...
llvm-svn: 26487
2006-03-03 01:53:40 +00:00
d7f6b55afa
Regenerate
...
llvm-svn: 26486
2006-03-03 01:47:37 +00:00
e7b74c5da1
add support for multiple include directories
...
llvm-svn: 26485
2006-03-03 01:47:14 +00:00
53a2d60bca
New vector type v2f32.
...
llvm-svn: 26437
2006-03-01 01:10:52 +00:00
dc445eadc0
Select inline asm memory operands.
...
llvm-svn: 26349
2006-02-24 02:13:31 +00:00
43070b7541
Added x86 integer vector types: 64-bit packed byte integer (v16i8), 64-bit
...
packed word integer (v8i16), and 64-bit packed doubleword integer (v2i32).
llvm-svn: 26294
2006-02-20 22:34:53 +00:00
0add83e969
Fix bugs identified by VC++.
...
llvm-svn: 26287
2006-02-18 03:20:33 +00:00
33f4156663
Bump up pattern cost if the resulting instruction is marked
...
usesCustomDAGSchedInserter.
llvm-svn: 26282
2006-02-18 02:33:09 +00:00
3e15eac81b
Check the new form for bison output into CVS
...
llvm-svn: 26208
2006-02-15 07:24:01 +00:00
ecd162d5cd
Adjust to new form of handling lexer dependencies, this way shouldn't have
...
the problems the old way did.
llvm-svn: 26161
2006-02-14 05:13:13 +00:00
5940bc210e
Call InsertISelMapEntry rather than map insertion operator to prevent overly
...
aggrssive inlining. This reduces Select_store frame size from 24k to 10k.
llvm-svn: 26095
2006-02-09 22:12:27 +00:00
9ce762d51f
Match getTargetNode() changes (now returns SDNode* instead of SDOperand).
...
llvm-svn: 26084
2006-02-09 07:16:09 +00:00
6dc90ca172
Change Select() from
...
SDOperand Select(SDOperand N);
to
void Select(SDOperand &Result, SDOperand N);
llvm-svn: 26067
2006-02-09 00:37:58 +00:00
1630c2848f
Hoist all SDOperand declarations within a Select_{opcode}() to the top level
...
to reduce stack memory usage. This is intended to work around the gcc bug.
llvm-svn: 26026
2006-02-07 00:37:41 +00:00
5c76b499aa
Add support for modifier strings in machine instr descriptions. This allows
...
us to avoid creating lots of "Operand" types with different printers, instead
we can fold several together and use modifiers. For example, we can now use:
${target:call} to say that the operand should be printed like a 'call' operand.
llvm-svn: 26024
2006-02-06 23:40:48 +00:00
033e32e5d9
Simplify the variant handling code, no functionality change.
...
llvm-svn: 26023
2006-02-06 22:43:28 +00:00
ebf05bea1b
At the end of isel, select a replacement node for each handle that does not
...
have one. This can happen if a load's real uses are dead (i.e. they do not
have uses themselves).
llvm-svn: 26014
2006-02-06 08:12:55 +00:00
308d0090e6
Name change.
...
llvm-svn: 26013
2006-02-06 06:03:35 +00:00
aa26555b25
Handle HANDLENODE: just return itself.
...
llvm-svn: 26011
2006-02-05 08:46:14 +00:00
368f20e53d
Allow more loads to be folded which were previously prevented from happening
...
due to ordering issue. i.e. they were selected for chain use first.
Now at load select time, check if it is being selected for a chain use and if
it has only a single real use. If so, return a HANDLENODE (with the load as
its operand) in its place and record it.
When it is folded or the load is selected for a real use, the isel records it
as the replacement for the HANDLENODE. The replacement is done when all nodes
are selected.
This scheme exposed a couple of problems where cycles can happen. (See comments
in EmitMatchCode() for descriptions of the problems and their workaround /
solutions.) These problems have been resolved with a small compile time
penality.
llvm-svn: 25995
2006-02-05 06:43:12 +00:00
7ab4579c68
Re-committing the last bit of change. It shouldn't break PPC this time.
...
llvm-svn: 25982
2006-02-05 05:22:18 +00:00
586b06281c
Temporarily revert the last change, which breaks PPC and other targets that
...
DO select things.
llvm-svn: 25970
2006-02-04 09:23:06 +00:00
ce87cac555
Complex pattern's custom matcher should not call Select() on any operands.
...
Select them afterwards if it returns true.
llvm-svn: 25968
2006-02-04 08:50:49 +00:00
2bcfc52af6
node predicates add to the complexity of a pattern. This ensures that the
...
X86 backend attempts to match small-immediate versions of instructions before
the full size immediate versions.
llvm-svn: 25937
2006-02-03 18:06:02 +00:00
717db484a5
(store (op (load ...))) folding problem. In the generated matching code,
...
Chain is initially set to the chain operand of store node, when it reaches
load, if it matches the load then Chain is set to the chain operand of the
load.
However, if the matching code that follows this fails, isel moves on to the
next pattern but it does not restore Chain to the chain operand of the store.
So when it tries to match the next store / op / load pattern it would fail on
the Chain == load.getOperand(0) test.
The solution is for each chain operand to get a unique name. e.g. Chain10.
llvm-svn: 25931
2006-02-03 06:22:41 +00:00
244e800c19
add a note, ya knoe
...
llvm-svn: 25880
2006-02-01 19:12:23 +00:00
88e616d803
If a pattern's root node is a constant, its size should be 3 rather than 2.
...
llvm-svn: 25870
2006-02-01 06:06:31 +00:00
0d3ef40656
implement test/Regression/TableGen/DagIntSubst.ll
...
llvm-svn: 25836
2006-01-31 06:02:35 +00:00
a8821624d4
simplify some code
...
llvm-svn: 25791
2006-01-29 20:01:35 +00:00
1af077c0c7
it is nice not to chop off bits for those blessed with lots of bits
...
llvm-svn: 25766
2006-01-29 05:22:37 +00:00
49f323a90e
make the casts actually cast to the variable type
...
llvm-svn: 25765
2006-01-29 05:17:22 +00:00
c438c51e82
start of the 64bit safety cleanup
...
llvm-svn: 25764
2006-01-29 05:07:04 +00:00
0e352963fd
Emit series of conditionals with &&, emitting stuff like this:
...
if (N1.getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
!CodeGenMap.count(N1.getValue(0)) &&
!CodeGenMap.count(N1.getValue(1))) {
instead of this:
if (N1.getOpcode() == ISD::LOAD) {
if (N1.hasOneUse()) {
if (!CodeGenMap.count(N1.getValue(0))) {
if (!CodeGenMap.count(N1.getValue(1))) {
llvm-svn: 25763
2006-01-29 04:41:05 +00:00
7c0149d1d6
Factor matching code that is common between patterns. This works around
...
GCC not jump-threading across this common code, and produces far nicer
output.
llvm-svn: 25762
2006-01-29 04:25:26 +00:00
d3a63de91e
Split out code generation from analysis from emission
...
llvm-svn: 25759
2006-01-29 02:57:39 +00:00
afe9baeb69
move some code around, no change in the generated code
...
llvm-svn: 25758
2006-01-29 02:43:35 +00:00
5255c6c627
now that we have control over emission of the code, emit the code using nested
...
"if" statements (indenting it appropriately, of course) instead of using goto's.
This inverts the logic for all of the if statements, which makes things simpler
to understand in addition to making the generated code easier to read.
llvm-svn: 25757
2006-01-28 20:43:52 +00:00
4c4da201bf
Change PatternCodeEmitter to emit code into a buffer instead of emitting it
...
directly to the output file. This makes things simple because the code doesn't
have to worry about indentation or the case when there is no goto. It also
allows us to indent the code better without touching everything :)
llvm-svn: 25756
2006-01-28 20:31:24 +00:00
a7d6bbff00
Fit to 80 columns, no functionality change
...
llvm-svn: 25752
2006-01-28 19:06:51 +00:00
e251e92c23
Teach tablegen to generate code that is VC++ warning-free.
...
llvm-svn: 25709
2006-01-27 22:22:28 +00:00
e555a92c8d
(store (op (load ...)), ...)
...
If store's chain operand is load, then use load's chain operand instead. If
it isn't (likely a TokenFactor), then do not allow the folding.
llvm-svn: 25708
2006-01-27 22:13:45 +00:00
d98701c639
Subtarget feature can now set any variable to any value
...
llvm-svn: 25678
2006-01-27 08:09:42 +00:00
4d5a93ed28
Use printInlineAsm to, well, print inline asm's.
...
llvm-svn: 25677
2006-01-27 02:10:50 +00:00
543fe4b6aa
PHI and INLINEASM are now builtin instructions provided by Target.td
...
llvm-svn: 25673
2006-01-27 01:45:06 +00:00
db2a5f09f1
If we want to emit things in enum order, use getInstructionsByEnumValue to
...
get the order, don't compute it ourselves.
Don't emit stuff like (14<<0), emit 14 instead.
Don't attempt to get target properties for builtin instructions.
llvm-svn: 25672
2006-01-27 01:44:09 +00:00
ac8b13b32b
There is at least a 'noitinerary' itinerary now
...
llvm-svn: 25671
2006-01-27 01:41:55 +00:00
ec249a3d30
Don't emit JIT code for these instructions
...
llvm-svn: 25669
2006-01-27 01:39:38 +00:00
5815669251
Teach the dag selectors to select InlineAsm nodes.
...
Aren't we happy the pattern selectors are almost all gone?
llvm-svn: 25666
2006-01-26 23:08:55 +00:00
e9025f1f3b
Another folding problem: if a node r/w chain or flag, don't fold it if it
...
has already been selected. The number of use check is not strong enough since
a node can be replaced with newly created target node. e.g. If the original
node has two uses, when it is selected for one of the uses it is replaced with
another. Each node now has a single use but isel still should not fold it.
llvm-svn: 25651
2006-01-26 19:13:45 +00:00
dc8365d4f3
Add a FIXME comment.
...
llvm-svn: 25635
2006-01-26 02:13:31 +00:00
ecfaa0a1c9
Incoming (and optional) flag bugs. They may be embedded inside a inner node of
...
a pattern. Also, nodes which take incoming flag should not be folded if it has
more than one use.
llvm-svn: 25627
2006-01-26 00:22:25 +00:00
c5c228fa59
Fix an optional in flag bug.
...
llvm-svn: 25590
2006-01-24 20:46:50 +00:00
295e196558
Optional InFlag was not being included in node.
...
llvm-svn: 25588
2006-01-24 20:07:38 +00:00
e272b4ec17
Prevent folding of a node with multiple uses if the node already folds a load!
...
Here is an example where the load ended up being done twice:
%A = global uint 0
uint %test(uint %B, ubyte %C) {
%tmp = load uint *%A;
%X = shl uint %tmp, ubyte %C
%Cv = sub ubyte 32, %C
%Y = shr uint %B, ubyte %Cv
%Z = or uint %Y, %X
store uint %Z, uint* %A
ret uint %Z
}
==>
subl $4, %esp
movl %ebx, (%esp)
movl 8(%esp), %edx
movl A, %eax
movb 12(%esp), %bl
movb %bl, %cl
shldl %cl, %edx, %eax
movb %bl, %cl
shldl %cl, %edx, A
movl (%esp), %ebx
addl $4, %esp
ret
llvm-svn: 25471
2006-01-20 01:11:03 +00:00
9e7fb7b2fc
Bug fix. Flag operand number may be calculated incorrectly.
...
llvm-svn: 25465
2006-01-19 21:57:10 +00:00
a15731cd50
Use pattern information to determine whether the use expects this
...
instruction to produce a result. e.g MUL8m, the instruction does not
produce a explicit result. However it produces an implicit result in
AL which would be copied to a temp. The root operator of the matching
pattern is a mul so the use would expect it to produce a result.
llvm-svn: 25458
2006-01-19 10:12:58 +00:00
acec02ebf5
Prevent unnecessary CopyToReg when the same HW register appears in two spots
...
in the pattern.
llvm-svn: 25437
2006-01-19 01:55:45 +00:00
dce31c8d70
fix a broken comment
...
llvm-svn: 25411
2006-01-17 21:31:18 +00:00
5ed803256d
Regenerated the Lex and Yacc output files on Linux. It seems that our
...
Linux machines don't like the source code generated on MacOS X for some
reason.
llvm-svn: 25394
2006-01-17 17:01:34 +00:00
61864ec3fe
Emit a type matching check for ComplexPatterns.
...
llvm-svn: 25392
2006-01-17 07:36:41 +00:00
a039d439dc
Type inferencing bug
...
llvm-svn: 25337
2006-01-15 10:04:45 +00:00
bd1de84121
Allow transformation from GlobalAddress to TargetGlobalAddress and
...
ExternalSymbol to TargetExternalSymbol.
llvm-svn: 25252
2006-01-12 19:35:54 +00:00
e6300aaabc
GlobalAddress -> TargetGlobalAddress; ExternalSymbol -> TargetExternalSymbol
...
llvm-svn: 25245
2006-01-12 07:54:57 +00:00
31686087cd
Some minor fixes.
...
llvm-svn: 25227
2006-01-11 22:16:13 +00:00
e18ad392d3
Always select target registers to themselves
...
llvm-svn: 25218
2006-01-11 19:52:27 +00:00
3857f6d067
Emit an error instead of an assertion if trying to do bogus things in result patterns.
...
llvm-svn: 25194
2006-01-11 01:33:49 +00:00
230044839d
Added support for the extractelement operation.
...
llvm-svn: 25181
2006-01-10 19:05:34 +00:00
4b0623e141
* Remove instruction fields hasInFlag / hasOutFlag and added SNDPInFlag and
...
SNDPOutFlag to DAG nodes. These properties do not belong to target specific
instructions.
* Added DAG node property SNDPOptInFlag. It's same as SNDPInFlag except it's
optional. Used by ret / call, etc.
llvm-svn: 25154
2006-01-09 18:27:06 +00:00
482ef91d26
Pattern complexity calculation fix.
...
llvm-svn: 25133
2006-01-06 22:19:44 +00:00
46634d21e3
Tweak pattern complexity calc.
...
llvm-svn: 25122
2006-01-06 02:30:23 +00:00
6b037909ff
Bug fix wrt chain operand.
...
llvm-svn: 25115
2006-01-06 00:41:12 +00:00
a69bb989f1
Replace fix with one less disruptive to the original code.
...
Also note that GCC 4.1 also correctly flags the syntax error.
llvm-svn: 25076
2006-01-04 03:23:30 +00:00
7d17a6bc86
Tblgen was generating syntactically illegal C++ code like:
...
SDOperand Tmp0,Tmp1,Tmp2,Tmp3,;
GCC has a bug (24907) in which is fails to catch this, but VC++ correctly
notes its illegality, so tblgen must be taught to only generate legal C++.
llvm-svn: 25075
2006-01-04 03:15:19 +00:00
3d38031bef
Remove obsolete comment, make things look a bit nicer
...
llvm-svn: 25070
2006-01-04 00:32:01 +00:00
c29793a077
reduce stack usage of the recursive SelectCode function by out-lining each
...
case of the switch statement into its own method.
llvm-svn: 25069
2006-01-04 00:25:00 +00:00
81e4dbc6a1
Remove my previous ugly hack that tries to reduce the stack space usage
...
of SelectCode to make way for a better solution.
llvm-svn: 25068
2006-01-03 22:55:16 +00:00
def44bec82
HP-UX DVDs are crunchy and good to eat
...
llvm-svn: 25052
2005-12-30 16:41:48 +00:00
018da4f5ef
almost got the HP-UX tester up.. :)
...
llvm-svn: 25051
2005-12-30 14:56:37 +00:00
336dba6fb1
Add support for generating v4i32 altivec code
...
llvm-svn: 25046
2005-12-30 00:12:56 +00:00
ccb1aebcd3
This gets most of the backends building with HP HappyC++.
...
llvm-svn: 25029
2005-12-27 10:56:22 +00:00
14c53b45f5
Added field noResults to Instruction.
...
Currently tblgen cannot tell which operands in the operand list are results so
it assumes the first one is a result. This is bad. Ideally we would fix this
by separating results from inputs, e.g. (res R32:$dst),
(ops R32:$src1, R32:$src2). But that's a more distruptive change. Adding
'let noResults = 1' is the workaround to tell tblgen that the instruction does
not produces a result. It works for now since tblgen does not support
instructions which produce multiple results.
llvm-svn: 25017
2005-12-26 09:11:45 +00:00
14492afc23
more standards-compliance stuff
...
llvm-svn: 25014
2005-12-26 05:08:55 +00:00
0dc12c38e5
support targetexternalsym
...
llvm-svn: 25005
2005-12-24 23:36:59 +00:00
72aaf8e374
* Support for hasInFlag and hasOutFlag (on instructions). Remove nameless FLAG
...
support which is fragile.
* Fixed a number of bugs.
llvm-svn: 24996
2005-12-23 22:11:47 +00:00
d834d495b2
silence some bogus gcc warnings
...
llvm-svn: 24962
2005-12-22 20:37:36 +00:00
a87d743912
Attempt to fix a crash on WIN32.
...
llvm-svn: 24936
2005-12-22 02:35:21 +00:00
991bc6d6ba
* Added support for FLAG - a special nameless flag register. Can be used as
...
either an operand or a result.
* Fixed some more flag / chain bugs.
llvm-svn: 24933
2005-12-22 02:24:50 +00:00
f646926ecf
Allows instructions which no explicit operands. e.g. X86 RET which has but
...
an implicit flag operand.
llvm-svn: 24916
2005-12-21 20:20:49 +00:00
812a56e888
Eliminate some GCC warnings from the generated code
...
llvm-svn: 24897
2005-12-21 05:31:05 +00:00
4bf64a8ba4
Fix the semantic of Requires<[cond]> to mean if (!cond) goto PXXFail;
...
llvm-svn: 24883
2005-12-20 20:08:01 +00:00
777bb6eb45
This ugly patch works around a GCC bug where it is compiling SelectCode to
...
use too much stack space, overflowing the stack for large functions. Instead
of emitting new SDOperands in each match block, we emit some common ones at
the top of SelectCode then reuse them when possible.
This reduces the stack size of SelectCode from 28K to 21K. Note that GCC
compiles it to 512 bytes :-/
I've filed GCC PR 25505 to track this.
llvm-svn: 24882
2005-12-20 19:41:03 +00:00
9696f63d3e
Now support instructions with implicit write to non-flag registers.
...
llvm-svn: 24878
2005-12-20 07:37:41 +00:00
fe90b604a4
Lefted out a fix in the previous check in.
...
llvm-svn: 24873
2005-12-20 00:06:17 +00:00
19b9f15377
Fix another bug related to chain / flag.
...
llvm-svn: 24868
2005-12-19 22:40:04 +00:00
9bd85c2f19
Fixes for a number of bugs: save flag results in CodeGenMap, folded chains
...
may not all have ResNo == 0.
llvm-svn: 24858
2005-12-19 07:18:51 +00:00
f7ae0a95fe
Handle basic block nodes
...
llvm-svn: 24833
2005-12-18 21:05:44 +00:00
abb11cc83e
More fixes for Selection of copyto/fromreg with a flag
...
llvm-svn: 24829
2005-12-18 15:45:51 +00:00
fc3d4f8fd8
Select copytoreg and copyfromreg nodes that have flag operands correctly.
...
llvm-svn: 24827
2005-12-18 15:28:25 +00:00
e22f9181f7
Support for read / write from explicit registers with FlagVT type.
...
llvm-svn: 24753
2005-12-17 01:19:28 +00:00
d296a43f96
Added support to specify predicates.
...
llvm-svn: 24715
2005-12-14 22:02:59 +00:00
6a31777c8e
Skip over srcvalue nodes when generating ISEL code.
...
llvm-svn: 24704
2005-12-14 02:21:57 +00:00
6148153230
Bug fix: CodeGenMap[N] = ... -> CodeGenMap[N.getValue(0)] = ...
...
llvm-svn: 24680
2005-12-12 23:45:21 +00:00
7e4c01eee3
At top of generated isel SelectCode() is this:
...
if (!N.Val->hasOneUse()) {
std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(N);
if (CGMI != CodeGenMap.end()) return CGMI->second;
}
Suppose a DAG like this:
X
^ ^
/ \
USE1 USE2
Suppose USE1 is being selected first and during which X is selected and
returned a new node. After this, USE1 is no longer an use of X. During USE2
selection, X will be selected again since it has only one use!
The fix is to always query CodeGenMap.
llvm-svn: 24679
2005-12-12 23:22:48 +00:00
cdb16ef6f3
Bug fix: finding the correct incoming chain for pattern with nested src operand. And a minor change to make output code slightly more readible.
...
llvm-svn: 24669
2005-12-12 19:37:43 +00:00
4e56db674c
Add support for TargetConstantPool nodes to the dag isel emitter, and use
...
them in the PPC backend, to simplify some logic out of Select and
SelectAddr.
llvm-svn: 24657
2005-12-10 02:36:00 +00:00
0da396ffe2
Stop emitting a redudant type check for complex pattern node.
...
llvm-svn: 24655
2005-12-10 01:57:33 +00:00
bac252c289
For instructions which produce no result, e.g. store, chain's Resno == 0.
...
llvm-svn: 24652
2005-12-10 00:09:17 +00:00
433573f4c6
Add a new SDTCisPtrTy constraint, which indicates that an operand must have
...
the same type as the pointer type for a target.
llvm-svn: 24649
2005-12-09 22:57:42 +00:00
499ab2a9fa
* Do not allow nodes which produce chain results (e.g. loads) to be folded if
...
it has more than one real use (non-chain uses).
* Record folded chain producing node in CodeGenMap.
* Do not fold a chain producing node if it has already been selected as an
operand of a chain use.
llvm-svn: 24647
2005-12-09 22:45:35 +00:00
c1f911a238
Prevent folding of instructions which produce chains that have more than 1 real use
...
llvm-svn: 24643
2005-12-09 06:06:08 +00:00
f423a17e33
* Make sure complex pattern operands are selected first since their select
...
functions can return false and causing the instruction pattern match to fail.
* Code clean up.
llvm-svn: 24642
2005-12-09 00:48:42 +00:00
c9a620060b
* Added an explicit type field to ComplexPattern.
...
* Renamed MatchingNodes to RootNodes.
llvm-svn: 24636
2005-12-08 02:14:08 +00:00
9b9567bfb5
Added support for ComplexPattern. These are patterns that require C++ pattern
...
matching code that is not currently auto-generated by tblgen, e.g. X86
addressing mode. Selection routines for complex patterns can return multiple operands, e.g. X86 addressing mode returns 4.
llvm-svn: 24634
2005-12-08 02:00:36 +00:00
0fe76d1585
* Infer instruction property hasCtrlDep from pattern if it has one.
...
* Fixed a bug related to hasCtrlDep property use.
llvm-svn: 24610
2005-12-05 23:08:55 +00:00
ba369ae8f1
Implement PR673: for explicit register references, use type information
...
if available
llvm-svn: 24597
2005-12-05 02:36:37 +00:00
3717b4c830
Add some methods
...
llvm-svn: 24596
2005-12-05 02:35:08 +00:00
d49489f01e
Generate code to silence bogus GCC warnings.
...
llvm-svn: 24593
2005-12-05 00:48:51 +00:00
f02bb9af8b
* Commit the fix (by Chris) for a tblgen type inferencing bug.
...
* Enhanced tblgen to handle instructions which have chain operand and writes a
chain result.
* Enhanced tblgen to handle instructions which produces no results. Part of
the change is a temporary hack which relies on instruction property (e.g.
isReturn, isBranch). The proper fix would be to change the .td syntax to
separate results dag from ops dag.
llvm-svn: 24587
2005-12-04 08:18:16 +00:00
006bb04f3a
Support multiple ValueTypes per RegisterClass, needed for upcoming vector
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work. This change has no effect on generated code.
llvm-svn: 24563
2005-12-01 04:51:06 +00:00
fed83adbe3
Teach tblgen to accept register source operands in patterns, e.g.
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def SHL8rCL : I<0xD2, MRM4r, (ops R8 :$dst, R8 :$src),
"shl{b} {%cl, $dst|$dst, %CL}",
[(set R8:$dst, (shl R8:$src, CL))]>, Imp<[CL],[]>;
This generates a CopyToReg operand and added its 2nd result to the shl as
a flag operand.
llvm-svn: 24557
2005-12-01 00:18:45 +00:00
faad542d24
Nuke CodeGenInstruction's ValueType member, it is no longer used.
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llvm-svn: 24556
2005-12-01 00:12:04 +00:00
cdf2c67888
Stop checking the ValueType of the CodeGenInstruction. Instead, use the
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ValueType from the RegisterClass or Operands. This step is necessary to
allow RegisterClasses to have multiple ValueTypes.
llvm-svn: 24555
2005-12-01 00:06:14 +00:00
e479ccb27b
fit into 80 columns
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llvm-svn: 24554
2005-11-30 23:58:18 +00:00
3e63dc00da
Make the code generated by tblgen return the result of SelectNodeTo, to
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permit future changes.
llvm-svn: 24553
2005-11-30 23:08:45 +00:00
6f8c1ace6e
No longer track value types for asm printer operands, and remove them as
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an argument to every operand printing function. Requires some slight
tweaks to x86, the only user.
llvm-svn: 24541
2005-11-30 18:54:35 +00:00
f621b333f3
Fix some copy and paste typos.
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llvm-svn: 24540
2005-11-30 18:37:14 +00:00
c8af0cb893
Better error message when unrecognized opcode is seen.
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llvm-svn: 24519
2005-11-29 18:44:58 +00:00
4d0251ad55
Add the new vector types to tablegen
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llvm-svn: 24514
2005-11-29 06:19:38 +00:00
f2807be3da
Initialize this variable on all paths, fixing a crasher in windows. Thanks
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to JeffC for pointing this out.
llvm-svn: 24426
2005-11-19 07:48:33 +00:00
6bc0304c91
Teach tblgen about instruction operands that have multiple MachineInstr
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operands, digging into them to find register values (used on X86). Patch
by Evan Cheng!
llvm-svn: 24424
2005-11-19 07:05:57 +00:00
a70c7dff2e
Validate that the input to 'Pat' patterns is sane.
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llvm-svn: 24393
2005-11-17 17:43:52 +00:00
2a230e1c1a
teach tblgen to be smart enough to handle tglobaladdr nodes
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llvm-svn: 24391
2005-11-17 07:39:45 +00:00
b22950df6c
fix a tblgen bug that Evan ran into, where we would lose the '$src' name
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on patterns like "(set R32:$dst, (i32 imm:$src))"
llvm-svn: 24383
2005-11-16 23:14:54 +00:00
d6d3afb05e
1. Remove ranges from itinerary data.
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2. Tidy up the subtarget emittined code.
llvm-svn: 24172
2005-11-03 22:47:41 +00:00
64209fd14b
Reject integer literals that are out of range for their type.
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llvm-svn: 24162
2005-11-03 05:46:11 +00:00
590176be16
Add support for immediates directly in the pattern, this allows itanium to
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define:
def : Pat<(i1 1), (CMPEQ r0, r0)>;
llvm-svn: 24149
2005-11-02 06:49:14 +00:00
802748cd61
Allow itineraries to be passed through the Target Machine.
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llvm-svn: 24139
2005-11-01 20:06:59 +00:00
9e1784d738
Keep VC++ happy.
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llvm-svn: 24137
2005-11-01 18:04:06 +00:00
0433df136f
Emit itinerary class in instruction info.
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llvm-svn: 24122
2005-10-31 17:16:46 +00:00
3763a50d82
Generate cpu to itinerary map.
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llvm-svn: 24121
2005-10-31 17:16:01 +00:00
d91df9d941
Make negative immediates in patterns work correctly, silence some warnings
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building the itanium backend.
llvm-svn: 24095
2005-10-29 16:39:40 +00:00
742606ad30
Switch more code over to using getValueAsListOfDefs. Look at all the -'s. :)
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llvm-svn: 24074
2005-10-28 22:59:53 +00:00
7ad0bed89f
Rename Record::getValueAsListDef to getValueAsListOfDefs, to more accurately
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reflect what it is.
Convert some more code over to use it.
llvm-svn: 24072
2005-10-28 22:49:02 +00:00
802bd8d94f
Use the new interface Jim added
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llvm-svn: 24071
2005-10-28 22:43:25 +00:00
dffe5978a3
Removed Mr. Smith from the code.
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llvm-svn: 24070
2005-10-28 21:47:29 +00:00
b04feb633f
Added method to return a vector of records for a ListInit of Def field. This
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simplifies using list of records.
llvm-svn: 24069
2005-10-28 21:46:31 +00:00
1959575208
Add some commentary.
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llvm-svn: 24055
2005-10-28 15:20:43 +00:00
b0aa47b043
Keep Visual Studio happy.
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llvm-svn: 24052
2005-10-28 01:43:09 +00:00
Chris Lattner