- Track implicit instantiations vs. the not-yet-supported explicit
specializations
- Give implicit instantiations of function templates (and member
functions of class templates) linkonce_odr linkage.
- Improve name mangling for function template specializations,
including the template arguments of the instantiation and the return
type of the function.
Note that our name-mangling is improved, but not correct: we still
don't mangle substitutions, although the manglings we produce can be
demangled.
llvm-svn: 74466
Constant. This lets ConstantInts be handled as SCEVConstant instead
of SCEVUnknown, as getUnknown no longer has special-case code for
ConstantInt and friends. This usually doesn't affect the final
output, since the constants end up getting folded later, but it
does make intermediate expressions more obvious in many cases.
llvm-svn: 74459
an individual exhaustive evaluation reflects only the exit value
implied by an individual exit, which may differ from the actual
exit value of the loop if there are other exits. This fixes PR4477.
llvm-svn: 74447
Also don't call finalizers for LoopPass if initialization was not called.
Add a unittest that tests that these methods are called, in the proper
order, and the correct number of times.
llvm-svn: 74438
fence-atomic-fence down to just the atomic op. This is possible thanks to
X86's relatively strong memory model, which guarantees that locked instructions
(which are used to implement atomics) are implicit fences.
llvm-svn: 74435
-Introduce Decl::getASTContext() which returns the reference from the TranslationUnitDecl that it is contained in.
The general idea is that Decls can point to their own ASTContext so that it is no longer required to "manually" keep track and make sure that you pass the correct ASTContext to Decls' methods, e.g. methods like Decl::getAttrs should eventually not require a ASTContext parameter.
llvm-svn: 74434
After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.
llvm-svn: 74420
Anders Carlsson