Commit Graph

204393 Commits

Author SHA1 Message Date
Rui Ueyama 0744e87fad COFF: Rename getReplacement -> repl.
The previous name was too long to my taste.

llvm-svn: 241215
2015-07-02 00:21:11 +00:00
Rui Ueyama 18f8d2c5c0 COFF: Change GCRoot member type from StringRef to Undefined. NFC.
I think Undefined symbols are a bit more convenient than StringRefs
since SymbolBodies are handles for symbols. You can get resolved
symbols for undefined symbols just by calling getReplacmenet without
looking up the symbol table.

llvm-svn: 241214
2015-07-02 00:21:08 +00:00
Rui Ueyama 6bf638e688 COFF: Simplify and rename findMangle. NFC.
Occasionally we have to resolve an undefined symbol to its
mangled symbol. Previously, we did that on calling side of
findMangle by explicitly updating SymbolBody.
In this patch, mangled symbols are handled as weak aliases
for undefined symbols.

llvm-svn: 241213
2015-07-02 00:04:14 +00:00
Sean Callanan 05834cd2ad Reversed r238363, because the message is inconsistent
with all the other assertion messages.

llvm-svn: 241212
2015-07-01 23:56:30 +00:00
JF Bastien 03855df197 WebAssembly: start instructions
Summary:
* Add 64-bit address space feature.
* Rename SIMD feature to SIMD128.
* Handle single-thread model with an IR pass (same way ARM does).
* Rename generic processor to MVP, to follow design's lead.
* Add bleeding-edge processors, with all features included.
* Fix a few DEBUG_TYPE to match other backends.

Test Plan: ninja check

Reviewers: sunfish

Subscribers: jfb, llvm-commits

Differential Revision: http://reviews.llvm.org/D10880

llvm-svn: 241211
2015-07-01 23:41:25 +00:00
Greg Clayton 14cd13c513 Check to make sure we have a valid N_GSYM symbol name before we use it for anything.
llvm-svn: 241210
2015-07-01 23:29:06 +00:00
Greg Clayton e521457db3 Fix indentation.
llvm-svn: 241209
2015-07-01 23:28:31 +00:00
Siva Chandra b88703c037 [Python] Allow PyLong values in integer lists (when converting to C lists)
Test Plan: dotest.py -p TestSBData

Reviewers: clayborg, granata.enrico

Reviewed By: clayborg, granata.enrico

Subscribers: lldb-commits

Differential Revision: http://reviews.llvm.org/D10821

llvm-svn: 241208
2015-07-01 23:27:32 +00:00
Richard Smith da6c234c39 [modules] Merging support for specializations of a function template. This very
rarely matters, but can affect whether two dependent types are canonically
equivalent.

llvm-svn: 241207
2015-07-01 23:19:58 +00:00
Quentin Colombet 9729fb3315 [TwoAddressInstructionPass] Try 3 Addr Conversion After Commuting.
TwoAddressInstructionPass stops after a successful commuting but 3 Addr
conversion might be good for some cases.
 
Consider:

int foo(int a, int b) {
  return a + b;
}

Before this commit, we emit:

addl	%esi, %edi
movl	%edi, %eax
ret

After this commit, we try 3 Addr conversion:

leal	(%rsi,%rdi), %eax
ret

Patch by Volkan Keles <vkeles@apple.com>!

Differential Revision: http://reviews.llvm.org/D10851

llvm-svn: 241206
2015-07-01 23:12:13 +00:00
Richard Smith 28ff268373 [modules] Remove some out-of-date (fixed) FIXMEs.
llvm-svn: 241205
2015-07-01 23:10:03 +00:00
Pawel Bylica ea46a66ea2 Change APInt comparison with uint64_t.
Summary:
This patch changes the way APInt is compared with a value of type uint64_t.
Before the uint64_t value was truncated to the size of APInt before comparison.
Now the comparison takes into account full 64-bit precision.

Test Plan: Unit tests added. No regressions. Self-hosted check-all done as well.

Reviewers: chandlerc, dexonsmith

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10655

llvm-svn: 241204
2015-07-01 22:56:43 +00:00
Ying Chen 9b5eca903b Mark test_sb_api_listener_event_process_state as flakey
llvm-svn: 241203
2015-07-01 22:50:28 +00:00
Ying Chen 0a7202bb5d Run teardown and setup before retry for expectedFlakey tests
Summary:
If test is decorated with expectedFlakey*, run teardown and setup before retry
Don't run retry if the test is already decorated with xfail or skip

Test Plan:
Mark TestMultithreaded.test_sb_api_listener_event_process_state as expectedFlakey
Run ./dotest.py -p TestMultithreaded.py -A x86_64 -C gcc4.9.2

Reviewers: vharron, tberghammer

Subscribers: lldb-commits

Differential Revision: http://reviews.llvm.org/D10830

llvm-svn: 241202
2015-07-01 22:44:27 +00:00
Anton Yartsev 84f9042fae [analyzer] Prevent ccc/c++-analyzer from hanging on Windows.
'fork'+'exec' combination made scan-build and ccc-analyzer hang under Windows. The patch replaces 'fork'+'exec' with more reliable 'system' (ccc-analyzer) and piped 'open' (scan-build). See http://reviews.llvm.org/D8774 and http://reviews.llvm.org/D9357 for more details.

llvm-svn: 241201
2015-07-01 22:35:29 +00:00
Matthias Braun e21e0f1620 Test for specific output in lit test
llvm-svn: 241200
2015-07-01 22:34:59 +00:00
Reid Kleckner 698310b004 [SEH] Update EmitCapturedLocals to match r241187
It was still using frameaddress(1) to get the parent FP, even though it
had the value it wanted as a parameter.

llvm-svn: 241199
2015-07-01 22:33:45 +00:00
Rui Ueyama 4897596728 COFF: Chagne weak alias' type from SymbolBody** to SymbolBody*. NFC.
llvm-svn: 241198
2015-07-01 22:32:23 +00:00
Alexey Samsonov 958dab71b3 [LoopVectorize] Use ReplaceInstWithInst() helper where appropriate.
This is mostly an NFC, which increases code readability (instead of
saving old terminator, generating new one in front of old, and deleting
old, we just call a function). However, it would additionaly copy
the debug location from old instruction to replacement, which
would help PR23837.

llvm-svn: 241197
2015-07-01 22:18:30 +00:00
Pete Cooper abcac11d1b Pack MCSymbol::Flags in to the bitfield with other members. NFC.
All file formats only needed 16-bits right now which is enough to fit
in to the padding with other fields.

This reduces the size of MCSymbol to 24-bytes on a 64-bit system.  The
layout is now

   0 | class llvm::MCSymbol
   0 |   class llvm::PointerIntPair SectionOrFragmentAndHasName
   0 |     intptr_t Value
     |   [sizeof=8, dsize=8, align=8
     |    nvsize=8, nvalign=8]

   8 |   unsigned int IsTemporary
   8 |   unsigned int IsRedefinable
   8 |   unsigned int IsUsed
   8 |   _Bool IsRegistered
   8 |   unsigned int IsExternal
   8 |   unsigned int IsPrivateExtern
   8 |   unsigned int Kind
   9 |   unsigned int IsUsedInReloc
   9 |   unsigned int SymbolContents
   9 |   unsigned int CommonAlignLog2
  10 |   uint32_t Flags
  12 |   uint32_t Index
  16 |   union
  16 |     uint64_t Offset
  16 |     uint64_t CommonSize
  16 |     const class llvm::MCExpr * Value
     |   [sizeof=8, dsize=8, align=8
     |    nvsize=8, nvalign=8]

     | [sizeof=24, dsize=24, align=8
     |  nvsize=24, nvalign=8]

llvm-svn: 241196
2015-07-01 21:57:51 +00:00
Davide Italiano 67bb9f7f63 [Sema] Range-loopify InititializationSequence destructor. NFC intended.
llvm-svn: 241195
2015-07-01 21:51:58 +00:00
Simon Atanasyan 0d38933235 [ELF] Make OutputSection::memSize `const` member function. NFC
llvm-svn: 241194
2015-07-01 21:44:55 +00:00
Dan Gohman d82494bb75 [WebAssembly] Define separate Target instances for 32-bit and 64-bit.
llvm-svn: 241193
2015-07-01 21:42:34 +00:00
Adhemerval Zanella dbd75b7fa0 [ELF/AArch64] Initial General-dynamic TLS support
This patch adds initial general-dynamic TLS support for AArch64.  Currently
no optimization is done to realx for more performance-wise models (initial-exec
or local-exec).  This patch also only currently handles correctly executable
generation, although priliminary DSO support through PLT specific creation
is also added.

With this change clang/llvm bootstrap with lld is possible in static configuration
(some DSO creation fails due missing Linker script support, not AArch64 specific),
although make check also shows some issues.

llvm-svn: 241192
2015-07-01 21:35:39 +00:00
Jingyue Wu a0a56601c0 [NVPTX] expand extload/truncstore for vectors of floats
Summary:
According to PTX ISA:

For convenience, ld, st, and cvt instructions permit source and destination data operands to be wider than the instruction-type size, so that narrow values may be loaded, stored, and converted using regular-width registers. For example, 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded, stored, or converted to other types and sizes. The operand type checking rules are relaxed for bit-size and integer (signed and unsigned) instruction types; floating-point instruction types still require that the operand type-size matches exactly, unless the operand is of bit-size type.

So, the ISA does not support load with extending/store with truncatation for floating numbers. This is reflected in setting the loadext/truncstore actions to expand in the code for floating numbers, but vectors of floating numbers are not taken care of.

As a result, loading a vector of floats followed by a fp_extend may be combined by DAGCombiner to a extload, and the extload may be lowered to NVPTXISD::LoadV2 with extending information. However, NVPTXISD::LoadV2 does not perform extending, and no extending instructions are inserted. Finally, PTX instructions with mismatched types are generated, like
ld.v2.f32 {%fd3, %fd4}, [%rd2]

This patch adds the correct actions for vectors of floats, so DAGCombiner would not create loads with extending, and correct code is generated.

Patched by Gang Hu. 

Test Plan: Test case attached.

Reviewers: jingyue

Reviewed By: jingyue

Subscribers: llvm-commits, jholewinski

Differential Revision: http://reviews.llvm.org/D10876

llvm-svn: 241191
2015-07-01 21:32:42 +00:00
Marshall Clow f43a42d53e Noticed that std::allocator<const T> was missing the definition for is_always_equal. Fixed this, and added a test for it.
llvm-svn: 241190
2015-07-01 21:23:40 +00:00
Pete Cooper acfd55b039 Encode MCSymbol alignment as log2(align).
Given that alignments are always powers of 2, just encode it this way.

This matches how we encode alignment on IR GlobalValue's for example.

This compresses the CommonAlign member down to 5 bits which allows it
to pack better with the surrounding fields.

Reviewed by Duncan Exon Smith.

llvm-svn: 241189
2015-07-01 21:07:03 +00:00
Daniel Jasper 3992e2c742 clang-format: Support member function reference qualifiers with
trailing return types.

Before:
  template <typename T>
      auto x() & -> int {}

After:
  template <typename T>
  auto x() & -> int {}

llvm-svn: 241188
2015-07-01 21:02:24 +00:00
Reid Kleckner eb11c41900 [SEH] Delete the 32-bit IR lowering for __finally blocks and use x64
32-bit finally funclets are intended to be called both directly from the
parent function and indirectly from the EH runtime. Because we aren't
contorting LLVM's X86 prologue to match MSVC's, calling the finally
block directly passes in a different value of EBP than the one that the
runtime provides. We need an adapter thunk to adjust EBP to the expected
value. However, WinEHPrepare already has to solve this problem when
cleanups are not pre-outlined, so we can go ahead and rely on it rather
than duplicating work.

Now we only do the llvm.x86.seh.recoverfp dance for 32-bit SEH filter
functions.

llvm-svn: 241187
2015-07-01 21:00:00 +00:00
Reid Kleckner 6511c8bb9a [WinEH] Use llvm.x86.seh.recoverfp in WinEHPrepare
Don't pattern match for frontend outlined finally calls on non-x64
platforms. The 32-bit runtime uses a different funclet prototype.  Now,
the frontend is pre-outlining the finally bodies so that it ends up
doing most of the heavy lifting for variable capturing. We're just
outlining the callsite, and adapting the frameaddress(0) call to line up
the frame pointer recovery.

llvm-svn: 241186
2015-07-01 20:59:25 +00:00
Jingyue Wu 77b5b385ee [NVPTX] Move NVPTXPeephole after NVPTXPrologEpilogPass
Summary:
Offset of frame index is calculated by NVPTXPrologEpilogPass. Before
that the correct offset of stack objects cannot be obtained, which
leads to wrong offset if there are more than 2 frame objects. This patch
move NVPTXPeephole after NVPTXPrologEpilogPass. Because the frame index
is already replaced by %VRFrame in NVPTXPrologEpilogPass, we check
VRFrame register instead, and try to remove the VRFrame if there
is no usage after NVPTXPeephole pass.

Patched by Xuetian Weng. 

Test Plan:
Strengthened test/CodeGen/NVPTX/local-stack-frame.ll to check the
offset calculation based on SP and SPL.

Reviewers: jholewinski, jingyue

Reviewed By: jingyue

Subscribers: jholewinski, llvm-commits

Differential Revision: http://reviews.llvm.org/D10853

llvm-svn: 241185
2015-07-01 20:08:06 +00:00
Enrico Granata d4cb1dddeb When I introduced hard-coded formatters, I made them non-cacheable
This is because - in theory - the formatter could match on not just the type, but also other properties of a ValueObject, so a per-type caching would not be a good thing
On the other hand, that is not always true - sometimes the matching truly is per-type

So, introduce a non-cacheable attribute on formatters that decides whether a formatter should or should not be cached. That way, the few formatters that don't want themselves cached can do so, but most formatters (including most hard-coded ones) can cache themselves just fine

llvm-svn: 241184
2015-07-01 20:06:40 +00:00
Bill Schmidt ae94f11d55 [PPC64LE] Enable missing lxvdsx optimization, and related swap optimization
When adding little-endian vector support for PowerPC last year, I
inadvertently disabled an optimization that recognizes a load-splat
idiom and generates the lxvdsx instruction.  This patch moves the
offending logic so lxvdsx is once again generated.

This pattern is frequently generated by the vectorizer for scalar
loads of an effective constant.  Previously the lxvdsx instruction was
wrongly listed as lane-sensitive for the VSX swap optimization (since
both doublewords are identical, swaps are safe).  This patch fixes
this as well, so that vectorized code using lxvdsx can now have swaps
removed from the computation.

There is an existing test (@test50) in test/CodeGen/PowerPC/vsx.ll
that checks for the missing optimization.  However, vsx.ll was only
being tested for POWER7 with big-endian code generation.  I've added
a little-endian RUN statement and expected LE code generation for all
the tests in vsx.ll to give us a bit better VSX coverage, including
what's needed for this patch.

llvm-svn: 241183
2015-07-01 19:40:07 +00:00
Richard Smith 5327b89001 [modules] Don't make out-of-line member specializations of an instantiated
class template specialization visible just because the class template
specialization's definition is visible.

llvm-svn: 241182
2015-07-01 19:32:54 +00:00
Jim Ingham 5673eef85a Add a missing space.
llvm-svn: 241181
2015-07-01 19:27:08 +00:00
Richard Smith 04c6c1f3a5 [modules] Skip trailing attributes when skipping a class definition during parse-merging.
llvm-svn: 241180
2015-07-01 18:56:50 +00:00
Sanjay Patel 943829a1ad add a cl::opt override for TargetLoweringBase's JumpIsExpensive
This patch is not intended to change existing codegen behavior for any target. 
It just exposes the JumpIsExpensive setting on the command-line to allow for
easier testing and emergency overrides.

Also, change the existing regression test to use FileCheck, explicitly specify
the jump-is-expensive option, and use more precise checks.

Differential Revision: http://reviews.llvm.org/D10846

llvm-svn: 241179
2015-07-01 18:10:20 +00:00
Jonathan Roelofs 0e9ff6972c Disallow in-source builds (as we already do for the cmake build).
http://reviews.llvm.org/D10614

llvm-svn: 241178
2015-07-01 18:09:21 +00:00
David Blaikie be822edf03 Revert "[DebugInfo] Fix debug info generation for function static variables, typedefs, and records"
Caused PR24008.

This reverts commit r241154.

llvm-svn: 241177
2015-07-01 18:07:22 +00:00
David Blaikie d51dea67b3 Revert "[DWARF] Fix debug info generation for function static variables, typedefs, and records"
Caused PR24008

This reverts commit 37cb5f1c2db9f42d29f26b215585f56bb64ae4f5.

llvm-svn: 241176
2015-07-01 18:07:16 +00:00
Sanjay Patel 910d5daa4b fix formatting; NFC
llvm-svn: 241175
2015-07-01 17:58:53 +00:00
Sanjay Patel e4d95c6c9a fix typos in comment; NFC
llvm-svn: 241174
2015-07-01 17:55:07 +00:00
Dawn Perchik 508f040994 Fix typo in comment.
llvm-svn: 241173
2015-07-01 17:41:02 +00:00
Matthias Braun e1cd96bf9e LivePhysRegs: Add support to add pristine registers when populating with live-in/live-out registers.
Differential Revision: http://reviews.llvm.org/D10139

llvm-svn: 241172
2015-07-01 17:17:17 +00:00
Reid Kleckner d0d9a1f63f [SEH] Add 32-bit lowering for SEH __try
This re-lands r236052 and adds support for __exception_code().

In 32-bit SEH, the exception code is not available in eax. It is only
available in the filter function, and now we arrange to load it and
store it into an escaped variable in the parent frame.

As a consequence, we have to disable the "catch i8* null" optimization
on 32-bit and always generate a filter function. We can re-enable the
optimization if we detect an __except block that doesn't use the
exception code, but this probably isn't worth optimizing.

Reviewers: majnemer

Differential Revision: http://reviews.llvm.org/D10852

llvm-svn: 241171
2015-07-01 17:10:10 +00:00
Reid Kleckner f80636682c [SEH] Don't assert if the parent function lacks a personality
The EH code might have been deleted as unreachable and the personality
pruned while the filter is still present.  Currently I'm hitting this at
-O0 due to the clang bug PR24009.

llvm-svn: 241170
2015-07-01 16:45:47 +00:00
Benjamin Kramer 286d466097 [AsmPrinter] Hide implementation details
NFC.

llvm-svn: 241169
2015-07-01 16:18:16 +00:00
Jonathan Peyton 4828151635 Fix OMPT event_barrer_end
The OMPT status is never equal to ompt_status_track. ompt_status_track = 0x2 
and ompt_status_track_callback = 0x6 just share a bit, so that we can check 
for traceing and callbacks with the same status.

Patch by Tim Cramer

Differential Revision: http://reviews.llvm.org/D10863

llvm-svn: 241167
2015-07-01 15:16:04 +00:00
Arnaud A. de Grandmaison 650c520007 [AArch64] Implement add/adds/sub/subs/cmp/cmn with negative immediate aliases
This patch teaches the AsmParser to accept add/adds/sub/subs/cmp/cmn
with a negative immediate operand and convert them as shown:

  add  Rd, Rn, -imm -> sub  Rd, Rn, imm
  sub  Rd, Rn, -imm -> add  Rd, Rn, imm
  adds Rd, Rn, -imm -> subs Rd, Rn, imm
  subs Rd, Rn, -imm -> adds Rd, Rn, imm
  cmp  Rn, -imm     -> cmn  Rn, imm
  cmn  Rn, -imm     -> cmp  Rn, imm

Those instructions are an alternate syntax available to assembly coders,
and are needed in order to support code already compiling with some other
assemblers (gas). They are documented in the "ARMv8 Instruction Set
Overview", in the "Arithmetic (immediate)" section. This makes llvm-mc
a programmer-friendly assembler !

This also fixes PR20978: "Assembly handling of adding negative numbers
not as smart as gas".

llvm-svn: 241166
2015-07-01 15:05:58 +00:00
Benjamin Kramer 85b2815aba [SDAG] Give InstrEmitter hidden visibility
NFC.

llvm-svn: 241165
2015-07-01 14:55:10 +00:00