0721084327
Do not check isPredicated() on non-predicable instructions.
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llvm-svn: 37891
2007-07-05 07:06:46 +00:00
3d7008cd49
Refactor X87 instructions. As a side effect, all
...
their names are changed.
llvm-svn: 37876
2007-07-04 21:07:47 +00:00
8590f920c7
Support generation of GR64 to MMX code in the JIT.
...
llvm-svn: 37866
2007-07-04 01:29:22 +00:00
3053244b27
Allow a GR64 to be moved into an MMX register via the "movd" instruction.
...
Still need to have JIT generate this code.
llvm-svn: 37863
2007-07-04 00:19:54 +00:00
c2a6089b8b
Some spacing fixes. Cosmetic.
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llvm-svn: 37853
2007-07-03 17:07:33 +00:00
a2b3c175db
Fix for PR 1505 (and 1489). Rewrite X87 register
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model to include f32 variants. Some factoring
improvments forthcoming.
llvm-svn: 37847
2007-07-03 00:53:03 +00:00
f9ae1c6001
Vector results may be returned in XMM0 and XMM1, not just XMM0. With
...
the recent lowering changes, this allows types like <4 x double> to
be returned, using two vector registers.
llvm-svn: 37844
2007-07-02 16:21:53 +00:00
2660cef6d7
Convert .cvsignore files
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llvm-svn: 37801
2007-06-29 16:35:07 +00:00
58d1eacd80
Prevent PPC::BCC first operand, the PRED number, from being isel'd into a LI instruction.
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llvm-svn: 37790
2007-06-29 01:25:06 +00:00
444d3ca53d
No vector fneg.
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llvm-svn: 37786
2007-06-29 00:18:15 +00:00
3bd318e298
Type of vector extract / insert index operand should be iPTR.
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llvm-svn: 37784
2007-06-29 00:01:20 +00:00
f413419a72
Set implied features based upon the CPU's feature list.
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llvm-svn: 37768
2007-06-27 23:34:06 +00:00
1cbdcac409
Remove a redundant newline in the asm output for ELF .rodata sections.
...
llvm-svn: 37756
2007-06-27 15:09:47 +00:00
335c65e9a4
Silence a warning.
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llvm-svn: 37737
2007-06-26 18:31:22 +00:00
e8c1e428f2
Revert the earlier change that removed the M_REMATERIALIZABLE machine
...
instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).
llvm-svn: 37728
2007-06-26 00:48:07 +00:00
a866514528
Generalize MVT::ValueType and associated functions to be able to represent
...
extended vector types. Remove the special SDNode opcodes used for pre-legalize
vector operations, and the special MVT::Vector type used with them. Adjust
lowering and legalize to work with the normal SDNode kinds instead, and to
use the normal MVT functions to work with vector types instead of using the
two special operands that the pre-legalize nodes held.
This allows pre-legalize and post-legalize DAGs, and the code that operates
on them, to be more consistent. Pre-legalize vector operators can be handled
more consistently with scalar operators. And, -view-dag-combine1-dags and
-view-legalize-dags now look prettier for vector code.
llvm-svn: 37719
2007-06-25 16:23:39 +00:00
2e84e3f7b7
Make minor adjustments to whitespace and comments to reduce differences
...
between SSE1 instructions and their respective SSE2 analogues.
llvm-svn: 37718
2007-06-25 15:44:19 +00:00
33209bd6b8
Fix loadv2i32 to be loadv4i32, though it isn't actually used anywhere yet.
...
llvm-svn: 37717
2007-06-25 15:19:03 +00:00
e33c4b739b
Say AT&T instead of Intel in the comments for AT&T support.
...
llvm-svn: 37716
2007-06-25 15:11:25 +00:00
0c550df9d2
Fix the build.
...
llvm-svn: 37705
2007-06-22 16:59:54 +00:00
309d3d51b3
Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from
...
TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.
llvm-svn: 37704
2007-06-22 14:59:07 +00:00
485531ea9b
Quote complex names for Darwin X86 and ARM.
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llvm-svn: 37700
2007-06-22 00:54:56 +00:00
77d61e6f6d
Be more conservative of duplicating blocks.
...
llvm-svn: 37669
2007-06-19 23:55:02 +00:00
c3c949b473
Allow predicated immediate ARM to ARM calls.
...
llvm-svn: 37659
2007-06-19 21:05:09 +00:00
a7644dd9b9
Pass a SelectionDAG into SDNode::dump everywhere it's used, in prepration
...
for needing the DAG node to print pre-legalize extended value types, and
to get better debug messages with target-specific nodes.
llvm-svn: 37656
2007-06-19 14:13:56 +00:00
7936d91f70
describe an argument, hide it.
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llvm-svn: 37650
2007-06-19 05:46:06 +00:00
9e82064924
Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad
...
with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.
llvm-svn: 37644
2007-06-19 01:48:05 +00:00
a7ca624028
Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit.
...
llvm-svn: 37643
2007-06-19 01:26:51 +00:00
944200be45
If a function is vararg, never pass inreg arguments in registers. Thanks to
...
Anton for half of this patch.
llvm-svn: 37641
2007-06-19 00:13:10 +00:00
cea02ffd05
Look for VECTOR_SHUFFLE that's identity operation on either LHS or RHS. This can happen before DAGCombiner catches it.
...
llvm-svn: 37636
2007-06-19 00:02:56 +00:00
c98815ba32
Define the pushq instruction for x86-64.
...
llvm-svn: 37625
2007-06-18 14:12:56 +00:00
094a4e813a
Revert patch. It regresses:
...
define double @test2(i64 %A) {
%B = bitcast i64 %A to double
ret double %B
}
$ llvm-as < t.ll | llc -march=x86-64
before:
.align 4
.globl _test2
_test2:
movd %rdi, %xmm0
ret
after:
_test2:
subq $8, %rsp
movq %rdi, (%rsp)
movsd (%rsp), %xmm0
addq $8, %rsp
ret
llvm-svn: 37617
2007-06-16 23:57:15 +00:00
cd9673e565
Fix a failure to bit_convert from integer GPR to MMX register.
...
llvm-svn: 37611
2007-06-16 06:17:31 +00:00
36b1f5476e
Instructions with unique labels or embedded jumptables cannot be duplicated during ifcvt.
...
llvm-svn: 37606
2007-06-15 21:15:00 +00:00
5c4413120f
Rename MVT::getVectorBaseType to MVT::getVectorElementType.
...
llvm-svn: 37579
2007-06-14 22:58:02 +00:00
616627b002
Do not treat FP_REG_KILL as terminator in branch analysis (X86).
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llvm-svn: 37578
2007-06-14 22:03:45 +00:00
4a4a8eb00e
Add a target hook to allow loads from constant pools to be rematerialized, and an
...
implementation for x86.
llvm-svn: 37576
2007-06-14 20:50:44 +00:00
3a8e2a8b2f
Eliminate some redundant newlines in asm output.
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llvm-svn: 37574
2007-06-14 15:00:27 +00:00
f274efef9f
Add support to tablegen for specifying subregister classes on a per register class basis.
...
llvm-svn: 37572
2007-06-13 22:20:15 +00:00
c68554683d
Handle blocks with 2 unconditional branches in AnalyzeBranch.
...
llvm-svn: 37571
2007-06-13 17:59:52 +00:00
75372ad603
fix x86-64 mmx calling convention for real, which passes in integer gprs.
...
llvm-svn: 37534
2007-06-09 05:08:10 +00:00
a4a49e37ab
fix mmx handling bug
...
llvm-svn: 37533
2007-06-09 05:01:50 +00:00
5514bbef46
Add a utility routine to check for unpredicated terminator instruction.
...
llvm-svn: 37528
2007-06-08 21:59:56 +00:00
c7ebbaa10e
Define AsmTransCBE for ARM.
...
llvm-svn: 37527
2007-06-08 21:06:23 +00:00
6740da9407
Fix ARM condition code subsumission check.
...
llvm-svn: 37517
2007-06-08 09:14:47 +00:00
f62a5afb98
tBcc is not a barrier.
...
llvm-svn: 37516
2007-06-08 09:13:23 +00:00
842be09d86
Stupid cut-n-paste bug caused me soooo much grief. Why wasn't there a compilation warning? I blame it on the FE folks.
...
llvm-svn: 37484
2007-06-07 01:37:54 +00:00
e8c3cbf971
Mark these instructions clobbersPred. They modify the condition code register.
...
llvm-svn: 37468
2007-06-06 10:17:05 +00:00
d04409154f
Added clobbersPred.
...
llvm-svn: 37466
2007-06-06 10:15:28 +00:00
35e43c49b0
Initial Mips support, here we go! =)
...
- Modifications from the last patch included
(issues pointed by Evan Cheng are now fixed).
- Added more MipsI instructions.
- Added more patterns to match branch instructions.
llvm-svn: 37461
2007-06-06 07:42:06 +00:00
Evan Cheng