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396 Commits

Author SHA1 Message Date
Evan Cheng 0d639a28aa Rename TargetSubtarget to TargetSubtargetInfo for consistency. 
llvm-svn: 134259
 2011-07-01 21:01:15 +00:00
Evan Cheng 54b68e3432 - Added MCSubtargetInfo to capture subtarget features and scheduling 
itineraries.
- Refactor TargetSubtarget to be based on MCSubtargetInfo.
- Change tablegen generated subtarget info to initialize MCSubtargetInfo
  and hide more details from targets.

llvm-svn: 134257
 2011-07-01 20:45:01 +00:00
Evan Cheng 703a0fbf39 Hide the call to InitMCInstrInfo into tblgen generated ctor. 
llvm-svn: 134244
 2011-07-01 17:57:27 +00:00
Evan Cheng fe6e405e8c Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name to 
be the first encoded as the first feature. It then uses the CPU name to look up
features / scheduling itineray even though clients know full well the CPU name
being used to query these properties.

The fix is to just have the clients explictly pass the CPU name!

llvm-svn: 134127
 2011-06-30 01:53:36 +00:00
Eric Christopher 790d882caa Move XCore from getRegClassForInlineAsmConstraint to 
getRegForInlineAsmConstraint.

Part of rdar://9643582

llvm-svn: 134080
 2011-06-29 17:53:29 +00:00
Evan Cheng 194c3dc01f Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo. 
llvm-svn: 134030
 2011-06-28 21:14:33 +00:00
Evan Cheng 0beca53a29 Hide more details in tablegen generated MCRegisterInfo ctor function. 
llvm-svn: 134027
 2011-06-28 20:44:22 +00:00
Evan Cheng 1e210d08d8 Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.inc 
llvm-svn: 134024
 2011-06-28 20:07:07 +00:00
Evan Cheng d9997acd14 Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.inc 
into XXXGenRegisterInfo.inc.

llvm-svn: 133922
 2011-06-27 18:32:37 +00:00
Rafael Espindola 38c3c7f386 Fix cmake build. 
llvm-svn: 133830
 2011-06-24 22:01:28 +00:00
Evan Cheng 247533179a Starting to refactor Target to separate out code that's needed to fully describe 
target machine from those that are only needed by codegen. The goal is to
sink the essential target description into MC layer so we can start building
MC based tools without needing to link in the entire codegen.

First step is to refactor TargetRegisterInfo. This patch added a base class
MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to
separate register description from the rest of the stuff.

llvm-svn: 133782
 2011-06-24 01:44:41 +00:00
Jay Foad 6002068c13 Fix a FIXME by making GlobalVariable::getInitializer() return a 
const Constant *.

llvm-svn: 133400
 2011-06-19 18:37:11 +00:00
Jakob Stoklund Olesen 99f35eab45 Use set operations instead of plain lists to enumerate register classes. 
This simplifies many of the target description files since it is common
for register classes to be related or contain sequences of numbered
registers.

I have verified that this doesn't change the files generated by TableGen
for ARM and X86. It alters the allocation order of MBlaze GPR and Mips
FGR32 registers, but I believe the change is benign.

llvm-svn: 133105
 2011-06-15 23:28:14 +00:00
Jakob Stoklund Olesen 5750ca7089 Remove custom allocation order boilerplate that is no longer needed. 
The register allocators automatically filter out reserved registers and
place the callee saved registers last in the allocation order, so custom
methods are no longer necessary just for that.

Some targets still use custom allocation orders:

ARM/Thumb: The high registers are removed from GPR in thumb mode. The
NEON allocation orders prefer to use non-VFP2 registers first.

X86: The GR8 classes omit AH-DH in x86-64 mode to avoid REX trouble.

SystemZ: Some of the allocation orders are omitting R12 aliases without
explanation. I don't understand this target well enough to fix that. It
looks like all the boilerplate could be removed by reserving the right
registers.

llvm-svn: 132781
 2011-06-09 16:56:59 +00:00
Eric Christopher 0713a9d8fc Add a parameter to CCState so that it can access the MachineFunction. 
No functional change.

Part of PR6965

llvm-svn: 132763
 2011-06-08 23:55:35 +00:00
Jakob Stoklund Olesen 60cdf8e727 Flag unallocatable register classes instead of giving them empty 
allocation orders.

llvm-svn: 132509
 2011-06-02 23:07:24 +00:00
Richard Osborne 4dae7379ef Fix 80 column violations. 
llvm-svn: 132341
 2011-05-31 16:30:33 +00:00
Richard Osborne 2f14b0bb1d Add XCore intrinsic for crc8. 
llvm-svn: 132340
 2011-05-31 16:24:49 +00:00
Richard Osborne 542f9a2bcf Add XCore intrinsic for crc32. 
llvm-svn: 132336
 2011-05-31 14:47:36 +00:00
Rafael Espindola 08600bcf65 Use the dwarf->llvm mapping to print register names in the cfi 
directives.

Fixes PR9826.

llvm-svn: 132317
 2011-05-30 20:20:15 +00:00
Rafael Espindola fc9bae6f8b Replace the -unwind-tables option with a per function flag. This is more 
LTO friendly as we can now correctly merge files compiled with or without
-fasynchronous-unwind-tables.

llvm-svn: 132033
 2011-05-25 03:44:17 +00:00
Devang Patel 5de2375db8 Remove dead code. 
llvm-svn: 131974
 2011-05-24 18:27:52 +00:00
Eli Friedman 2518f8376d Make the logic for determining function alignment more explicit. No functionality change. 
llvm-svn: 131012
 2011-05-06 20:34:06 +00:00
Jay Foad 1a180156b6 Remove unused STL header includes. 
llvm-svn: 130068
 2011-04-23 19:53:52 +00:00
Chris Lattner 0ab5e2cded Fix a ton of comment typos found by codespell. Patch by 
Luis Felipe Strano Moraes!

llvm-svn: 129558
 2011-04-15 05:18:47 +00:00
Richard Osborne 9a827b30ab Add XCore intrinsics for initializing / starting / synchronizing threads. 
llvm-svn: 128633
 2011-03-31 15:13:13 +00:00
Richard Osborne 6120962d7d Add XCore intrinsic for setpsc. 
llvm-svn: 127821
 2011-03-17 18:42:05 +00:00
Richard Osborne c871eff3f5 Add XCore intrinsics for setclk, setrdy. 
llvm-svn: 127761
 2011-03-16 21:56:00 +00:00
Richard Osborne d4346f2388 Add checkevent intrinsic to check if any resources owned by the current thread 
can event.

llvm-svn: 127741
 2011-03-16 18:34:00 +00:00
Richard Osborne 024932fc77 Don't indent cases in a switch, no functionality change. 
llvm-svn: 127681
 2011-03-15 15:55:30 +00:00
Richard Osborne 5f1a26ea39 On the XCore the scavenging slot should be closest to the SP. 
llvm-svn: 127680
 2011-03-15 15:10:11 +00:00
Richard Osborne 3a68eb150b Add XCore intrinsics for getps, setps, setsr and clrsr. 
llvm-svn: 127678
 2011-03-15 13:45:47 +00:00
Owen Anderson b2c80da4ae Allow targets to specify a the type of the RHS of a shift parameterized on the type of the LHS. 
llvm-svn: 126518
 2011-02-25 21:41:48 +00:00
Richard Osborne 42f52e737e Add XCore intrinsic for eeu instruction. 
llvm-svn: 126384
 2011-02-24 13:39:18 +00:00
Richard Osborne bfa5cc0e08 Add XCore intrinsic for clre instruction. 
llvm-svn: 126322
 2011-02-23 18:52:05 +00:00
Richard Osborne 4995b05f56 Add llvm.xcore.waitevent intrinsic. The effect of this intrinsic is to enable 
events on the thread and wait until a resource is ready to event. The vector
of the resource that is ready is returned.

llvm-svn: 126320
 2011-02-23 18:35:59 +00:00
Richard Osborne 2c610aa3ed Add XCore intrinsic for the setv instruction. 
llvm-svn: 126315
 2011-02-23 16:46:37 +00:00
Richard Osborne 12377e0947 Fix format for setc instruction. 
llvm-svn: 126314
 2011-02-23 15:20:16 +00:00
Richard Osborne aab96995f6 Add XCore intrinsic for settw instruction. 
llvm-svn: 126313
 2011-02-23 14:45:03 +00:00
Richard Osborne 1ae65c7cb8 Add XCore intrinsics for various instructions on ports. 
llvm-svn: 126132
 2011-02-21 18:23:30 +00:00
Oscar Fuentes ba1186c23e Use explicit add_subdirectory's for LLVM target sublibraries instead 
of testing for its presence at cmake time.

This way the build automatically regenerates the makefiles when a svn
update brings in a new sublibrary.

llvm-svn: 126068
 2011-02-20 02:55:27 +00:00
Stuart Hastings 81c4306005 Swap VT and DebugLoc operands of getExtLoad() for consistency with 
other getNode() methods.  Radar 9002173.

llvm-svn: 125665
 2011-02-16 16:23:55 +00:00
Richard Osborne d9dde78c27 Add intrinsic for setc instruction on the XCore. 
llvm-svn: 125186
 2011-02-09 13:22:12 +00:00
Richard Osborne a31b9c2f7c Add XCore intrinsics for resource instructions. 
llvm-svn: 124794
 2011-02-03 13:14:25 +00:00
Richard Osborne 8607a67d37 Add support for trampolines on the XCore. 
llvm-svn: 124722
 2011-02-02 14:57:41 +00:00
Rafael Espindola 0e7e34e476 Remove more duplicated code. 
llvm-svn: 124056
 2011-01-23 04:43:11 +00:00
Rafael Espindola aea4958ea6 Remove duplicated code. 
llvm-svn: 124054
 2011-01-23 04:28:49 +00:00
Jakob Stoklund Olesen bbb1a54b84 Fix a few more places that should use MBB::getLastNonDebugInstr(). 
llvm-svn: 123408
 2011-01-13 22:47:43 +00:00
Anton Korobeynikov 441ae5b88c Update CMake stuff 
llvm-svn: 123171
 2011-01-10 12:39:23 +00:00
Anton Korobeynikov 2f93128109 Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs and fixes here and there. 
llvm-svn: 123170
 2011-01-10 12:39:04 +00:00