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4198 Commits

Author SHA1 Message Date
Chris Lattner bd099102f0 Fix a regression caused by a patch earlier today 
llvm-svn: 24561
 2005-12-01 03:50:19 +00:00
Andrew Lenharth ce68ef8073 Flags where I think I need them, quick, before the nightly tester starts 
llvm-svn: 24560
 2005-12-01 01:53:10 +00:00
Evan Cheng 4b02426130 Proper support for shifts with register shift value. 
llvm-svn: 24559
 2005-12-01 00:43:55 +00:00
Evan Cheng d94aa71e1a Use a getCopyToReg() variant to generate a flaggy CopyToReg node. 
llvm-svn: 24558
 2005-12-01 00:41:50 +00:00
Chris Lattner 4b25924d2a SelectNodeTo now returns its result, we must pay attention to it. 
llvm-svn: 24552
 2005-11-30 23:04:38 +00:00
Chris Lattner a75694aa16 Pay attn to the node returned by SelectNodeTo 
llvm-svn: 24551
 2005-11-30 23:02:08 +00:00
Chris Lattner af2e0373dd SelectNodeTo now returns its result, we must pay attention to it. 
llvm-svn: 24550
 2005-11-30 22:59:19 +00:00
Chris Lattner e318977940 SelectNodeTo now returns N. Use it instead of return N directly. 
llvm-svn: 24549
 2005-11-30 22:53:06 +00:00
Chris Lattner 3713e6b49c Fix Regression/CodeGen/PowerPC/2005-11-30-vastart-crash.ll 
llvm-svn: 24547
 2005-11-30 20:40:54 +00:00
Nate Begeman 11695c0537 Fix a typo in my latest change 
llvm-svn: 24542
 2005-11-30 18:57:39 +00:00
Nate Begeman 6f8c1ace6e No longer track value types for asm printer operands, and remove them as 
an argument to every operand printing function.  Requires some slight
tweaks to x86, the only user.

llvm-svn: 24541
 2005-11-30 18:54:35 +00:00
Andrew Lenharth 7ffe3affda remove redundant code 
llvm-svn: 24538
 2005-11-30 17:14:11 +00:00
Andrew Lenharth ede966e8ee Make typesafe that which isn't: FCMOVxx 
llvm-svn: 24536
 2005-11-30 17:11:20 +00:00
Andrew Lenharth 873ed82a36 FPSelect and more custom lowering 
llvm-svn: 24535
 2005-11-30 16:10:29 +00:00
Nate Begeman 1064d6ec43 First chunk of actually generating vector code for packed types. These 
changes allow us to generate the following code:

_foo:
        li r2, 0
        lvx v0, r2, r3
        vaddfp v0, v0, v0
        stvx v0, r2, r3
        blr

for this llvm:

void %foo(<4 x float>* %a) {
entry:
        %tmp1 = load <4 x float>* %a
        %tmp2 = add <4 x float> %tmp1, %tmp1
        store <4 x float> %tmp2, <4 x float>* %a
        ret void
}

llvm-svn: 24534
 2005-11-30 08:22:07 +00:00
Andrew Lenharth 6db615df14 All sorts of stuff. 
Getting in on the custom lowering thing, yay
evilness with fp setcc, yuck
trivial int select, hmmm
in memory args for functions, yay
DIV and REM, always handy.  They should be custom lowered though.

Lots more stuff compiles now (go go single source!).  Of course, none of it
probably works, but that is what the nightly tester can find out :)

llvm-svn: 24533
 2005-11-30 07:19:56 +00:00
Chris Lattner 9c7af08bc9 Fix a bug in a recent patch that broke shifts 
llvm-svn: 24526
 2005-11-30 05:11:18 +00:00
Evan Cheng 4eb7af9bc9 Added support to STORE and shifts to DAG to DAG isel. 
llvm-svn: 24525
 2005-11-30 02:51:20 +00:00
Evan Cheng d2cb70513d Fixed a minor bug: - -offset != offset iff offset == MININT 
llvm-svn: 24522
 2005-11-30 01:59:00 +00:00
Nate Begeman 048b26387b Represent the encoding of the SPR instructions as they actually are, so 
that we can use the correct SPR numbers in the InstrInfo.td file.  This is
necessary to support VRsave.

llvm-svn: 24521
 2005-11-29 22:42:50 +00:00
Evan Cheng 72ab335858 Add more X86 ISel patterns. 
llvm-svn: 24520
 2005-11-29 19:38:52 +00:00
Nate Begeman 3e7db9c6d5 Hook up one type, v4f32, to the VR RegisterClass for now. 
llvm-svn: 24517
 2005-11-29 08:17:20 +00:00
Nate Begeman c138118cdb Add the remainder of the AltiVec 4 x float instructions. Further 
enhancements will be necessary to teach the code generator that since
there is no fmul, it will have to do vmaddfp, adding +0.0.

llvm-svn: 24516
 2005-11-29 08:04:45 +00:00
Chris Lattner 9c415364cf No targets support line number info yet. 
llvm-svn: 24513
 2005-11-29 06:16:21 +00:00
Nate Begeman 89b049af90 Add the majority of the vector machien value types we expect to support, 
and make a few changes to the legalization machinery to support more than
16 types.

llvm-svn: 24511
 2005-11-29 05:45:29 +00:00
Evan Cheng 1d4af53444 Fixed a comment bug: 
createPPCPatternInstructionSelector -> createPPCISelPattern

llvm-svn: 24510
 2005-11-29 04:59:46 +00:00
Chris Lattner c418b5d938 refix typo 
llvm-svn: 24505
 2005-11-29 00:42:30 +00:00
Chris Lattner 7a18a25d33 don't say this is i128, because it isn't yet. Hopefully nate will change 
this to be something sane, but in the mean time it is unused, so safe to
make something bogus.

llvm-svn: 24504
 2005-11-29 00:41:40 +00:00
Chris Lattner d3bc8cb26d revert my change for the time being, which broke the build 
llvm-svn: 24503
 2005-11-29 00:24:08 +00:00
Chris Lattner 50986909dc fix a typo :) 
llvm-svn: 24501
 2005-11-28 22:42:15 +00:00
Chris Lattner 820c94e467 Add a missed optimization 
llvm-svn: 24495
 2005-11-28 04:52:39 +00:00
Nate Begeman 11fd6b22b1 Small tweaks noticed while on the plane. 
llvm-svn: 24492
 2005-11-26 22:39:34 +00:00
Duraid Madina 0c88f150c6 add support for dynamic_stackalloc to the dag isel (thanks andrew ;) 
next up: support argument passing in memory, not just registers

llvm-svn: 24490
 2005-11-25 07:49:25 +00:00
Nate Begeman 8492fd30ab Some first bits of AltiVec stuff: Instruction Formats, Encodings, and 
Registers.  Apologies to Jim if the scheduling info so far isn't accurate.

There's a few more things like VRsave support that need to be finished up
in my local tree before I can commit code that Does The Right Thing for
turning 4 x float into the various altivec packed float instructions.

llvm-svn: 24489
 2005-11-23 05:29:52 +00:00
Andrew Lenharth d6a0308470 Fix warning, the better way. Really, this is what this instruction is for, so use it 
llvm-svn: 24486
 2005-11-22 20:59:00 +00:00
Andrew Lenharth 03390557fa Fix warning 
llvm-svn: 24485
 2005-11-22 20:56:05 +00:00
Andrew Lenharth 0294e33ea4 massive DAGISel patch. lots and lots more stuff compiles now 
llvm-svn: 24483
 2005-11-22 04:20:06 +00:00
Nate Begeman 07890bbec4 Rather than attempting to legalize 1 x float, make sure the SD ISel never 
generates it.  Make MVT::Vector expand-only, and remove the code in
Legalize that attempts to legalize it.

The plan for supporting N x Type is to continually epxand it in ExpandOp
until it gets down to 2 x Type, where it will be scalarized into a pair of
scalars.

llvm-svn: 24482
 2005-11-22 01:29:36 +00:00
Chris Lattner ac6cb46429 Use HasDotTypeDotSizeDirective instead of forELF 
llvm-svn: 24481
 2005-11-21 23:06:54 +00:00
Chris Lattner 78161dbc84 Remove a level of indentation by using a continue. 
llvm-svn: 24479
 2005-11-21 22:48:18 +00:00
Chris Lattner 40f8c8450d Simplify the subtarget info, allow the asmwriter to do some target sensing 
based on TargetType.

llvm-svn: 24478
 2005-11-21 22:43:58 +00:00
Chris Lattner 99be8f766f Use subtarget information computed by X86Subtarget instead of rolling our own. 
llvm-svn: 24477
 2005-11-21 22:39:40 +00:00
Chris Lattner 3eb876117a Make the X86 subtarget compute the basic target type: ELF, Cygwin, Darwin, 
or native Win32

llvm-svn: 24476
 2005-11-21 22:31:58 +00:00
Chris Lattner ebc39f5a9c Add a forELF flag, allowing the removal of forCygwin and simplification of 
conditionals.

llvm-svn: 24475
 2005-11-21 22:19:48 +00:00
Chris Lattner 7df25ab429 simplify and genericize this code 
llvm-svn: 24473
 2005-11-21 19:50:31 +00:00
Duraid Madina 8edbf805d7 add support for div/rem to the dag->dag isel. yay. 
llvm-svn: 24472
 2005-11-21 14:14:54 +00:00
Chris Lattner b9db67a045 Eliminate unneeded intermediate class. Move doFinalizeMethod to bottom of 
file.

llvm-svn: 24470
 2005-11-21 08:40:17 +00:00
Chris Lattner b55de47595 Start using shared asmprinter Constant Pool emitter, use shorter cpi names. 
llvm-svn: 24469
 2005-11-21 08:38:26 +00:00
Chris Lattner 4a7eb5132b prune #include 
llvm-svn: 24468
 2005-11-21 08:33:17 +00:00
Chris Lattner 8a5f3c1b68 Switch to using the shared constant pool printer, along with using shorter 
CPI ids

llvm-svn: 24467
 2005-11-21 08:32:23 +00:00
Chris Lattner 882b9fa977 Switch to using the generic constant pool emitter impl, use shorter 
CPI names

llvm-svn: 24466
 2005-11-21 08:29:17 +00:00
Chris Lattner ef83ebd45d Use generic constant pool emission code in the AsmPrinter class. 
llvm-svn: 24465
 2005-11-21 08:26:15 +00:00
Chris Lattner ffbfa71866 Use the FunctionNumber provided by the AsmPrinter class 
llvm-svn: 24462
 2005-11-21 08:14:07 +00:00
Chris Lattner dd3bf8e4a2 Use CommentString where possible, fix a bug where aix mode wouldn't assemble 
due to basic blocks being misnamed.

llvm-svn: 24459
 2005-11-21 08:02:41 +00:00
Chris Lattner a0222a1698 unify the darwin and aix constant pool printers 
llvm-svn: 24458
 2005-11-21 07:57:37 +00:00
Chris Lattner 99946fb63f Adjust to capitalized AsmPrinter method names 
llvm-svn: 24456
 2005-11-21 07:51:23 +00:00
Chris Lattner d365627d3e Use PrivateGlobalPrefix for basic block labels. This allows the x86 darwin 
port to properly use L for the bb prefix instead of .

llvm-svn: 24454
 2005-11-21 07:43:59 +00:00
Chris Lattner c2bc19af57 use PrivateGlobalPrefix for basic blocks 
llvm-svn: 24453
 2005-11-21 07:41:05 +00:00
Chris Lattner 2b53ea99b0 Use PrivateGlobalPrefix for basic block labels 
llvm-svn: 24452
 2005-11-21 07:39:22 +00:00
Chris Lattner 9885c97088 Use PrivateGlobalPrefix for basic blocks 
llvm-svn: 24451
 2005-11-21 07:38:08 +00:00
Chris Lattner a43b832f7f Switch to the new shared SwitchSection 
llvm-svn: 24450
 2005-11-21 07:30:28 +00:00
Chris Lattner 2bccd73dbb Start using SwitchSection, allowing globals and functions to be emitted 
to specific sections.  Delete some dead functions copied from the X86 backend.

llvm-svn: 24449
 2005-11-21 07:26:04 +00:00
Chris Lattner 050bf2faf8 convert the rest of this over to use SwitchSection 
llvm-svn: 24448
 2005-11-21 07:16:34 +00:00
Chris Lattner 024e32e118 Start using the AsmPrinter shared SwitchSection code. This allows the X86 
backend to implement global variables in sections.

llvm-svn: 24447
 2005-11-21 07:11:11 +00:00
Chris Lattner b650241f8b This is now implemented in common codegen code 
llvm-svn: 24446
 2005-11-21 07:06:58 +00:00
Chris Lattner 2c0b435ba6 Rename SwitchSection -> switchSection to avoid conflicting with a future 
change.

llvm-svn: 24443
 2005-11-21 06:55:27 +00:00
Chris Lattner 8a4995e42a Start using PrivateGlobalPrefix correctly 
llvm-svn: 24442
 2005-11-21 06:51:52 +00:00
Chris Lattner 41cb115afb set PrivateGlobalPrefix on darwin, use it when printing out CP references 
llvm-svn: 24441
 2005-11-21 06:47:58 +00:00
Chris Lattner 618981fd03 Naturally align doubles in the constant pool, set PrivateGlobalPrefix on 
darwin, use it when printing the constant pool indices so the labels are
appropriately private, emit cp entries to .const instead of .data on darwin
and only emit a single .section for the constant pool, not one for each
entry.

llvm-svn: 24440
 2005-11-21 06:46:22 +00:00
Chris Lattner 6c1ca888d4 Lower READCYCLECOUNTER correctly, preserving the chain result 
llvm-svn: 24438
 2005-11-20 22:57:19 +00:00
Chris Lattner d1061ac8d1 encode rdtsc correctly 
llvm-svn: 24435
 2005-11-20 22:13:18 +00:00
Chris Lattner 6df9e11989 use chain operands to ensure the copies don't wander from the rdtsc instruction. 
llvm-svn: 24434
 2005-11-20 22:01:40 +00:00
Andrew Lenharth 0bf68ae434 The second patch of X86 support for read cycle counter. 
llvm-svn: 24430
 2005-11-20 21:41:10 +00:00
Chris Lattner d7102c4980 Teach the x86 backend about the register constraints of its addressing mode. 
Patch by Evan Cheng

llvm-svn: 24423
 2005-11-19 07:01:30 +00:00
Chris Lattner 252d88c68e Capture more operand info, patch by Evan Cheng 
llvm-svn: 24422
 2005-11-19 07:00:10 +00:00
Chris Lattner 3f0f71b92b Add load and other support to the dag-dag isel. Patch contributed by Evan 
Cheng!

llvm-svn: 24419
 2005-11-19 02:11:08 +00:00
Andrew Lenharth 6bc51c6f34 prevent latent switch creation 
llvm-svn: 24413
 2005-11-18 13:57:03 +00:00
Chris Lattner 57ce97862d add more patterns, patch by Evan Cheng. 
llvm-svn: 24406
 2005-11-18 01:04:42 +00:00
Nate Begeman 227f1bdd2f Also add the new vector value type here, for completeness. 
llvm-svn: 24405
 2005-11-18 00:53:32 +00:00
Chris Lattner cdde9990b7 only use dyld stubs if not in ppc-static mode. This completes support for 
non-static codegen.

llvm-svn: 24403
 2005-11-17 19:40:30 +00:00
Chris Lattner 6ab87fa360 refactor call operand handling to eliminate special cases from printOp. 
llvm-svn: 24401
 2005-11-17 19:25:59 +00:00
Chris Lattner bd9efdb64c disentangle call operands from branch operands a bit 
llvm-svn: 24400
 2005-11-17 19:16:08 +00:00
Chris Lattner 3570cf456b add an option to generate completely non-pic code, corresponding to what 
gcc -static produces on PPC.  This is used for building kexts and other things.

With this, materializing the address of a global looks like:

        lis r2, ha16(L_H$non_lazy_ptr)
        la r3, lo16(L_H$non_lazy_ptr)(r2)

we're still emitting stubs for functions, which is wrong.  That is next.

llvm-svn: 24399
 2005-11-17 18:55:48 +00:00
Chris Lattner 8f8ed28a64 Fix a bug that resistor on IRC hit where we tried to create token factor 
nodes of load results, not of their chain results.

llvm-svn: 24398
 2005-11-17 18:30:17 +00:00
Chris Lattner 5aba6ae3b3 Enable global address legalization, fixing a todo and allowing the removal 
of some code.  This exposes the implicit load from the stubs to the DAG, allowing
them to be optimized by the dag combiner.  It also moves darwin specific stuff
out of the isel into the legalizer, and allows more to be moved to the .td file.

llvm-svn: 24397
 2005-11-17 18:26:56 +00:00
Chris Lattner 0fe88e3f32 Teach the selector to fold lo(g) into load instruction immediate fields 
llvm-svn: 24396
 2005-11-17 18:02:16 +00:00
Chris Lattner 4b11fa284d Generate LA and ADDIS when possible. 
llvm-svn: 24395
 2005-11-17 17:52:01 +00:00
Chris Lattner 3648c20472 Use the right accessor to create this node 
llvm-svn: 24394
 2005-11-17 17:51:38 +00:00
Chris Lattner 595088aa0f Add an initial hack at legalizing GlobalAddress into the appropriate nodes 
on Darwin to remove smarts from the isel.  This is currently disabled by
default (uncomment setOperationAction(ISD::GlobalAddress to enable it).
tblgen needs to become smarter about tglobaladdr nodes and bigger patterns
needed to be added to the .td file.  However, we can currently emit stuff like
this:  :)

        li r2, lo16(L_x$non_lazy_ptr)
        lis r3, ha16(L_x$non_lazy_ptr)
        lwzx r2, r3, r2

The obvious improvements will follow.

llvm-svn: 24390
 2005-11-17 07:30:41 +00:00
Chris Lattner 840458276c Add globaladdress and targetglobaladdress nodes for dag patterns 
llvm-svn: 24389
 2005-11-17 07:20:15 +00:00
Chris Lattner 63ed749ce0 LI could theoretically be used for the lo-part of a global address, just like 
lis can be used for the high part.

llvm-svn: 24388
 2005-11-17 07:04:43 +00:00
Chris Lattner b7025749e1 When lowering direct calls, lower them to use a targetglobaladress directly 
instead of a globaladdress.  This has no effect on the generated code at all.

llvm-svn: 24386
 2005-11-17 05:56:14 +00:00
Chris Lattner 2bf458af92 Add patterns for some 16-bit immediate instructions, patch contributed by 
Evan Cheng.

llvm-svn: 24384
 2005-11-17 02:01:55 +00:00
Chris Lattner 5930d3df3d Add patterns for several simple instructions that take i32 immediates. 
Patch contributed by Evan Cheng!

llvm-svn: 24382
 2005-11-16 22:59:19 +00:00
Andrew Lenharth 59eefd4787 who would have thought you would want to write into globals too 
llvm-svn: 24381
 2005-11-16 21:15:53 +00:00
Chris Lattner 655e7dfd0d initial step at adding a dag-to-dag isel for X86 backend. Patch contributed 
by Evan Cheng!

llvm-svn: 24371
 2005-11-16 01:54:32 +00:00
Nate Begeman a171f6b20c Patch to clean up function call pseudos and support the BLA instruction, 
which branches to an absolute address.  This is required to support objc
direct dispatch.

llvm-svn: 24370
 2005-11-16 00:48:01 +00:00
Chris Lattner 63985e2892 Make sure to use SwitchSection to switch sections so that we don't accidentally emit 
functions into the .const section.  Whoops.

llvm-svn: 24363
 2005-11-15 01:45:01 +00:00
Chris Lattner 76ac068568 Separate X86ISelLowering stuff out from the X86ISelPattern.cpp file. Patch 
contributed by Evan Cheng.

llvm-svn: 24358
 2005-11-15 00:40:23 +00:00
Chris Lattner 1a4adc7aee Handle globals with explicit alignment requests 
llvm-svn: 24355
 2005-11-14 19:00:30 +00:00
Chris Lattner 0aacd2ab9b Teach the PPC asmwriter to honor globals with explicit section requests. 
llvm-svn: 24353
 2005-11-14 18:52:46 +00:00
Duraid Madina 76034f95f6 add FP select. next up - divide! 
llvm-svn: 24346
 2005-11-14 01:17:30 +00:00
Chris Lattner 54c8fcf303 unbreak the build 
llvm-svn: 24339
 2005-11-13 01:45:23 +00:00
Andrew Lenharth ab72424488 enable LSR by default on alpha 
llvm-svn: 24337
 2005-11-12 19:21:08 +00:00
Andrew Lenharth 2ba45d1ee9 fix more regressions 
llvm-svn: 24335
 2005-11-12 19:06:28 +00:00
Andrew Lenharth 56526ec1a9 fix READCYCLECOUNTER 
llvm-svn: 24334
 2005-11-12 19:04:09 +00:00
Andrew Lenharth 97e8207a05 fix yet more regressions 
llvm-svn: 24308
 2005-11-11 23:08:46 +00:00
Andrew Lenharth fab772045e generate chain result 
llvm-svn: 24307
 2005-11-11 23:02:55 +00:00
Andrew Lenharth 5b3b9d7052 Fix a bunch more alpha regressions 
llvm-svn: 24304
 2005-11-11 19:52:25 +00:00
Andrew Lenharth 01aa56397d continued readcyclecounter support 
llvm-svn: 24300
 2005-11-11 16:47:30 +00:00
Chris Lattner fafff9ba1d Make BB and CPI labels use the function number, not the function name as a 
uniquing id.  This makes things happy when the function name is quoted,
preventing labels like LBB"foo"_2.

llvm-svn: 24295
 2005-11-10 21:59:25 +00:00
Chris Lattner 4b3b9192b2 do not allow '.' in symbol names 
llvm-svn: 24292
 2005-11-10 21:39:29 +00:00
Chris Lattner 9eb7dfa15a Darwin supports quoted labels. This implements: 
test/Regression/CodeGen/PowerPC/darwin-labels.ll

llvm-svn: 24287
 2005-11-10 19:33:43 +00:00
Chris Lattner 369b61f068 Call this method with the object we have 
llvm-svn: 24279
 2005-11-10 18:53:25 +00:00
Chris Lattner 59e44ff3d3 Make the aix asm printer interface properly with the parent class 
llvm-svn: 24274
 2005-11-10 18:20:29 +00:00
Andrew Lenharth e373163e95 fix a bunch of regressions 
llvm-svn: 24269
 2005-11-10 16:59:55 +00:00
Andrew Lenharth 97a7fcfd2b whatever. Intermediate patch to see what breaks. Seems ok. 
llvm-svn: 24260
 2005-11-09 19:17:08 +00:00
Chris Lattner 88e234dd49 Add a new option to indicate we want the code generator to emit code quickly, 
not spending tons of time microoptimizing it.  This is useful for an -O0
style of build.

llvm-svn: 24235
 2005-11-08 02:12:47 +00:00
Chris Lattner b28f214033 Add a new option to indicate we want the code generator to emit code quickly,not spending tons of time microoptimizing it. This is useful for an -O0style of build. 
llvm-svn: 24233
 2005-11-08 02:11:51 +00:00
Duraid Madina 3c1c8c55c3 add support for storing and returning bools 
llvm-svn: 24228
 2005-11-07 03:11:02 +00:00
Duraid Madina 4a30d4a460 just some random hacking - calls (particularly indirect) need a lot of 
love (especially with -sched=simple)

llvm-svn: 24225
 2005-11-06 13:43:30 +00:00
Nate Begeman 3ee3e69556 Add the necessary support to the ISel to allow targets to codegen the new 
alignment information appropriately.  Includes code for PowerPC to support
fixed-size allocas with alignment larger than the stack.  Support for
arbitrarily aligned dynamic allocas coming soon.

llvm-svn: 24224
 2005-11-06 09:00:38 +00:00
Duraid Madina 4645db0948 ask for 16-byte aligned jmpbufs. This should unbreak C++ on IA64 (and 
a bunch of other things) but is currently ignored by the code
generator.

llvm-svn: 24206
 2005-11-06 04:29:30 +00:00
Chris Lattner 75fe59c4ea add a case Nate sent me 
llvm-svn: 24195
 2005-11-05 08:57:56 +00:00
Duraid Madina 31071b7471 oops, forgot to load GP for indirect calls, though the old code now commented 
out failed (e.g. methcall) - now the code compiles, though it's not quite
right just yet (tm) ;)

would fix this but it's 3am! :O

llvm-svn: 24186
 2005-11-04 17:55:53 +00:00
Duraid Madina d3260128af kill redundant SP/GP/RP save/restores across calls 
llvm-svn: 24183
 2005-11-04 10:01:10 +00:00
Duraid Madina fc1d1b2499 add support for loading bools 
llvm-svn: 24182
 2005-11-04 09:59:06 +00:00
Duraid Madina 7ac646ef95 fun with predicates! (add TRUNC i64->i1, AND i1 i1, fix XOR i1 i1) 
llvm-svn: 24175
 2005-11-04 00:57:56 +00:00
Duraid Madina f0f22a55b0 add pattern to load constant 0 into a predicate reg 
llvm-svn: 24164
 2005-11-03 10:09:32 +00:00
Chris Lattner 674660ff03 Fix a bug that prevented this pattern from matching 
llvm-svn: 24161
 2005-11-03 05:45:34 +00:00
Chris Lattner 9b9a839605 Fix a QOI issue noticed by Markus F.X.J. Oberhumer. 
This fixes PR641

llvm-svn: 24154
 2005-11-02 17:42:58 +00:00
Duraid Madina 955ffafd79 "fix" support for FP constants (this code asserts in the scheduler, 
though)

llvm-svn: 24152
 2005-11-02 07:32:59 +00:00
Duraid Madina 4480dcdcea add F0 and F1 to the FP register class 
llvm-svn: 24151
 2005-11-02 07:30:39 +00:00
Chris Lattner b5310bdbe9 This works now 
llvm-svn: 24150
 2005-11-02 06:49:37 +00:00
Duraid Madina 17decbb253 add support for SELECT to TargetSelectionDAG.td, add support for 
selecting ints to IA64, and a few other ia64 bits and pieces

llvm-svn: 24147
 2005-11-02 02:37:18 +00:00
Duraid Madina 9abf1650ed add support for loading FP constants +0.0 and +1.0 to the dag isel, 
stop pretending -0.0 and -1.0 are machine constants

llvm-svn: 24146
 2005-11-02 02:35:04 +00:00
Jim Laskey 802748cd61 Allow itineraries to be passed through the Target Machine. 
llvm-svn: 24139
 2005-11-01 20:06:59 +00:00
Duraid Madina 5a087ff8c3 heh, scheduling was easy? 
need to send chris, jim and sampo a box of fish each

llvm-svn: 24135
 2005-11-01 05:49:08 +00:00
Duraid Madina 9b61d3c1e2 FORTRAN!!! :( and other similarly unfortunate things mean that on ia64 
one sometimes needs to pass FP args in both FP *and* integer registers.

llvm-svn: 24134
 2005-11-01 05:46:16 +00:00
Duraid Madina b81b61330e so tablegen was thinking I might want to convert FPs to predicates. 
clever little tablegen!

llvm-svn: 24133
 2005-11-01 03:32:15 +00:00
Duraid Madina 6c912bffd6 add support for int->FP and FP->int ops, and add ia64 patterns for these 
llvm-svn: 24132
 2005-11-01 03:07:25 +00:00
Duraid Madina a284b6636f add zeroextend predicate->integer 
llvm-svn: 24131
 2005-11-01 01:29:55 +00:00
Chris Lattner 7432ceef5c Add a flag to enable a darwin linker optimization 
llvm-svn: 24130
 2005-11-01 00:12:36 +00:00
Chris Lattner 6b63e0c6fd Make constant pool entries use private labels. This is important when you're 
not compiling a whole program at a time :)

llvm-svn: 24129
 2005-10-31 22:12:06 +00:00
Duraid Madina 88fc69f627 add FP compares and implicit register defs to the dag isel 
llvm-svn: 24118
 2005-10-31 01:42:11 +00:00
Chris Lattner 5c7d731832 If the module has no t-t and the host is an alpha, default to using the Alpha BE 
llvm-svn: 24110
 2005-10-30 16:44:01 +00:00
Duraid Madina 57b7ee9da8 fix some broken comparisons, this affected the Pattern isel too. 
llvm-svn: 24109
 2005-10-30 10:14:19 +00:00
Chris Lattner e507a15184 This is implemented 
llvm-svn: 24107
 2005-10-30 06:42:12 +00:00
Chris Lattner 85b184b292 Make -time-passes output prettier 
llvm-svn: 24096
 2005-10-29 16:45:02 +00:00
Duraid Madina 7abaf906e2 add some FP stuff, some mix.* stuff, and constant pool support to the 
DAG instruction selector, which should be destroyed one day (in the pattern
isel also) since ia64 can pack any constant in the instruction stream

llvm-svn: 24094
 2005-10-29 16:08:30 +00:00
Chris Lattner dcceae104e remove reference to this pass 
llvm-svn: 24088
 2005-10-29 05:28:34 +00:00
Duraid Madina c252f33fdb add shladd 
llvm-svn: 24080
 2005-10-29 04:13:40 +00:00
Nate Begeman 00cea9b2e0 New case to handle someday 
llvm-svn: 24075
 2005-10-28 23:26:57 +00:00
Chris Lattner 7ca53a5783 Don't emit "32" for unordered comparison 
llvm-svn: 24073
 2005-10-28 22:58:07 +00:00
Chris Lattner f8899a6877 add a hack to get code with ordered comparisons working. This hack is 
tracked as PR642

llvm-svn: 24068
 2005-10-28 20:49:47 +00:00
Chris Lattner 5d6cb604de add support for branch on ordered/unordered. 
llvm-svn: 24067
 2005-10-28 20:32:44 +00:00
Chris Lattner 97d72c80e4 Do not globalize internal symbols 
llvm-svn: 24064
 2005-10-28 18:44:07 +00:00
Chris Lattner 12fca42062 These are autogenerated 
llvm-svn: 24063
 2005-10-28 18:26:52 +00:00
Duraid Madina f221c261f3 DAG->DAG instruction selection for ia64! "hello world" works, not much else. 
use -enable-ia64-dag-isel to turn this on

TODO: delete lowering stuff from the pattern isel
    : get operations on predicate bits working
    : get other bits of pseudocode going
    : use sampo's mulh/mull-using divide-by-constant magic
    : *so* many patterns ("extr", "tbit" and "dep" will be fun :)
    : add FP
    : add a JIT!
    : get it working 100%

in short: this'll be happier in a couple of weeks, but it's here now so
the tester can make me feel guilty sooner.

OTHER: there are a couple of fixes to the pattern isel, in particular
making the linker happy with big blobs of fun like pypy.

llvm-svn: 24058
 2005-10-28 17:46:35 +00:00
Chris Lattner 529169cab2 remove dead stuff 
llvm-svn: 24054
 2005-10-28 04:58:24 +00:00
Chris Lattner e68a807025 Eliminate getClass, it is not needed 
llvm-svn: 24053
 2005-10-28 04:57:11 +00:00
Chris Lattner a0dfc67ae6 a bad case for bitfield insert 
llvm-svn: 24051
 2005-10-28 00:20:45 +00:00
Andrew Lenharth 381cab36ed int comparison patterns 
llvm-svn: 24020
 2005-10-26 18:44:45 +00:00
Jim Laskey 75eab3ca63 Typo made worse x 2 - take 2. 
llvm-svn: 24018
 2005-10-26 18:07:50 +00:00
Chris Lattner f718a9e17b Fix an assert compiling MallocBench/gs 
llvm-svn: 24017
 2005-10-26 18:01:11 +00:00
Jim Laskey b1f2cedbaa Typo x 2 
llvm-svn: 24016
 2005-10-26 17:50:22 +00:00
Andrew Lenharth 7ac194560e Simplify instinfo, set random bits on more fp insts, and fix 1 opcode 
llvm-svn: 24014
 2005-10-26 17:41:46 +00:00
Jim Laskey a2b5235fac Give full control of subtarget features over to table generated code. 
llvm-svn: 24013
 2005-10-26 17:30:34 +00:00
Jim Laskey 53ad110490 Add attribute name and type to SubtargetFeatures. 
llvm-svn: 24012
 2005-10-26 17:28:23 +00:00
Chris Lattner ce9580fce4 Add nodes for CondCodeSDNode and setcc, and add a bunch of pattern fragments 
to make it easy to use them.  This lets you write patterns like:

(set PRRC:$rd, (setne GPRC:$rS, imm:$SH))

and stuff.

llvm-svn: 24009
 2005-10-26 17:00:25 +00:00
Nate Begeman ff1796534f Add a note about some bitfield stuff we could be doing better. 
llvm-svn: 23994
 2005-10-25 23:50:02 +00:00
Nate Begeman 762bf809b5 Correctly Expand or Promote FP_TO_UINT based on the capabilities of the 
machine.  This allows us to generate great code for i32 FP_TO_UINT now on
targets with 64 bit extensions.

llvm-svn: 23993
 2005-10-25 23:48:36 +00:00
Chris Lattner 81ff73ec46 autogen undef 
llvm-svn: 23991
 2005-10-25 21:03:41 +00:00
Chris Lattner 3a4b141e8c Add undef 
llvm-svn: 23990
 2005-10-25 21:03:14 +00:00
Chris Lattner b439dad538 Allow pseudos to have patterns, no functionality change 
llvm-svn: 23988
 2005-10-25 20:58:43 +00:00
Chris Lattner 261009a4df Autogen fsel 
llvm-svn: 23987
 2005-10-25 20:55:47 +00:00
Chris Lattner 65845a2f7c Expose the fextend on the DAG instead of doing it in the matcher 
llvm-svn: 23986
 2005-10-25 20:54:57 +00:00
Chris Lattner cd7f101c9a Autogen a few new ppc-specific nodes 
llvm-svn: 23985
 2005-10-25 20:41:46 +00:00
Chris Lattner 26ee5953f7 The dag isel generator generates this now 
llvm-svn: 23984
 2005-10-25 20:36:10 +00:00
Chris Lattner c0a201c318 Be a bit more paranoid about calling SelectNodeTo 
llvm-svn: 23982
 2005-10-25 20:26:41 +00:00
Chris Lattner e1fd05ebde Fix a couple of minor bugs. The first fixes povray, the second fixes things 
if the dag combiner isn't run

llvm-svn: 23981
 2005-10-25 19:32:37 +00:00
Jim Laskey db4621a5f5 Preparation of supporting scheduling info. Need to find info based on selected 
CPU.

llvm-svn: 23974
 2005-10-25 15:15:28 +00:00
Chris Lattner 76b12c4d95 do not wrap this whole file in namespace llvm 
llvm-svn: 23962
 2005-10-24 06:38:35 +00:00
Chris Lattner 2a65d7b633 Make this build with GCC 4.1, patch contributed by Vladimir A. Merzliakov! 
llvm-svn: 23956
 2005-10-24 04:51:35 +00:00
Chris Lattner bde3845548 DONT_BUILD_RELINKED is gone and implied by BUILD_ARCHIVE now 
llvm-svn: 23940
 2005-10-24 02:26:13 +00:00
Chris Lattner df88d79c08 only build .a version of this library 
llvm-svn: 23938
 2005-10-24 02:14:49 +00:00
Chris Lattner 437b6116c9 There is no need to build an archive version of this library 
llvm-svn: 23936
 2005-10-24 02:09:03 +00:00
Chris Lattner 87d4e1c130 This file is hopelessly out of date 
llvm-svn: 23935
 2005-10-24 02:07:08 +00:00
Chris Lattner d36c34822e Simplify this, matching changes in the tblgen emitter 
llvm-svn: 23909
 2005-10-23 22:34:25 +00:00
Chris Lattner 03bf3a1763 Simplify this due to changes in the tblgen side 
llvm-svn: 23908
 2005-10-23 22:33:22 +00:00
Chris Lattner abcce5c4b3 mark this as beta 
llvm-svn: 23906
 2005-10-23 22:23:45 +00:00
Chris Lattner 8ff9df29a9 If a user requests help, give them help on both features and processors 
llvm-svn: 23905
 2005-10-23 22:23:13 +00:00
Chris Lattner 766361e8f4 Autogen subtarget information from .td files. 
llvm-svn: 23904
 2005-10-23 22:15:34 +00:00
Chris Lattner 4b5921d4d8 Add subtarget feature/processor defns to the .td file 
llvm-svn: 23903
 2005-10-23 22:08:45 +00:00
Chris Lattner a389f0d8fa rearrange things a bit so that instructions can use subtarget features in the 
future.

llvm-svn: 23902
 2005-10-23 22:08:13 +00:00
Chris Lattner 437fd559d7 add a marker 
llvm-svn: 23901
 2005-10-23 22:07:20 +00:00
Chris Lattner b54070745e add a note that Nate mentioned last week 
llvm-svn: 23898
 2005-10-23 21:44:59 +00:00
Chris Lattner 2e81fba9cd Put some of my random notes somewhere public 
llvm-svn: 23897
 2005-10-23 19:52:42 +00:00
Chris Lattner f64f8407c2 Improve help output. 
llvm-svn: 23893
 2005-10-23 05:33:39 +00:00
Chris Lattner 0d4923b975 improve -help output 
llvm-svn: 23892
 2005-10-23 05:28:51 +00:00
Chris Lattner 18a70c35b8 Move static functions from .h file, reduce #includes, pass strings by const&, 
use LowercaseString from StringExtras.h, remove extraneous space from help
output.

llvm-svn: 23891
 2005-10-23 05:26:26 +00:00
Andrew Lenharth c6072af580 Add several things. 
loads
branches
setcc
working calls
Global address
External addresses

now I can manage malloc calls.

llvm-svn: 23887
 2005-10-23 03:43:48 +00:00
Andrew Lenharth 5a990417f8 Well, the Constant matching pattern works. Can't say much about calls or globals yet. 
llvm-svn: 23884
 2005-10-22 22:06:58 +00:00
Chris Lattner 42b3a5d596 This file is entirely ifdef'd out 
llvm-svn: 23882
 2005-10-22 19:37:08 +00:00
Jim Laskey 13a19453d2 Add g3 back to the mix and reorder to irritate them anal folk. Actually, it's 
to group appropriately and provide cues to maintainers that the lists don't
need to be ordered.

llvm-svn: 23880
 2005-10-22 08:04:24 +00:00
Chris Lattner c5d511c4d9 64-bit reg support should not be enabled by default, as support isn't complete. 
llvm-svn: 23878
 2005-10-21 22:15:43 +00:00
Chris Lattner e296949fbe Instead of aborting if not a case we can handle specially, break out and 
let the generic code handle it.  This fixes CodeGen/Generic/2005-10-21-longlonggtu.ll on ppc.

also, reindent this code

llvm-svn: 23874
 2005-10-21 21:17:10 +00:00
Jim Laskey 9ed9032e22 Plugin new subtarget backend into the build. 
llvm-svn: 23870
 2005-10-21 19:05:19 +00:00
Chris Lattner 229878b7bc silence a release mode warning 
llvm-svn: 23868
 2005-10-21 16:01:26 +00:00
Nate Begeman fd0d55ec69 Match rotate. This does actually match the rotates in an rc5 cipher, but I 
haven't seen it fire on our testsuite.

llvm-svn: 23863
 2005-10-21 06:36:18 +00:00
Nate Begeman ae5d9bd65b Don't generate operations that aren't yet supported 
llvm-svn: 23858
 2005-10-21 01:52:45 +00:00
Nate Begeman 62e9e5462c Kill some now-dead code. 
llvm-svn: 23857
 2005-10-21 01:52:20 +00:00
Andrew Lenharth a099c0131e byte zap not immediate goodness 
llvm-svn: 23855
 2005-10-21 01:24:05 +00:00
Nate Begeman 4dd383120f Invert the TargetLowering flag that controls divide by consant expansion. 
Add a new flag to TargetLowering indicating if the target has really cheap
  signed division by powers of two, make ppc use it.  This will probably go
  away in the future.
Implement some more ISD::SDIV folds in the dag combiner
Remove now dead code in the x86 backend.

llvm-svn: 23853
 2005-10-21 00:02:42 +00:00
Andrew Lenharth a6a23b5874 Inst cleanup. As a bonus, operands are in the correct order for cmovs. Expect new stuff to pass in the JIT tonight 
llvm-svn: 23852
 2005-10-20 23:58:36 +00:00
Chris Lattner a553780e98 Use a literal to define ineg instead of immzero 
llvm-svn: 23851
 2005-10-20 23:30:37 +00:00
Andrew Lenharth d4c0ed74e4 added a few 1 operand form stuff. Seems to break regalloc on alpha. sigh 
llvm-svn: 23849
 2005-10-20 19:39:24 +00:00
Andrew Lenharth 7e0e8234f6 add cttz and ctpop 
llvm-svn: 23848
 2005-10-20 19:38:11 +00:00
Andrew Lenharth eb0ad1863b Sounds good, finish the intop conversion. 
llvm-svn: 23843
 2005-10-20 14:42:48 +00:00
Nate Begeman 60bbe2d1e5 Add some more patterns for i64 on ppc 
llvm-svn: 23842
 2005-10-20 07:51:08 +00:00
Chris Lattner fd07fcda67 Add some pattern fragments to simplify the repetitive parts of the patterns 
for some common ops and use them for a few examples.  Andrew, if you like
this, feel free to convert the rest over, if you hate it, feel free to
revert.

llvm-svn: 23837
 2005-10-20 04:21:06 +00:00
Chris Lattner cd4be8798f simplify this a bit by using immediates 
llvm-svn: 23836
 2005-10-20 03:57:03 +00:00
Nate Begeman c6f067a8c4 Move the target constant divide optimization up into the dag combiner, so 
that the nodes can be folded with other nodes, and we can not duplicate
code in every backend.  Alpha will probably want this too.

llvm-svn: 23835
 2005-10-20 02:15:44 +00:00
Andrew Lenharth 794f15868a forgot this one 
llvm-svn: 23833
 2005-10-20 00:29:02 +00:00
Andrew Lenharth 7b69867052 ret 0; works, not much else 
still lots of uglyness.
Maybe calls will come soon.
Fixing the return value of things will be necessary to make alpha work.

llvm-svn: 23832
 2005-10-20 00:28:31 +00:00
John Criswell 196e8c1f58 This fixes PR638: 
Regression/CodeGen/Generic/2004-02-08-UnwindSupport.llx

llvm-svn: 23831
 2005-10-19 20:07:15 +00:00
Jim Laskey 74ab9960f2 Added InstrSchedClass to each of the PowerPC Instructions. 
Note that when adding new instructions that you should refer to the table at the
bottom of PPCSchedule.td.

llvm-svn: 23830
 2005-10-19 19:51:16 +00:00
Nate Begeman 9f3c26c4ea Write patterns for the various shl and srl patterns that don't involve 
doing something clever.

llvm-svn: 23824
 2005-10-19 18:42:01 +00:00
Jim Laskey 9761100055 Push processor descriptions to the top of target and add command line info. 
llvm-svn: 23820
 2005-10-19 13:34:52 +00:00
Chris Lattner c16b0c387f now that tblgen is smarter, use integers directly. This should help Andrew too 
llvm-svn: 23818
 2005-10-19 04:32:04 +00:00
Chris Lattner 5f37623218 teach ppc backend these are copies 
llvm-svn: 23813
 2005-10-19 01:50:36 +00:00
Chris Lattner 5b6f4dc623 Convert these cases to patterns 
llvm-svn: 23811
 2005-10-19 01:38:02 +00:00
Nate Begeman 9eaa6bac06 Woo, it kinda works. We now generate this atrociously bad, but correct, 
code for long long foo(long long a, long long b) { return a + b; }

_foo:
        or r2, r3, r3
        or r3, r4, r4
        or r4, r5, r5
        or r5, r6, r6
        rldicr r2, r2, 32, 31
        rldicl r3, r3, 0, 32
        rldicr r4, r4, 32, 31
        rldicl r5, r5, 0, 32
        or r2, r3, r2
        or r3, r5, r4
        add r4, r3, r2
        rldicl r2, r4, 32, 32
        or r4, r4, r4
        or r3, r2, r2
        blr

llvm-svn: 23809
 2005-10-19 01:12:32 +00:00
Chris Lattner ecdf842311 apply some tblgen majik to simplify the X register definitions 
llvm-svn: 23805
 2005-10-19 00:17:55 +00:00
Nate Begeman 92e77502f3 Make a new reg class for 64 bit regs that aliases the 32 bit regs. This 
will have to tide us over until we get real subreg support, but it prevents
the PrologEpilogInserter from spilling 8 byte GPRs on a G4 processor.

Add some initial support for TRUNCATE and ANY_EXTEND, but they don't
currently work due to issues with ScheduleDAG.  Something wll have to be
figured out.

llvm-svn: 23803
 2005-10-19 00:05:37 +00:00
Nate Begeman 78afac2ddd Add the ability to lower return instructions to TargetLowering. This 
allows us to lower legal return types to something else, to meet ABI
requirements (such as that i64 be returned in two i32 regs on Darwin/ppc).

llvm-svn: 23802
 2005-10-18 23:23:37 +00:00
Jim Laskey d812a2e449 Simple edits; remove unimplimented cases and clarify long haul SLU cases. 
llvm-svn: 23788
 2005-10-18 16:59:23 +00:00
Chris Lattner 5a2fb9787b Fix the JIT encoding of LWA, LD, STD, and STDU. 
llvm-svn: 23787
 2005-10-18 16:51:22 +00:00
Jim Laskey c6533006c8 Checking in first round of scheduling tablegen files. Not tied in as yet. 
llvm-svn: 23786
 2005-10-18 16:23:40 +00:00
Chris Lattner 53b9c3ad4c add a case 
llvm-svn: 23785
 2005-10-18 06:30:51 +00:00
Nate Begeman e74dfbb9ce Do the right thing and enable 64 bit regs under the control of a subtarget 
option.  Currently the only way to enable this is to specify the
64bitregs mattr flag.  It is never enabled by default on any config yet.

llvm-svn: 23779
 2005-10-18 00:56:42 +00:00
Nate Begeman 0b71e007ef First bits of 64 bit PowerPC stuff, currently disabled. A lot of this is 
purely mechanical.

llvm-svn: 23778
 2005-10-18 00:28:58 +00:00
Nate Begeman 6cca84e43c More PPC32 -> PPC changes, as well as merging some classes that were 
redundant after the change.

llvm-svn: 23759
 2005-10-16 05:39:50 +00:00
Nate Begeman c0896117d3 Remove some dead code now that the dag combiner exists. 
llvm-svn: 23754
 2005-10-15 22:08:02 +00:00
Chris Lattner d869bec4fe Remove some dead code: the ORI/ORIS cases are autogen'd. This makes 
SelectIntImmediateExpr dead.

llvm-svn: 23753
 2005-10-15 22:06:18 +00:00
Chris Lattner 03354280eb prune #includes 
llvm-svn: 23752
 2005-10-15 21:58:54 +00:00
Chris Lattner a52969c8d6 These instructions are now autogenerated 
llvm-svn: 23751
 2005-10-15 21:44:56 +00:00
Chris Lattner 286c1d7cfa Add a pattern for FSQRTS 
llvm-svn: 23750
 2005-10-15 21:44:15 +00:00
Chris Lattner efa382616b remove dead code 
llvm-svn: 23749
 2005-10-15 21:40:12 +00:00
Chris Lattner e33870d154 remove broken SRA/rlwimi case 
llvm-svn: 23746
 2005-10-15 19:04:48 +00:00
Chris Lattner 6f3b954662 Rename PPC32*.h to PPC*.h 
This completes the grand PPC file renaming

llvm-svn: 23745
 2005-10-14 23:59:06 +00:00
Chris Lattner 0aa794ba5b Merge PPCJITInfo.h and PPC32JITInfo.h. Note that the PowerPCJITInfo 
and PPC32JITInfo classes should be merged.

llvm-svn: 23744
 2005-10-14 23:53:41 +00:00
Chris Lattner bfca1ab79d Rename PowerPC*.h to PPC*.h 
llvm-svn: 23743
 2005-10-14 23:51:18 +00:00
Chris Lattner e80bf1b33a Rename PowerPCInstrBuilder.h -> PPC* 
llvm-svn: 23742
 2005-10-14 23:45:43 +00:00
Chris Lattner 2ed745a905 Nuke the PowerPCTargetMachine.h header. Note that the PowerPCTargetMachine 
still should be merged into the PPC32TargetMachine class

llvm-svn: 23741
 2005-10-14 23:44:05 +00:00
Chris Lattner 7503d46feb Rename PowerPC*.td -> PPC*.td 
llvm-svn: 23740
 2005-10-14 23:40:39 +00:00
Chris Lattner f3b97f53b9 These are dead 
llvm-svn: 23739
 2005-10-14 23:38:51 +00:00
Chris Lattner 0921e3bfc1 Eliminate PowerPC.td and PPC32.td, consolidating them into PPC.td 
llvm-svn: 23738
 2005-10-14 23:37:35 +00:00
Chris Lattner 09cd9e7661 Like the comment says... 
llvm-svn: 23737
 2005-10-14 22:48:24 +00:00
Chris Lattner 2121f3ca50 Nuke PowerPCInstrFormats.h, its contents are dead. Remove the definitions 
from the .td file that correspond to it

llvm-svn: 23736
 2005-10-14 22:44:13 +00:00
Nate Begeman 9d7008b08d Properly split f32 and f64 into separate register classes for scalar sse fp 
fixing a bunch of nasty hackery

llvm-svn: 23735
 2005-10-14 22:06:00 +00:00
Nate Begeman c41e1be2e8 Remove an unnecsesary file. PPC32 and PPC64 share architected registers. 
We will decide with subtarget support whether we ever use an i64 register
class.

llvm-svn: 23734
 2005-10-14 18:58:46 +00:00
Chris Lattner 56f31f5408 add the integer truncate/extension operations 
llvm-svn: 23733
 2005-10-14 06:40:20 +00:00
Chris Lattner 7d9f719d42 These are now autogenerated 
llvm-svn: 23731
 2005-10-14 06:26:29 +00:00
Chris Lattner 9c0d3c5932 Add patterns for FP round/extend 
llvm-svn: 23727
 2005-10-14 04:55:50 +00:00
Chris Lattner 6e83cbf7f3 add a new SDTCisOpSmallerThanOp type constraint, and implement fround/fextend in terms of it 
llvm-svn: 23726
 2005-10-14 04:55:10 +00:00
Chris Lattner d59a57a8d5 These definitions have been moved to common code. 
llvm-svn: 23681
 2005-10-10 06:01:00 +00:00
Chris Lattner d83571bbf2 Pull DAG ISel generation nodes out of the PowerPC backend to where they 
can be used by other targets.  For those targets that want to use it,
have at.  :)

llvm-svn: 23680
 2005-10-10 06:00:30 +00:00
Andrew Lenharth 1dfb85c7af This seems useful from the original patch that added the function. If there is a reason it is not useful on a RISC type target, let me know and I will pull it out 
llvm-svn: 23676
 2005-10-09 20:11:35 +00:00
Chris Lattner 89c7fa22b1 Disable formation of rlwinm instructions from SRA bases. This fixes 
the 177.mesa failure from last night, and fixes the
CodeGen/PowerPC/2005-10-08-ArithmeticRotate.ll regression test I added.
If this code cannot be fixed, it should be removed for good, but I'll leave
it to Nate to decide its fate.

llvm-svn: 23670
 2005-10-09 05:36:17 +00:00
Nate Begeman 967ce74980 Remove another unused file. Preparing for the great "enable i64 on ppc32" 
merge, and using subtarget info for ptr size.

llvm-svn: 23668
 2005-10-08 01:32:34 +00:00
Nate Begeman af72457fc4 Remove a file that is no longer used 
llvm-svn: 23666
 2005-10-08 01:21:27 +00:00
Chris Lattner dae96f8881 When preselecting, favor things that have low depth to select first. This 
is faster and uses less stack space.  This reduces our stack requirement
enough to compile sixtrack, and though it's a hack, should be enough until
we switch to iterative isel

llvm-svn: 23664
 2005-10-07 22:10:27 +00:00
Chris Lattner e373592258 Fix a CQ regression from my patch to split F32/F64 into seperate register 
classes on PPC.  We were emitting fmr instructions to do fp extensions, which
weren't getting coallesced.  This fixes Regression/CodeGen/PowerPC/fpcopy.ll

llvm-svn: 23654
 2005-10-07 05:00:52 +00:00
Chris Lattner cd8b421799 Fix CodeGen/Generic/bool-to-double.ll 
llvm-svn: 23652
 2005-10-07 04:50:48 +00:00
Chris Lattner 318622fb9f Pull out Call, reducing stack frame size from 6032 bytes to 5184 bytes. 
llvm-svn: 23650
 2005-10-06 19:07:45 +00:00
Chris Lattner 491b8294f4 Pull out setcc, this reduces stack frame size from 7520 to 6032 bytes 
llvm-svn: 23649
 2005-10-06 19:03:35 +00:00
Chris Lattner 502a36935e Pull two more methods out, reducing stack frame size from 8224 -> 7520 bytes 
llvm-svn: 23648
 2005-10-06 18:56:10 +00:00
Chris Lattner 259e6c76f2 Add a recursive-iterative hybrid stage to attempt to reduce stack space, this 
helps but not enough.

Start pulling cases out of PPC32DAGToDAGISel::Select.  With GCC 4, this function
required 8512 bytes of stack space for each invocation (GCC 3 required less
than 700 bytes).  Pulling this first function out gets us down to 8224.  More
to come :(

llvm-svn: 23647
 2005-10-06 18:45:51 +00:00
Andrew Lenharth e4c91fc9e8 This is suppose to work now 
llvm-svn: 23644
 2005-10-06 16:54:29 +00:00
Andrew Lenharth 332df13b9e remove VAX compatibility instruction, we will never use this 
llvm-svn: 23643
 2005-10-06 16:53:32 +00:00
Chris Lattner 05da0d966e silence some warnings 
llvm-svn: 23637
 2005-10-05 17:15:09 +00:00
Chris Lattner d1a5bc8dbd Add a forward def 
llvm-svn: 23621
 2005-10-04 05:09:20 +00:00
Chris Lattner afef68baff Speed up the asm printer a lot by not printing formatted LLVM asm output 
for globals

llvm-svn: 23608
 2005-10-03 07:08:36 +00:00
Chris Lattner 9982da2703 silence some warnings 
llvm-svn: 23594
 2005-10-02 16:29:36 +00:00
Chris Lattner c0e655b65d silence a warning 
llvm-svn: 23593
 2005-10-02 16:27:59 +00:00
Chris Lattner 68303a78ff add patterns for float binops and fma ops 
llvm-svn: 23592
 2005-10-02 07:46:28 +00:00
Chris Lattner 98da1d9910 Sort the cpu and features table, so that the alpha backend doesn't fail EVERY 
compile with an assertion that the tables are not sorted!

llvm-svn: 23591
 2005-10-02 07:13:52 +00:00
Chris Lattner 3734d204b8 another solution to the fsel issue. Instead of having 4 variants, just force 
the comparison to be 64-bits.  This is fine because extensions from float
to double are free.

llvm-svn: 23589
 2005-10-02 07:07:49 +00:00
Chris Lattner 9e98672962 fsel can take a different FP type for the comparison and for the result. As such 
split the FSEL family into 4 things instead of just two.

llvm-svn: 23588
 2005-10-02 06:58:23 +00:00
Chris Lattner a17e6c486c fix an f32/f64 type mismatch 
llvm-svn: 23587
 2005-10-02 06:37:13 +00:00
Chris Lattner 4155ae0f74 Adjust to change in ctor 
llvm-svn: 23585
 2005-10-02 06:23:51 +00:00
Chris Lattner 5ab9d42bb4 Minor tweak to the branch selector. When emitting a two-way branch, and if 
we're in a single-mbb loop, make sure to emit the backwards branch as the
conditional branch instead of the uncond branch.  For example, emit this:

LBBl29_z__44:
        stw r9, 0(r15)
        stw r9, 4(r15)
        stw r9, 8(r15)
        stw r9, 12(r15)
        addi r15, r15, 16
        addi r8, r8, 1
        cmpw cr0, r8, r28
        ble cr0, LBBl29_z__44
        b LBBl29_z__48                   *** NOT PART OF LOOP

Instead of:

LBBl29_z__44:
        stw r9, 0(r15)
        stw r9, 4(r15)
        stw r9, 8(r15)
        stw r9, 12(r15)
        addi r15, r15, 16
        addi r8, r8, 1
        cmpw cr0, r8, r28
        bgt cr0, LBBl29_z__48            *** PART OF LOOP!
        b LBBl29_z__44

The former sequence has one fewer dispatch group for the loop body.

llvm-svn: 23582
 2005-10-01 23:06:26 +00:00
Chris Lattner 6f4dc51d6f like the comment says, enable this 
llvm-svn: 23581
 2005-10-01 23:02:40 +00:00
Chris Lattner 8713ebf37c fix typo 
llvm-svn: 23578
 2005-10-01 02:51:36 +00:00
Chris Lattner d3eee1a09b Modify the ppc backend to use two register classes for FP: F8RC and F4RC. 
These are used to represent float and double values, and the two regclasses
contain the same physical registers.

llvm-svn: 23577
 2005-10-01 01:35:02 +00:00
Jim Laskey f61232354f Should be using flag and not chain. 
llvm-svn: 23572
 2005-09-30 23:43:37 +00:00
Nate Begeman fbfad0b565 Remove some now-dead code. 
llvm-svn: 23571
 2005-09-30 21:28:27 +00:00
Andrew Lenharth 49e48f6234 subtarget support for CIX and FIX extentions (the only 2 I care about right now) 
llvm-svn: 23569
 2005-09-30 20:24:38 +00:00
Chris Lattner c9f4219cfc Rename MRegisterDesc -> TargetRegisterDesc for consistency 
llvm-svn: 23564
 2005-09-30 17:49:27 +00:00