maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
78,039 Commits 23 Branches 0 Tags 2.2 GiB
Commit Graph

57176 Commits

Author SHA1 Message Date
Chris Lattner 064e926362 Remove special cases for [LM]FENCE, MONITOR and MWAIT from 
encoder and decoder by using new MRM_ forms.

llvm-svn: 96048
 2010-02-12 23:54:57 +00:00
Chris Lattner 34749d879d add some disassemble testcases for weird instructions 
llvm-svn: 96045
 2010-02-12 23:46:48 +00:00
Sean Callanan dde9c12307 Reworked the Intel disassembler to support instructions 
whose opcodes extend into the ModR/M field using the
Form field of the instruction rather than by special
casing each instruction.  Commented out the special
casing of VMCALL, which is the first instruction to use
this special form.  While I was in the neighborhood,
added a few comments for people modifying the Intel
disassembler. 

llvm-svn: 96043
 2010-02-12 23:39:46 +00:00
Chris Lattner 1e827fd8ca implement the rest of correct x86-64 encoder support for 
rip-relative addresses, and add a testcase.

llvm-svn: 96040
 2010-02-12 23:24:09 +00:00
Dale Johannesen 626b79d6a6 Add the problem I just hacked around in 96015/96020. 
The solution there produces correct code, but is seriously
deficient in several ways.

llvm-svn: 96039
 2010-02-12 23:16:24 +00:00
Chris Lattner 741580a5bd give MCCodeEmitters access to the current MCContext. 
llvm-svn: 96038
 2010-02-12 23:12:47 +00:00
Jeffrey Yasskin 2d36eb6e18 Make JIT::runFunction clean up the generated stub function. 
Patch by Shivram K!

llvm-svn: 96037
 2010-02-12 23:05:31 +00:00
Chris Lattner 4ad96055fb implement infrastructure to support fixups for rip-rel 
addressing.  This isn't complete because I need an MCContext
to generate new MCExprs.

llvm-svn: 96036
 2010-02-12 23:00:36 +00:00
Johnny Chen 29a9103ee6 Add YIELD, WFE, WFI, and SEV instructions for disassembly only. 
Plus add two formats: MiscFrm and ThumbMiscFrm.  Some of the for disassembly
only instructions are changed from Pseudo Format to MiscFrm Format.

llvm-svn: 96032
 2010-02-12 22:53:19 +00:00
Chris Lattner d18320361f pull the rip-relative addressing mode case up early. 
llvm-svn: 96031
 2010-02-12 22:47:55 +00:00
Chris Lattner 6c1c0141be fixme resolved! 
llvm-svn: 96029
 2010-02-12 22:39:06 +00:00
Chris Lattner 0055e75249 start producing reloc_pcrel_4byte/reloc_pcrel_1byte for calls. 
llvm-svn: 96028
 2010-02-12 22:36:47 +00:00
Bob Wilson e464c658ce Fix a comment typo. 
llvm-svn: 96027
 2010-02-12 22:34:54 +00:00
Chris Lattner 12455ca03d enhance the immediate field encoding to know whether the immediate 
is pc relative or not, mark call and branches as pcrel.

llvm-svn: 96026
 2010-02-12 22:27:07 +00:00
Evan Cheng 439bda9d3f Load / store multiple instructions cannot load / store sp. Sorry, can't come up with a reasonable test case. 
llvm-svn: 96023
 2010-02-12 22:17:21 +00:00
Dale Johannesen cb39340b81 This should have gone in with 26015, see comments there. 
llvm-svn: 96020
 2010-02-12 22:00:40 +00:00
Johnny Chen dc2051c802 Add halfword multiply accumulate long SMLALBB/BT/TB/TT for disassembly only. 
llvm-svn: 96019
 2010-02-12 21:59:23 +00:00
Chris Lattner 486483ac95 doxygenize some comments, patch by Peter Collingbourne! 
llvm-svn: 96018
 2010-02-12 21:54:28 +00:00
Dale Johannesen 26062150fa When save/restoring CR at prolog/epilog, in a large 
stack frame, the prolog/epilog code was using the same
register for the copy of CR and the address of the save slot.  Oops.
This is fixed here for Darwin, sort of, by reserving R2 for this case.
A better way would be to do the store before the decrement of SP,
which is safe on Darwin due to the red zone.

SVR4 probably has the same problem, but I don't know how to fix it;
there is no red zone and R2 is already used for something else.
I'm going to leave it to someone interested in that target.

Better still would be to rewrite the CR-saving code completely;
spilling each CR subregister individually is horrible code.

llvm-svn: 96015
 2010-02-12 21:35:34 +00:00
Chris Lattner 392be58cad Add support for a union type in LLVM IR. Patch by Talin! 
llvm-svn: 96011
 2010-02-12 20:49:41 +00:00
Johnny Chen bdf1b9520c Add SWP (Swap) and SWPB (Swap Byte) for disassembly only. 
llvm-svn: 96010
 2010-02-12 20:48:24 +00:00
Evan Cheng 545d36019b Also recognize armv6t2-* and armv5te-* triplets. 
llvm-svn: 96008
 2010-02-12 20:39:35 +00:00
Dan Gohman 1a8674e60b Fix a case of mismatched types in an Add that turned up in 447.dealII. 
llvm-svn: 96007
 2010-02-12 20:39:25 +00:00
Evan Cheng 9aa30fbe02 Add ARM bitcode file magic. 
llvm-svn: 96006
 2010-02-12 20:13:44 +00:00
Dan Gohman 2b75de97c0 Reapply 95979, a compile-time speedup, now that the bug it exposed is fixed. 
llvm-svn: 96005
 2010-02-12 19:35:25 +00:00
Dan Gohman 363f847ec6 Fix this code to avoid dereferencing an end() iterator in 
offset distributions it doesn't expect.

llvm-svn: 96002
 2010-02-12 19:20:37 +00:00
Johnny Chen cf20cbec49 Add CPS, MRS, MRSsys, MSR, MSRsys for disassembly only. 
llvm-svn: 95999
 2010-02-12 18:55:33 +00:00
Dale Johannesen 30d99f4b9b Rewrite handling of DBG_VALUE; previous algorithm 
didn't handle
X =
Y<dead> = use X
DBG_VALUE(X)
I was hoping to avoid this approach as it's slower,
but I don't think it can be done.

llvm-svn: 95996
 2010-02-12 18:40:17 +00:00
Chris Lattner 75879be9d8 1. modernize the constantmerge pass, using densemap/smallvector. 
2. don't bother trying to merge globals in non-default sections,
   doing so is quite dubious at best anyway.
3. fix a bug reported by Arnaud de Grandmaison where we'd try to
   merge two globals in different address spaces.

llvm-svn: 95995
 2010-02-12 18:17:23 +00:00
Chris Lattner 554003f481 rename test 
llvm-svn: 95993
 2010-02-12 18:05:00 +00:00
Daniel Dunbar e0b2c69d3c Revert "Reverse the order for collecting the parts of an addrec. The order", it 
is breaking llvm-gcc bootstrap.

llvm-svn: 95988
 2010-02-12 17:27:08 +00:00
Anton Korobeynikov b9ce3cc458 Testcases for recent stdcall / fastcall mangling improvements 
llvm-svn: 95982
 2010-02-12 15:29:13 +00:00
Anton Korobeynikov c3c357006e Setup correct data layout to match gcc's expectations on mingw32. 
llvm-svn: 95981
 2010-02-12 15:28:56 +00:00
Anton Korobeynikov c9276dfe04 Cleanup stdcall / fastcall name mangling. 
This should fix alot of problems we saw so far, e.g. PRs 5851 & 2936

llvm-svn: 95980
 2010-02-12 15:28:40 +00:00
Dan Gohman 0194f58047 Reverse the order for collecting the parts of an addrec. The order 
doesn't matter, except that ScalarEvolution tends to need less time
to fold the results this way.

llvm-svn: 95979
 2010-02-12 11:08:26 +00:00
Dan Gohman 45774ce0ad Reapply the new LoopStrengthReduction code, with compile time and 
bug fixes, and with improved heuristics for analyzing foreign-loop
addrecs.

This change also flattens IVUsers, eliminating the stride-oriented
groupings, which makes it easier to work with.

llvm-svn: 95975
 2010-02-12 10:34:29 +00:00
Lang Hames c7ef4cc9fc * Updated the cost matrix normalization proceedure to better handle infinite costs. 
* Enabled R1/R2 application for nodes with infinite spill costs in the Briggs heuristic (made
safe by the changes to the normalization proceedure).
* Removed a redundant header.

llvm-svn: 95973
 2010-02-12 09:43:37 +00:00
Evan Cheng 0e4df63bd5 Update test to match 95961. 
llvm-svn: 95971
 2010-02-12 07:48:46 +00:00
Evan Cheng 993bd1b7da Test for 95961. 
llvm-svn: 95962
 2010-02-12 02:35:03 +00:00
Chris Lattner f7477e599f add a bunch of mod/rm encoding types for fixed mod/rm bytes. 
This will work better for the disassembler for modeling things
like lfence/monitor/vmcall etc.

llvm-svn: 95960
 2010-02-12 02:06:33 +00:00
Evan Cheng 67e45e1670 Test case for 95958. 
llvm-svn: 95959
 2010-02-12 02:02:23 +00:00
Chris Lattner 44ac89f517 revert r95949, it turns out that adding new prefixes is not a 
great solution for the disassembler, we'll go with "plan b".

llvm-svn: 95957
 2010-02-12 01:55:31 +00:00
Daniel Dunbar 692d06fb77 MC: Fix bug where trailing tied operands were forgotten; the X86 assembler 
matcher is now free of implicit operands!
 - Still need to clean up the code now that we don't to worry about implicit
   operands, and to make it a hard error if an instruction fails to specify all
   of its operands for some reason.

llvm-svn: 95956
 2010-02-12 01:46:54 +00:00
Johnny Chen 905a2d7727 Added coprocessor Instructions CDP, CDP2, MCR, MCR2, MRC, MRC2, MCRR, MCRR2, 
MRRC, MRRc2.  For disassembly only.

llvm-svn: 95955
 2010-02-12 01:44:23 +00:00
Bob Wilson 0827e040e0 Add a new pass on machine instructions to optimize away PHI cycles that 
reduce down to a single value.  InstCombine already does this transformation
but DAG legalization may introduce new opportunities.  This has turned out to
be important for ARM where 64-bit values are split up during type legalization:
InstCombine is not able to remove the PHI cycles on the 64-bit values but
the separate 32-bit values can be optimized.  I measured the compile time 
impact of this (running llc on 176.gcc) and it was not significant.

llvm-svn: 95951
 2010-02-12 01:30:21 +00:00
Daniel Dunbar d7e9212e2d X86: Fix definition for RCL/RCR.*m? operations -- they were getting represented 
with "tied memory operands", which is wrong.

llvm-svn: 95950
 2010-02-12 01:22:03 +00:00
Chris Lattner 336f9abb45 add another bit of space for new kinds of instruction prefixes. 
llvm-svn: 95949
 2010-02-12 01:15:16 +00:00
Nate Begeman c780af6471 Add a missing pattern for movhps so that we get: 
movq	(%ecx,%edx,2), %xmm2
movhps	(%ecx,%eax,2), %xmm2

rather than:

movq     (%eax, %edx, 2), %xmm2		
movq     (%eax, %ebx, 2), %xmm3		
movlhps  %xmm3, %xmm2			

Testcase forthcoming.

llvm-svn: 95948
 2010-02-12 01:10:45 +00:00
Chris Lattner 1572e760bc fix the encodings of monitor and mwait, which were completely 
busted in both encoders.  I'm not bothering to fix it in the
old one at this point.

llvm-svn: 95947
 2010-02-12 01:06:22 +00:00
Chris Lattner 62f50dad8d improve support for minix, PR6280, patch by 
Kees van Reeuwijk!

llvm-svn: 95946
 2010-02-12 00:37:46 +00:00