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74 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen ed6c0408fa Remove variable_ops from call instructions in most targets. 
Call instructions are no longer required to be variadic, and
variable_ops should only be used for instructions that encode a variable
number of arguments, like the ARM stm/ldm instructions.

llvm-svn: 160189
 2012-07-13 20:44:29 +00:00
Jia Liu b22310fda6 Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 
llvm-svn: 150878
 2012-02-18 12:03:15 +00:00
Chris Lattner 2a0a3b43d7 Flag -> Glue, the ongoing saga 
llvm-svn: 122513
 2010-12-23 18:28:41 +00:00
Chris Lattner cfed96a410 fix breakage from r98938 by correctly marking msp430 calls as variadic. 
Patch by Ben Ransford!

llvm-svn: 106722
 2010-06-24 06:46:50 +00:00
Eric Christopher fa1b54d26e Remove isTwoAddress from MSP430. 
llvm-svn: 106455
 2010-06-21 20:07:30 +00:00
Eric Christopher 0ca648d758 Make 80-column. 
llvm-svn: 106448
 2010-06-21 18:56:55 +00:00
Anton Korobeynikov 319d71f44f Do folding for indirect branches, where possible 
llvm-svn: 102836
 2010-05-01 12:28:21 +00:00
Anton Korobeynikov ebbdfef2fc Implement indirect branches on MSP430 
llvm-svn: 102835
 2010-05-01 12:04:32 +00:00
Anton Korobeynikov 6fbff44893 Long branch target oparands are not pc-rel. 
This should fix PR6603.

llvm-svn: 102834
 2010-05-01 12:04:22 +00:00
Dan Gohman 8c5d683aa9 The mayHaveSideEffects flag is no longer used. 
llvm-svn: 97348
 2010-02-27 23:47:46 +00:00
Chris Lattner b06015aa69 move target-independent opcodes out of TargetInstrInfo 
into TargetOpcodes.h.  #include the new TargetOpcodes.h
into MachineInstr.  Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the 
codebase.

llvm-svn: 95687
 2010-02-09 19:54:29 +00:00
Anton Korobeynikov ce52fd5f93 Add branch relaxation pass (shamelessly stolen from PPC). 
llvm-svn: 93554
 2010-01-15 21:19:05 +00:00
Anton Korobeynikov 71471293a5 Provide instruction sizes & encoding. No opcodes yet (but not needed so far). 
llvm-svn: 93553
 2010-01-15 21:18:39 +00:00
Anton Korobeynikov 93a7d026a8 Enable bit tests and setcc stuff. 
llvm-svn: 93552
 2010-01-15 21:18:18 +00:00
Anton Korobeynikov cefa7addc8 Fix cmp emission on msp430: we definitely should turn stuff like 
"icmp lhs, rhs" into "cmp rhs, lhs". This should fix PR5979.

llvm-svn: 93496
 2010-01-15 01:29:49 +00:00
Anton Korobeynikov d8f320947f Implement variable-width shifts. 
No testcase yet - it seems we're exposing generic codegen bugs.

llvm-svn: 91221
 2009-12-12 18:55:37 +00:00
Anton Korobeynikov dd2b2f8cba Reduce (cmp 0, and_su (foo, bar)) into (bit foo, bar). This saves extra instruction. Patch inspired by Brian Lucas! 
llvm-svn: 90819
 2009-12-08 01:03:04 +00:00
Anton Korobeynikov b4be8ce537 Initial codegen support for MSP430 ISRs 
llvm-svn: 90739
 2009-12-07 02:27:53 +00:00
Anton Korobeynikov 3a31644c7a Drop unsupported imm operands 
llvm-svn: 89573
 2009-11-22 01:13:54 +00:00
Dan Gohman 9fd22f68f2 Set isBarrier = 1 on return instructions, as they are control barriers. 
llvm-svn: 86851
 2009-11-11 18:11:07 +00:00
Anton Korobeynikov 700c4ab3f9 Add and-not (bic) patterns. Based heavily on patch by Brian Lucas! 
llvm-svn: 86471
 2009-11-08 15:33:12 +00:00
Anton Korobeynikov e92c508764 Move OR patterns upper to all logical stuff. No functionality change. 
llvm-svn: 86470
 2009-11-08 15:32:44 +00:00
Anton Korobeynikov a404d61c8e Some nice peephole patterns. Based on patch by Brian Lucas! 
llvm-svn: 86469
 2009-11-08 15:32:28 +00:00
Anton Korobeynikov fd9a893cab Print tab before operand of jcc 
llvm-svn: 86468
 2009-11-08 15:32:11 +00:00
Anton Korobeynikov 4ca8d3a6a6 Fix invalid operand updates & implement post-inc memory operands 
llvm-svn: 86466
 2009-11-08 14:27:38 +00:00
Anton Korobeynikov cf84ab5043 First try of the post-inc operands handling... Not fully worked, though :( 
llvm-svn: 86386
 2009-11-07 17:15:25 +00:00
Anton Korobeynikov d3c8319f48 Add some dummy support for post-incremented loads 
llvm-svn: 86385
 2009-11-07 17:15:06 +00:00
Dan Gohman 453d64c9f5 Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a 
bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.

llvm-svn: 85517
 2009-10-29 18:10:34 +00:00
Anton Korobeynikov cc55b9086d Distinguish between pcrel imm operands and 'normal' ones. Fix fixes gross weirdness of asmprinting. 
llvm-svn: 84710
 2009-10-21 00:13:25 +00:00
Anton Korobeynikov 4b38ce9f25 Add missed mem-mem move patterns 
llvm-svn: 83812
 2009-10-11 23:03:53 +00:00
Anton Korobeynikov a58a3f930a Implement proper asmprinting for the globals. This eliminates bogus "call" modifier and also adds support for offsets wrt globals. 
llvm-svn: 83784
 2009-10-11 19:14:02 +00:00
Anton Korobeynikov 5b8826b4da It seems that OR operation does not affect status reg at all. 
Remove impdef of SRW. This fixes PR4779

llvm-svn: 83739
 2009-10-10 22:17:47 +00:00
Anton Korobeynikov cb781cfe81 Special constants as destinations does not work as expected - drop the patterns. 
llvm-svn: 78191
 2009-08-05 14:42:00 +00:00
Anton Korobeynikov 6b5523aec2 Typo 
llvm-svn: 71975
 2009-05-17 10:15:22 +00:00
Anton Korobeynikov 3c8e0c52d7 Add imm-reg and imm-mem patters for cmp on msp430 
(imm is allowed to be source operand, not dest...)

llvm-svn: 71393
 2009-05-10 14:49:00 +00:00
Anton Korobeynikov c3e1b392ae Add 8 bit select 
llvm-svn: 71235
 2009-05-08 18:50:26 +00:00
Anton Korobeynikov 4ff60e0cc2 Handle implicit zext in a better way. Shamelessly stolen from x86 backend. 
Thanks for Dan Gohman for suggestion!

llvm-svn: 70782
 2009-05-03 15:50:18 +00:00
Anton Korobeynikov 47fcd72e24 Make handling of conditional stuff much more straightforward 
llvm-svn: 70767
 2009-05-03 13:19:09 +00:00
Anton Korobeynikov dedfa00ba1 Temporary disable imm patterns for cmp. Actually, all cmp-related stuff (select_cc, setcc, br_cc). needs to be rethought 
llvm-svn: 70766
 2009-05-03 13:18:50 +00:00
Anton Korobeynikov f3a6bc8562 Add 8bit shifts 
llvm-svn: 70759
 2009-05-03 13:16:37 +00:00
Anton Korobeynikov 61763b532a Handle logical shift right (at least I hope so :) ) 
llvm-svn: 70758
 2009-05-03 13:16:17 +00:00
Anton Korobeynikov 20a91130ce Handle anyext 
llvm-svn: 70757
 2009-05-03 13:15:57 +00:00
Anton Korobeynikov 4b0a0f18fb Implement bswap 
llvm-svn: 70753
 2009-05-03 13:15:03 +00:00
Anton Korobeynikov ba0e81d4b2 Properly handle ExternalSymbol's 
llvm-svn: 70752
 2009-05-03 13:14:46 +00:00
Anton Korobeynikov 0da755ee3e Provide addc and subc 
llvm-svn: 70748
 2009-05-03 13:13:34 +00:00
Anton Korobeynikov a3f7a83ad8 Add left shift 
llvm-svn: 70747
 2009-05-03 13:13:17 +00:00
Anton Korobeynikov aa43d0b182 Add direct branch 
llvm-svn: 70746
 2009-05-03 13:12:58 +00:00
Anton Korobeynikov 24bfb51416 It's error-prone to maintain two separate variants of asmprinting stuff, one of which is even used. Drop second (aka 'intel') variant of operands. It can be added later, if needed. 
llvm-svn: 70745
 2009-05-03 13:12:37 +00:00
Anton Korobeynikov b6321e15f7 Lower select with custom inserted and make condjumps generic 
llvm-svn: 70744
 2009-05-03 13:12:23 +00:00
Anton Korobeynikov 962720129d Add first draft for conditions, conditional branches, etc 
llvm-svn: 70743
 2009-05-03 13:12:06 +00:00