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Author SHA1 Message Date
Chris Lattner a91a563530 Previously, all operands to Constant were themselves constant. 
In the new world order, BlockAddress can have a BasicBlock operand.
This doesn't permute much, because if you have a ConstantExpr (or
anything more specific than Constant) we still know the operand has
to be a Constant.

llvm-svn: 85375
 2009-10-28 05:14:34 +00:00
Evan Cheng 4a609f3cef Use fconsts and fconstd to materialize small fp constants. 
llvm-svn: 85362
 2009-10-28 01:44:26 +00:00
Evan Cheng 83896a59e1 Add a second ValueType argument to isFPImmLegal. 
llvm-svn: 85361
 2009-10-28 01:43:28 +00:00
Dan Gohman 9c6bc1f563 Update SystemZ to use PSW following the way x86 uses EFLAGS. Besides 
eliminating a use of MVT::Flag, this is needed for an upcoming CodeGen
change.

This unfortunately requires SystemZ to switch to the list-burr
scheduler, in order to handle the physreg defs properly, however
that's what LLVM has available at this time.

llvm-svn: 85357
 2009-10-28 00:55:57 +00:00
Bob Wilson e4b80c9bee Add an indirect branch pattern for ARM. Testcase will be coming soon. 
llvm-svn: 85355
 2009-10-28 00:37:03 +00:00
Chris Lattner d04cb6d0fa rename indbr -> indirectbr to appease the residents of #llvm. 
llvm-svn: 85351
 2009-10-28 00:19:10 +00:00
Bob Wilson 9693f9d465 Record CodeGen optimization level in the BranchFolding pass so that we can 
use it to control tail merging when there is a tradeoff between performance
and code size.  When there is only 1 instruction in the common tail, we have
been merging.  That can be good for code size but is a definite loss for
performance.  Now we will avoid tail merging in that case when the
optimization level is "Aggressive", i.e., "-O3".  Radar 7338114.

Since the IfConversion pass invokes BranchFolding, it too needs to know
the optimization level.  Note that I removed the RegisterPass instantiation
for IfConversion because it required a default constructor.  If someone
wants to keep that for some reason, we can add a default constructor with
a hard-wired optimization level.

llvm-svn: 85346
 2009-10-27 23:49:38 +00:00
Bill Wendling 2e5198ff09 Add new note. 
llvm-svn: 85341
 2009-10-27 23:30:07 +00:00
Jim Grosbach 5607d2cb54 Enable virtual register based frame index scavenging by default for ARM & T2. 
llvm-svn: 85335
 2009-10-27 22:52:29 +00:00
Bill Wendling fd2730ee8c Move and clarify note. 
llvm-svn: 85334
 2009-10-27 22:48:31 +00:00
Jim Grosbach c1403a0024 Infrastructure for dynamic stack realignment on ARM. For now, this is off by 
default behind a command line option. This will enable better performance for
vectors on NEON enabled processors.

llvm-svn: 85333
 2009-10-27 22:45:39 +00:00
Bill Wendling 2974f63cb5 Note corrected. 
llvm-svn: 85332
 2009-10-27 22:43:24 +00:00
Bill Wendling cd4d148040 Modify note. 
llvm-svn: 85331
 2009-10-27 22:40:45 +00:00
Bill Wendling a205402c16 Add a note. 
llvm-svn: 85329
 2009-10-27 22:34:43 +00:00
Chris Lattner e8628a0206 cppbackend support for indbr 
llvm-svn: 85312
 2009-10-27 21:24:48 +00:00
Chris Lattner 42c979e8d3 CBE support for indbr. 
llvm-svn: 85311
 2009-10-27 21:21:06 +00:00
Johnny Chen cde65ec581 Similar to r85280, do not clear the "S" bit for RSBri and RSBrs. 
llvm-svn: 85299
 2009-10-27 20:51:49 +00:00
Johnny Chen 4f36affe5f Set condition code bits of BL and BLr9 to 0b1110 (ALways) to distinguish between 
BL_pred and BLr9_pred.

llvm-svn: 85297
 2009-10-27 20:45:15 +00:00
Evan Cheng 16993aa30b Do away with addLegalFPImmediate. Add a target hook isFPImmLegal which returns true if the fp immediate can be natively codegened by target. 
llvm-svn: 85281
 2009-10-27 19:56:55 +00:00
Bob Wilson b5044ce5a9 Do not clear the "S" bit for RSCri and RSCrs. They inherit from the "sI" 
instruction format that already takes care of setting this.

llvm-svn: 85280
 2009-10-27 19:52:03 +00:00
Johnny Chen df5dcdaa10 Explicitly specify 0b00, i.e, zero rotation, as the rotate filed (Inst{11-10}) 
for the r/rr fragment of the multiclass AI_unary_rrot/AI_bin_rrot.

llvm-svn: 85271
 2009-10-27 18:44:24 +00:00
Sanjiv Gupta a789f17ffc Remove unnecessary gotos to fall-thru successors. 
llvm-svn: 85257
 2009-10-27 17:40:24 +00:00
Johnny Chen b678a56fef Test commit. Added '.' to the comment line. 
llvm-svn: 85255
 2009-10-27 17:25:15 +00:00
Chris Lattner fb22a85baf apparently the X86 JIT isn't fully contextized, it is still using getGlobalContext() :( 
llvm-svn: 85252
 2009-10-27 17:01:03 +00:00
Rafael Espindola d90d169f9d Correctly align double arguments in the stack. 
llvm-svn: 85235
 2009-10-27 14:09:44 +00:00
Evan Cheng 538984c1c3 Now VFP instructions. 
llvm-svn: 85186
 2009-10-27 00:20:49 +00:00
Evan Cheng b02bdb4552 Change Thumb1 and Thumb2 instructions to separate opcode from operands with a tab instead of a space. 
llvm-svn: 85184
 2009-10-27 00:08:59 +00:00
Evan Cheng 13edef55b6 Change ARM asm strings to separate opcode from operands with a tab instead of a space. 
llvm-svn: 85178
 2009-10-26 23:45:59 +00:00
Victor Hernandez de5ad42aa1 Remove FreeInst. 
Remove LowerAllocations pass.
Update some more passes to treate free calls just like they were treating FreeInst.

llvm-svn: 85176
 2009-10-26 23:43:48 +00:00
Bob Wilson a33fa47141 Try to get ahead of Johnny Chen and pro-actively add some more ARM encoding 
bits.  Johnny, please review -- I do not have a good track record of getting
these right.

llvm-svn: 85173
 2009-10-26 22:59:12 +00:00
Bob Wilson 1de6a1f7d2 Fix ARM encoding typo: Opcod3 is not passed to ASuI parent class. 
Patch by Johnny Chen.

llvm-svn: 85169
 2009-10-26 22:42:13 +00:00
Bob Wilson a6aba77e0a Add more ARM instruction encodings for 's' bit set and "rs" register encoding 
bits.  Patch by Johnny Chen.

llvm-svn: 85167
 2009-10-26 22:34:44 +00:00
Ted Kremenek ce8f626f82 Update CMake files. 
llvm-svn: 85161
 2009-10-26 22:06:01 +00:00
Anton Korobeynikov 0ae1b2961d Revert r85134, it breaks mingw build 
llvm-svn: 85138
 2009-10-26 18:40:24 +00:00
Sanjiv Gupta 752aea6513 Make PIC16 overlay a loadable pass. 
llvm-svn: 85134
 2009-10-26 18:22:59 +00:00
David Goodwin 8370485db9 Break anti-dependence breaking out into its own class. 
llvm-svn: 85127
 2009-10-26 16:59:04 +00:00
Chandler Carruth 56869f22c4 Move DataTypes.h to include/llvm/System, update all users. This breaks the last 
direct inclusion edge from System to Support.

llvm-svn: 85086
 2009-10-26 01:35:46 +00:00
Jim Grosbach 5bde1cbd93 of -> or 
llvm-svn: 85065
 2009-10-25 19:14:48 +00:00
Jim Grosbach 5a9788b979 80-column cleanup 
llvm-svn: 85064
 2009-10-25 18:55:46 +00:00
Sanjiv Gupta b18a46806b Reapply 85006 with a minor fix. 
llvm-svn: 85052
 2009-10-25 08:14:11 +00:00
Evan Cheng 2e7dee5f23 Add ARM getMatchingSuperRegClass to handle S / D / Q cross regclass coalescing. 
llvm-svn: 85049
 2009-10-25 07:53:28 +00:00
Evan Cheng 5d1b849658 Don't forget subreg indices when folding load / store. 
llvm-svn: 85048
 2009-10-25 07:52:27 +00:00
Nick Lewycky 974e12b2d3 Remove includes of Support/Compiler.h that are no longer needed after the 
VISIBILITY_HIDDEN removal.

llvm-svn: 85043
 2009-10-25 06:57:41 +00:00
Nick Lewycky 02d5f77d26 Remove VISIBILITY_HIDDEN from class/struct found inside anonymous namespaces. 
Chris claims we should never have visibility_hidden inside any .cpp file but
that's still not true even after this commit.

llvm-svn: 85042
 2009-10-25 06:33:48 +00:00
Chris Lattner 13b8b56dd4 this is done. 
llvm-svn: 85041
 2009-10-25 06:17:51 +00:00
Nick Lewycky 54d7179a25 Remove ICmpInst::isSignedPredicate which was a reimplementation 
CmpInst::isSigned.

llvm-svn: 85037
 2009-10-25 05:20:17 +00:00
Sanjiv Gupta 9e8d42f295 Revert back 85006 for now as it breaks PIC16 tests. 
llvm-svn: 85008
 2009-10-24 18:19:41 +00:00
Sanjiv Gupta 055c3305a1 Adding support for placing global objects in shared data memory. 
llvm-svn: 85006
 2009-10-24 18:02:44 +00:00
Evan Cheng 46ed1f8341 80 col violation. 
llvm-svn: 84986
 2009-10-24 02:07:42 +00:00
Jim Grosbach e2871d69db Restrict Thumb1 register allocation to low registers, even for instructions that 
can access the hi regs. Our prologue and epilogue code doesn't know how to
properly handle save/restore of the hi regs, so things go badly when we alloc
them.

llvm-svn: 84982
 2009-10-24 00:19:24 +00:00
Jim Grosbach 22b2c011f9 FIXME no longer applies. R12 and R3 are available for allocation 
llvm-svn: 84977
 2009-10-23 23:07:42 +00:00
Chris Lattner 851193b873 some stuff is done, we still have constantexpr simplification to do. 
llvm-svn: 84943
 2009-10-23 07:00:55 +00:00
Evan Cheng 8b86efefec X86 needs critical path anti-dependency breaking. 
llvm-svn: 84931
 2009-10-23 05:57:35 +00:00
David Goodwin 02ad4cb32e Allow the target to select the level of anti-dependence breaking that should be performed by the post-RA scheduler. The default is none. 
llvm-svn: 84911
 2009-10-22 23:19:17 +00:00
Bob Wilson 9d763cc3f8 Revert 84843. Evan, this was breaking some of the if-conversion tests. 
llvm-svn: 84868
 2009-10-22 16:52:21 +00:00
Benjamin Kramer c77f8634e5 Shift art to the right to keep GCC from complaining about multi-line comments. 
llvm-svn: 84849
 2009-10-22 09:28:49 +00:00
Evan Cheng 3615b9bef3 Move if-conversion before post-regalloc scheduling so the predicated instruction get scheduled properly. 
llvm-svn: 84843
 2009-10-22 06:48:32 +00:00
Evan Cheng 943f4f41f2 Load / store multiple was missing opportunites when the load / store bundles are at the end of the bb. Test case is already in, the bug is exposed by subsequent commit. 
llvm-svn: 84842
 2009-10-22 06:47:35 +00:00
Evan Cheng 5457a96b63 Trim more includes. 
llvm-svn: 84832
 2009-10-22 05:11:00 +00:00
Evan Cheng 344fcd9d61 Trim include. 
llvm-svn: 84831
 2009-10-22 05:08:49 +00:00
Chris Lattner 1448799377 fix warning. 
llvm-svn: 84826
 2009-10-22 03:42:27 +00:00
Evan Cheng 0f55e9ce2e Don't generate sbfx / ubfx with negative lsb field. Patch by David Conrad. 
llvm-svn: 84813
 2009-10-22 00:40:00 +00:00
Anton Korobeynikov f1ad2c618a Use special DAG-to-DAG preprocessing to allow mem-mem instructions to be selected. 
Yay for ASCII graphics!

llvm-svn: 84808
 2009-10-22 00:16:00 +00:00
Jim Grosbach f2e74df12e Missing piece of the ARM frame index post-scavenging conditionalization 
llvm-svn: 84798
 2009-10-21 23:40:56 +00:00
Jim Grosbach 05536f50dc Conditionalize ARM/T2 frame index post-scavenging while working out fixes 
for a few bugs.

llvm-svn: 84791
 2009-10-21 22:59:24 +00:00
Bob Wilson 854530a7dd Most of the NEON shuffle instructions do not support 64-bit element types. 
llvm-svn: 84785
 2009-10-21 21:36:27 +00:00
Anton Korobeynikov b45d621ab1 Revert r84764, it breaks mingw build 
llvm-svn: 84783
 2009-10-21 21:15:18 +00:00
Jim Grosbach a93ca3c637 Improve handling of immediates by splitting 32-bit immediates into two 16-bit 
immediate operands when they will fit into the using instruction.

llvm-svn: 84778
 2009-10-21 20:44:34 +00:00
Anton Korobeynikov 9e92857b38 Add DAG printing for RMW stuff debugging 
llvm-svn: 84776
 2009-10-21 19:18:28 +00:00
Anton Korobeynikov ccfa3e31f7 RMW preprocessing stuff was incorrect. Grab the stuff from x86 backend and disable some tests until it will be clever enough to handle them. 
llvm-svn: 84775
 2009-10-21 19:17:55 +00:00
Anton Korobeynikov 5399c2d05e Implement branch folding 
llvm-svn: 84774
 2009-10-21 19:17:18 +00:00
Anton Korobeynikov 2983dcb1f2 Cosmetic changes, no functionality changes 
llvm-svn: 84773
 2009-10-21 19:16:49 +00:00
Bob Wilson 0db964a3a0 Fix NEON VST2LN instruction encoding. 
Patch by Johnny Chen.

llvm-svn: 84767
 2009-10-21 17:54:01 +00:00
Bob Wilson 87671da29a Revert 84732. It was the wrong fix. 
llvm-svn: 84766
 2009-10-21 17:52:34 +00:00
Sanjiv Gupta c5804f3cb6 Build shared lib instead of an archive. 
llvm-svn: 84764
 2009-10-21 17:27:23 +00:00
Sanjiv Gupta 47ea743618 Add a pass to overlay pic16 data sections for function frame and automatic 
variables. This pass can be invoked by llvm-ld or opt to traverse over the call graph 
to detect what function frames and their automatic variables can be overlaid.
Currently this builds an archive , but needs to be changed to a loadable module.

llvm-svn: 84753
 2009-10-21 10:42:44 +00:00
Evan Cheng 786b15fe12 Match more patterns to movt. 
llvm-svn: 84751
 2009-10-21 08:15:52 +00:00
Chris Lattner 175d04c90f tidy 
llvm-svn: 84738
 2009-10-21 04:10:24 +00:00
Bob Wilson 5b5cb92816 Fix some more NEON instruction encoding problems. 
Thanks to Johnny Chen for discovering the problem.

llvm-svn: 84732
 2009-10-21 02:27:20 +00:00
Bob Wilson bd3650cc84 Leave some NEON instruction encoding bits unspecified instead of setting 
a default value of zero.  This is important for decoding the instructions.
Patch by Johnny Chen, with some changes from me, too.

llvm-svn: 84730
 2009-10-21 02:15:46 +00:00
Chris Lattner bc69313909 IPSCCP is missing stuff. 
llvm-svn: 84725
 2009-10-21 01:10:37 +00:00
Anton Korobeynikov 7099d0c19c Add note 
llvm-svn: 84713
 2009-10-21 00:14:15 +00:00
Anton Korobeynikov e43af4a085 Be crazy and assert in case of unsupported modifier passed. 
llvm-svn: 84712
 2009-10-21 00:13:58 +00:00
Anton Korobeynikov 11074fa73e Handle external symbols 
llvm-svn: 84711
 2009-10-21 00:13:42 +00:00
Anton Korobeynikov cc55b9086d Distinguish between pcrel imm operands and 'normal' ones. Fix fixes gross weirdness of asmprinting. 
llvm-svn: 84710
 2009-10-21 00:13:25 +00:00
Anton Korobeynikov 94ba9c27b0 Add basic block operands & jump kinds 
llvm-svn: 84709
 2009-10-21 00:13:05 +00:00
Anton Korobeynikov 8a06a4e5c8 Ignore all implicit reg operands 
llvm-svn: 84708
 2009-10-21 00:12:44 +00:00
Anton Korobeynikov 196b0e5431 Add a workaround for different memops prefixes 
llvm-svn: 84707
 2009-10-21 00:12:27 +00:00
Anton Korobeynikov 4e32bff382 Checkpoint MCInst printer. We (almostly) able to print global / JT / constpool entries 
llvm-svn: 84706
 2009-10-21 00:12:08 +00:00
Anton Korobeynikov 7fbc0a50d5 Add simple operand printing stuff 
llvm-svn: 84704
 2009-10-21 00:11:27 +00:00
Anton Korobeynikov 6e78029d82 Add experimental MSP430 MCInstLowering stuff 
llvm-svn: 84703
 2009-10-21 00:11:08 +00:00
Anton Korobeynikov daaa2f0c31 Wire up MSP430 printMCInst() method 
llvm-svn: 84702
 2009-10-21 00:10:47 +00:00
Anton Korobeynikov b6e2e4fd50 Add MSP430 InstPrinter stub 
llvm-svn: 84701
 2009-10-21 00:10:30 +00:00
Anton Korobeynikov 13de81ac40 Use proper target data 
llvm-svn: 84700
 2009-10-21 00:10:00 +00:00
Daniel Dunbar a470eac6a1 Fix -Asserts warning. 
llvm-svn: 84687
 2009-10-20 22:10:05 +00:00
Jim Grosbach cccf5084a3 Disable by default while debugging 
llvm-svn: 84669
 2009-10-20 20:31:31 +00:00
Jim Grosbach f3a2b6499e add cmd line opt to disable frame index reuse for ARM and T2. debug aid. 
llvm-svn: 84664
 2009-10-20 20:19:50 +00:00
Dan Gohman 3d9d78463c Following r84485, add Defs = [EFLAGS] to the 32-bit lock instructions too. 
llvm-svn: 84652
 2009-10-20 18:14:49 +00:00
Dan Gohman 4a43e3068d Make TranslateX86CC return COND_INVALID instead of aborting when it 
encounters an OEQ or UNE comparison, and update its callers to check
for this return status and recover. This fixes a problem resulting from
the LowerOperation hooks being called from LegalizeVectorOps, because
LegalizeVectorOps only lowers vectors, so OEQ and UNE comparisons may
still be at large. This fixes PR5092.

llvm-svn: 84640
 2009-10-20 16:22:37 +00:00
Benjamin Kramer 3301207a15 Random #include pruning. 
llvm-svn: 84632
 2009-10-20 11:44:38 +00:00