b376ce0169
Fix t2Int_eh_sjlj_setjmp. Immediate form of orr is a 32-bit instruction. So it should be 22 bytes instead of 20 bytes long.
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llvm-svn: 85965
2009-11-03 23:13:34 +00:00
0410bced1c
fconsts / fconstd immediate should be proceeded with #.
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llvm-svn: 85952
2009-11-03 21:59:33 +00:00
76a4774a0d
Move subtarget check upper for NEON reg-reg fixup pass.
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llvm-svn: 85914
2009-11-03 18:46:11 +00:00
31c2f4701b
Trim unnecessary include.
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llvm-svn: 85878
2009-11-03 07:08:08 +00:00
064c5fef11
For Thumb indirect branches, use "mov pc, reg" which does not switch
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between ARM/Thumb modes and does not require the low bit of the target
address to be set for Thumb.
llvm-svn: 85874
2009-11-03 06:29:56 +00:00
8d681f0471
Fix PR5367. QPR_8 is the super regclass of DPR_8 and SPR_8.
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llvm-svn: 85871
2009-11-03 05:52:54 +00:00
23c009f125
Clean up copyRegToReg.
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llvm-svn: 85870
2009-11-03 05:51:39 +00:00
9e9079371c
Add QPR_8 as a superreg class of SPR_8 and DPR_8.
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llvm-svn: 85869
2009-11-03 05:50:57 +00:00
187cb4f493
Update CMake file.
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llvm-svn: 85861
2009-11-03 04:14:12 +00:00
d195f9e5c3
Turn neon reg-reg moves fixup code into separate pass. This should reduce the compile time.
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llvm-svn: 85850
2009-11-03 01:04:26 +00:00
fbe0256b23
Revert r85049, it is causing PR5367
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llvm-svn: 85847
2009-11-03 00:24:48 +00:00
b389f2a04d
Revert previous change to a comment. The BlockAddresses go in the
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constant pool so they don't get wrapped separately.
llvm-svn: 85844
2009-11-03 00:02:05 +00:00
1c66e8a6b7
Put BlockAddresses into ARM constant pools.
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llvm-svn: 85824
2009-11-02 20:59:23 +00:00
d9dfc2e752
Fix ARMAsmParser::ParseMemoryOffsetReg() where the parameter OffsetRegNum should
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have been passed as a reference.
llvm-svn: 85823
2009-11-02 20:14:39 +00:00
5ac6f244fd
Fix schedule model for BFC.
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llvm-svn: 85809
2009-11-02 17:28:36 +00:00
4c00a524eb
Hyphenate some comments.
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llvm-svn: 85808
2009-11-02 17:10:37 +00:00
433ab09ca3
Add support for BlockAddress values in ARM constant pools.
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llvm-svn: 85806
2009-11-02 16:59:06 +00:00
e90a4aa703
Prune unnecessary include.
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llvm-svn: 85805
2009-11-02 16:58:31 +00:00
115cfc07d5
These are done / no longer care.
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llvm-svn: 85798
2009-11-02 07:58:25 +00:00
f6f1b37f9f
Add an entry.
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llvm-svn: 85797
2009-11-02 07:51:19 +00:00
1708b06c0e
Unbreak ARMBaseRegisterInfo::copyRegToReg.
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llvm-svn: 85787
2009-11-02 04:44:55 +00:00
4d23754b14
Handle splats of undefs properly. This includes the testcase for PR5364 as well.
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llvm-svn: 85767
2009-11-02 00:12:06 +00:00
0f38d989bd
Do not infer the target type for COPY_TO_REGCLASS from dest regclass, this won't work if it can contain several types. Require explicit result type for the node for now. This fixes PR5364.
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PS: It seems that blackfin usage of copy_to_regclass is completely bogus!
llvm-svn: 85766
2009-11-02 00:11:39 +00:00
8cce1eb6aa
64-bit FP loads & stores operate on both NEON and VFP pipelines.
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llvm-svn: 85765
2009-11-02 00:11:06 +00:00
14635da94b
Use NEON reg-reg moves, where profitable. This reduces "domain-cross" stalls, when we used to mix vfp and neon code (the former were used for reg-reg moves)
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llvm-svn: 85764
2009-11-02 00:10:38 +00:00
1a4492be97
Fix a couple more places where we are creating ld / st instructions without memoperands.
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llvm-svn: 85746
2009-11-01 22:04:35 +00:00
43219997b6
Make use of imm12 version of Thumb2 ldr / str instructions more aggressively.
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llvm-svn: 85743
2009-11-01 21:12:51 +00:00
50ba5c3dc2
improve x86 codegen support for blockaddress. We now compile
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the testcase into:
_test1: ## @test1
## BB#0: ## %entry
leaq L_test1_bb6(%rip), %rax
jmpq *%rax
L_test1_bb: ## Address Taken
LBB1_1: ## %bb
movb $1, %al
ret
L_test1_bb6: ## Address Taken
LBB1_2: ## %bb6
movb $2, %al
ret
Note, it is very very strange that BlockAddressSDNode doesn't carry
around TargetFlags. Dan, please fix this.
llvm-svn: 85703
2009-11-01 03:25:03 +00:00
6f29ad9170
Use cbz and cbnz instructions.
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llvm-svn: 85698
2009-10-31 23:46:45 +00:00
5cba8de2c8
vml[as].f32 cause stalls in following advanced SIMD instructions. Avoid using
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them for scalar floating point operations for now.
llvm-svn: 85697
2009-10-31 22:57:36 +00:00
8fe6fd702d
Expand 64-bit logical shift right inline
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llvm-svn: 85687
2009-10-31 21:42:19 +00:00
624fcb286e
Expand 64-bit arithmetic shift right inline
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llvm-svn: 85685
2009-10-31 21:00:56 +00:00
5d994048dd
Expand 64 bit left shift inline rather than using the libcall. For now, this
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is unconditional. Making it still use the libcall when optimizing for size
would be a good adjustment.
llvm-svn: 85675
2009-10-31 19:38:01 +00:00
cdbb70c065
It's safe to remat t2LDRpci; Add PseudoSourceValue to load / store's to enable more machine licm. More changes coming.
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llvm-svn: 85643
2009-10-31 03:39:36 +00:00
8be42bd09f
Updates to the ARM target assembler for llvm-mc per review comments from
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Daniel Dunbar.
- Reordered the fields in the ARMOperand Mem struct to make the struct smaller.
Making bool's into 1 bit fields and put the MCExpr* fields adjacent to each
other.
- Fixed a number of places in ARMAsmParser.cpp so they have doxygen comments.
- Change the name of ARMAsmParser::ParseRegister() to MaybeParseRegister and
added the bool ParseWriteBack parameter.
- Changed ARMAsmParser::ParseMemory() to call MaybeParseRegister().
- Added ARMAsmParser::ParseMemoryOffsetReg to factor out parsing the offset of a
memory operand. And use it for both parsing both preindexed and post indexing
addressing forms in ARMAsmParser::ParseMemory.
- Changed the first argument to ParseShift() to a reference.
- Changed ParseShift() to check for Rrx first and return to reduce nesting.
llvm-svn: 85632
2009-10-30 22:55:57 +00:00
c7415bf536
Add a note about Robert Muth's alternate jump table implementation.
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llvm-svn: 85624
2009-10-30 22:22:46 +00:00
49fa51d936
Fix MachineLICM to use the correct virtual register class when
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unfolding loads for hoisting. getOpcodeAfterMemoryUnfold returns the
opcode of the original operation without the load, not the load
itself, MachineLICM needs to know the operand index in order to get
the correct register class. Extend getOpcodeAfterMemoryUnfold to
return this information.
llvm-svn: 85622
2009-10-30 22:18:41 +00:00
6b00f4b7a8
Fix a comment.
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llvm-svn: 85610
2009-10-30 20:13:25 +00:00
ab7c709f43
This fixes functions like
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void f (int a1, int a2, int a3, int a4, int a5,...)
In ARMTargetLowering::LowerFormalArguments if the function has 4 or
more regular arguments we used to set VarArgsFrameIndex using an
offset of 0, which is only correct if the function has exactly 4
regular arguments.
llvm-svn: 85590
2009-10-30 14:33:14 +00:00
1cf0b03064
Add ARM codegen for indirect branches.
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clang/test/CodeGen/indirect-goto.c runs! (unoptimized)
llvm-svn: 85577
2009-10-30 05:45:42 +00:00
f7c4299312
Initial x86 support for BlockAddresses.
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llvm-svn: 85557
2009-10-30 01:28:02 +00:00
8578068302
Dial back the realignment a bit.
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llvm-svn: 85546
2009-10-30 00:08:40 +00:00
453d64c9f5
Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a
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bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.
llvm-svn: 85517
2009-10-29 18:10:34 +00:00
b352d76480
To get more thorough testing from llc-beta nightly runs, do dynamic stack
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realignment regardless of whether it's strictly necessary.
llvm-svn: 85476
2009-10-29 02:41:21 +00:00
97b9312663
Revert r85346 change to control tail merging by CodeGenOpt::Level.
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I'm going to redo this using the OptimizeForSize function attribute.
llvm-svn: 85426
2009-10-28 20:46:46 +00:00
73789b848d
Add a Thumb BRIND pattern. Change the ARM BRIND assembly to separate the
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opcode and operand with a tab. Check for these instructions in the usual
places.
llvm-svn: 85411
2009-10-28 18:26:41 +00:00
6203c6868f
fconsts and fconstd are obviously re-materializable.
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llvm-svn: 85410
2009-10-28 18:19:56 +00:00
294aea709e
Cleanup now that frame index scavenging via post-pass is working for ARM and Thumb2.
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llvm-svn: 85406
2009-10-28 17:33:28 +00:00
ec6d7c945d
Give ARMISD::EH_SJLJ_LONGJMP and EH_SJLJ_SETJMP names.
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llvm-svn: 85381
2009-10-28 06:55:03 +00:00
f64db3e1d0
X86 palignr intrinsics immediate field is in bits. ISel must transform it into bytes.
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llvm-svn: 85379
2009-10-28 06:30:34 +00:00
Evan Cheng