317332fc2a
Start inferring side effect information more aggressively, and fix many bugs in the
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x86 backend where instructions were not marked maystore/mayload, and perf issues where
instructions were not marked neverHasSideEffects. It would be really nice if we could
write patterns for copy instructions.
I have audited all the x86 instructions down to MOVDQAmr. The flags on others and on
other targets are probably not right in all cases, but no clients currently use this
info that are enabled by default.
llvm-svn: 45829
2008-01-10 07:59:24 +00:00
ba734518c1
add a new bit.
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llvm-svn: 45726
2008-01-07 23:16:55 +00:00
8c69898157
remove a dead field.
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llvm-svn: 45685
2008-01-07 04:57:42 +00:00
a4ce4f6987
rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.
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llvm-svn: 45667
2008-01-06 23:38:27 +00:00
10324d0175
rename isStore -> mayStore to more accurately reflect what it captures.
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llvm-svn: 45656
2008-01-06 08:36:04 +00:00
f3ebc3f3d2
Remove attribution from file headers, per discussion on llvmdev.
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llvm-svn: 45418
2007-12-29 20:36:04 +00:00
939526a930
As per feedback, revised comments to (hopefully) make the different side effect
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flags clearer.
llvm-svn: 45120
2007-12-17 21:02:07 +00:00
cb77f04e1f
Add flags to indicate that there are "never" side effects or that there "may be"
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side effects for machine instructions.
llvm-svn: 45022
2007-12-14 01:48:59 +00:00
6e68381e02
Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always re-materializable and they should not be spilled.
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llvm-svn: 44960
2007-12-12 23:12:09 +00:00
933b5b7e62
Add a flag for indirect branch instructions.
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Target maintainers: please check that the instructions for your target are correctly marked.
llvm-svn: 44012
2007-11-12 07:39:39 +00:00
0644bb865e
Clarify the meaning of '-2' register number
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llvm-svn: 43998
2007-11-11 19:53:50 +00:00
4edfea438a
Use TableGen to emit information for dwarf register numbers.
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This makes DwarfRegNum to accept list of numbers instead.
Added three different "flavours", but only slightly tested on x86-32/linux.
Please check another subtargets if possible,
llvm-svn: 43997
2007-11-11 19:50:10 +00:00
f73fb6261b
Add CopyCost to TargetRegisterClass. This specifies the cost of copying a value
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between two registers in the specific class.
llvm-svn: 42123
2007-09-19 01:35:01 +00:00
3e18e504ae
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead.
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llvm-svn: 41863
2007-09-11 19:55:27 +00:00
cde0ee5221
Add target independent MachineInstr's to represent subreg insert/extract in MBB's. PR1350
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llvm-svn: 40518
2007-07-26 07:48:21 +00:00
ac1591be42
No more noResults.
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llvm-svn: 40132
2007-07-21 00:34:19 +00:00
94b5a80b93
Change instruction description to split OperandList into OutOperandList and
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InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 01:14:50 +00:00
0867337075
Remove clobbersPred.
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llvm-svn: 38500
2007-07-10 18:07:08 +00:00
b039c60889
Do away with ImmutablePredicateOperand.
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llvm-svn: 37959
2007-07-06 23:21:02 +00:00
eaa82198c4
Add OptionalDefOperand to stand for optionally defined result.
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llvm-svn: 37930
2007-07-06 01:00:16 +00:00
756d15ac6f
- Added zero_reg def to stand for register 0.
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- Added two variants of PredicateOperand: ImmutablePredicateOperand, whose predicate does not change after isel; PredicateDefOperand, which represent a predicate defintion operand.
llvm-svn: 37892
2007-07-05 07:09:09 +00:00
e8c1e428f2
Revert the earlier change that removed the M_REMATERIALIZABLE machine
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instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).
llvm-svn: 37728
2007-06-26 00:48:07 +00:00
9e82064924
Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad
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with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.
llvm-svn: 37644
2007-06-19 01:48:05 +00:00
a7ca624028
Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit.
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llvm-svn: 37643
2007-06-19 01:26:51 +00:00
f274efef9f
Add support to tablegen for specifying subregister classes on a per register class basis.
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llvm-svn: 37572
2007-06-13 22:20:15 +00:00
d04409154f
Added clobbersPred.
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llvm-svn: 37466
2007-06-06 10:15:28 +00:00
cc33218607
Added isPredicable bit to class Instruction.
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llvm-svn: 37117
2007-05-16 20:47:01 +00:00
d194a8603d
PredicateOperand can be used as a normal operand for isel.
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llvm-svn: 36947
2007-05-08 21:06:08 +00:00
e6182267d7
Add an "implies" field to features. This indicates that, if the current
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feature is set, then the features in the implied list should be set also.
The opposite is also enforced: if a feature in the implied list isn't set,
then the feature that owns that implies list shouldn't be set either.
llvm-svn: 36756
2007-05-04 20:38:40 +00:00
f65f18b2f9
expose HonorSignDependentRoundingFPMathOption to .td files
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llvm-svn: 36658
2007-05-03 00:27:11 +00:00
27a625a74b
llvm bug #1350 , parts 1, 2, and 3.
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llvm-svn: 36618
2007-05-01 05:57:02 +00:00
ac9fdde7f4
Add sub-registers sets.
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llvm-svn: 36278
2007-04-20 21:13:46 +00:00
461c964d3d
Added isReMaterializable.
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llvm-svn: 35160
2007-03-19 06:22:07 +00:00
fa9227ed54
Add calling convention info
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llvm-svn: 34661
2007-02-27 06:59:52 +00:00
8c8597c4d9
Fix typos in comments.
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llvm-svn: 34456
2007-02-20 20:52:03 +00:00
f9e5445ed4
Make LABEL a builtin opcode.
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llvm-svn: 33537
2007-01-26 14:34:52 +00:00
a557a0028d
Comment.
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llvm-svn: 33114
2007-01-12 07:25:16 +00:00
5c23899c7d
add a new field needed by the code emitter generator.
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llvm-svn: 31768
2006-11-15 22:55:04 +00:00
4905d2c5b4
initial steps to getting the predicate on PPC::BLR right.
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llvm-svn: 31437
2006-11-03 23:52:18 +00:00
4fcc04a32a
remove dead var
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llvm-svn: 31436
2006-11-03 23:50:15 +00:00
7a6a5b9af5
Add constraints to Instruction class.
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llvm-svn: 31332
2006-11-01 00:26:27 +00:00
adcaf294d7
Move the Imp tblgen class from the X86 backend to common code.
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llvm-svn: 30907
2006-10-12 17:49:27 +00:00
c767acd25a
Add code size to target instruction use it as the 3rd isel sorting tie-breaker.
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llvm-svn: 29193
2006-07-19 00:24:41 +00:00
f3cbd7ef31
Added a Flags field to TargetOperandInfo. Currently the only flag is
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M_LOOK_UP_PTR_REG_CLASS which allows the register class of the operand to be
resolved via a callback at runtime.
llvm-svn: 28387
2006-05-18 20:44:26 +00:00
297e1cb10a
Remove CalleeSavedRegisters from class Target.
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llvm-svn: 28377
2006-05-18 00:09:53 +00:00
dcec882286
Remove PointerType from class Target
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llvm-svn: 28368
2006-05-17 21:20:27 +00:00
788db2c812
Replace "../whatever.td" with "whatever.td", so that out-of-tree backends
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can just add lib/Target to TableGen includes.
llvm-svn: 28318
2006-05-16 06:39:36 +00:00
fce45ffcd6
Improve comment, patch provided by Vladimir Prus!
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llvm-svn: 28307
2006-05-15 18:35:02 +00:00
215280d8b9
Update comment.
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llvm-svn: 28283
2006-05-14 02:05:19 +00:00
85e9909755
Put PHI/INLINEASM into the correct namespace.
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llvm-svn: 28037
2006-05-01 17:00:49 +00:00
Chris Lattner