700c4ab3f9
Add and-not (bic) patterns. Based heavily on patch by Brian Lucas!
...
llvm-svn: 86471
2009-11-08 15:33:12 +00:00
4ca8d3a6a6
Fix invalid operand updates & implement post-inc memory operands
...
llvm-svn: 86466
2009-11-08 14:27:38 +00:00
dc2beaa05e
It is invalid to infer the value type from the result #0 of the node
...
since the instruction might use the other result of different type.
llvm-svn: 86462
2009-11-08 12:14:54 +00:00
3a313df69b
x86 vector shuffle cleanup/fixes:
...
1. rename the movhp patfrag to movlhps, since thats what it actually matches
2. eliminate the bogus movhps load and store patterns, they were incorrect. The load transforms are already handled (correctly) by shufps/unpack.
3. revert a recent test change to its correct form.
llvm-svn: 86415
2009-11-07 23:17:15 +00:00
d3c8319f48
Add some dummy support for post-incremented loads
...
llvm-svn: 86385
2009-11-07 17:15:06 +00:00
f93bb39b03
Add 8 bit libcalls and make use of them for msp430
...
llvm-svn: 86384
2009-11-07 17:14:39 +00:00
2a88785685
Initial support for addrmode handling. Tests by Brian Lucas!
...
llvm-svn: 86382
2009-11-07 17:13:35 +00:00
226467d6a6
It turns out that the testcase in question uncovered subreg-handling bug.
...
Add assert in asmprinter to catch such cases and xfail the tests.
PR is to be filled.
llvm-svn: 86375
2009-11-07 15:20:32 +00:00
bd05185ef1
Fix a couple of shuffle patterns to use movhlps instead
...
of movhps as the constraint. Changes optimizations so
update testcases as appropriate as well.
llvm-svn: 86360
2009-11-07 08:45:53 +00:00
8e1d7222a7
Fix PR5421 by APInt'izing switch lowering.
...
llvm-svn: 86354
2009-11-07 07:50:34 +00:00
74ab6efbe8
merge cmp1 into cmp0 and filecheckize.
...
llvm-svn: 86345
2009-11-07 06:19:20 +00:00
a8e8a7c976
Refactor code. Fix a potential missing check. Teach isIdentical() about tLDRpci_pic.
...
llvm-svn: 86330
2009-11-07 04:04:34 +00:00
7ff831962a
- Add TargetInstrInfo::isIdentical(). It's similar to MachineInstr::isIdentical
...
except it doesn't care if the definitions' virtual registers differ. This is
used by machine LICM and other MI passes to perform CSE.
- Teach Thumb2InstrInfo::isIdentical() to check two t2LDRpci_pic are identical.
Since pc relative constantpool entries are always different, this requires it
it check if the values can actually the same.
llvm-svn: 86328
2009-11-07 03:52:02 +00:00
207b246650
- Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relative
...
load of a GV from constantpool and then add pc. It allows the code sequence to
be rematerializable so it would be hoisted by machine licm.
- Add a late pass to break these pseudo instructions into a number of real
instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm
to this pass. This is done before post regalloc scheduling to allow the
scheduler to proper schedule these instructions. It also allow them to be
if-converted and shrunk by later passes.
llvm-svn: 86304
2009-11-06 23:52:48 +00:00
9df3acf486
Honour subreg machine operands during asmprinting
...
llvm-svn: 86303
2009-11-06 23:45:15 +00:00
d95ccd6c4d
Print VMOV (immediate) operands as hexadecimal values. Apple's assembler
...
will not accept negative values for these. LLVM's default operand printing
sign extends values, so that valid unsigned values appear as negative
immediates. Print all VMOV immediate operands as hex values to resolve this.
Radar 7372576.
llvm-svn: 86301
2009-11-06 23:33:28 +00:00
db42ca663b
Fix a broken test.
...
llvm-svn: 86298
2009-11-06 23:06:42 +00:00
408aa56fb5
Remove ARMPCLabelIndex from ARMISelLowering. Use ARMFunctionInfo::createConstPoolEntryUId() instead.
...
llvm-svn: 86294
2009-11-06 22:24:13 +00:00
80f04dc67d
Fix PR5315, original patch by Nicolas Capens!
...
llvm-svn: 86203
2009-11-06 00:11:57 +00:00
98693a3ac2
Update these tests for the new label names.
...
llvm-svn: 86192
2009-11-05 23:31:40 +00:00
45119d8850
Add -mtriple to llc commands, attempting to fix buildbot failures.
...
llvm-svn: 86086
2009-11-05 00:51:31 +00:00
90d0b82e12
Attempt again to fix buildbot failures: make expected output less specific
...
and compile with -mtriple to specify *-apple-darwin targets.
llvm-svn: 86081
2009-11-05 00:30:35 +00:00
f84f7105f7
Add PowerPC codegen for indirect branches.
...
llvm-svn: 86050
2009-11-04 21:31:18 +00:00
e8ca96cf24
Fix broken test.
...
llvm-svn: 86045
2009-11-04 20:04:11 +00:00
16f60b9216
Add test for ARM indirectbr codegen.
...
llvm-svn: 86042
2009-11-04 19:25:34 +00:00
95bdc5d899
RangeIsDefinedByCopyFromReg() should check for subreg_to_reg, insert_subreg,
...
and extract_subreg as a "copy" that defines a valno.
Also fixes a typo. These two issues prevent a simple subreg coalescing from
happening before.
llvm-svn: 86022
2009-11-04 08:33:14 +00:00
8f4e3d99c9
Fix test.
...
llvm-svn: 85986
2009-11-04 00:42:33 +00:00
0410bced1c
fconsts / fconstd immediate should be proceeded with #.
...
llvm-svn: 85952
2009-11-03 21:59:33 +00:00
f42b5af549
Re-apply 85799. It turns out my code isn't buggy.
...
llvm-svn: 85947
2009-11-03 21:40:02 +00:00
90fedc6ef9
Make opt default to not adding a target data string and update tests that depend on target data to supply it within the test
...
llvm-svn: 85900
2009-11-03 15:29:06 +00:00
8d681f0471
Fix PR5367. QPR_8 is the super regclass of DPR_8 and SPR_8.
...
llvm-svn: 85871
2009-11-03 05:52:54 +00:00
a21bc75d78
Declare sin & cos as readonly so they match the code in SelectionDAGBuild
...
llvm-svn: 85853
2009-11-03 02:19:31 +00:00
2c2dc9f64f
Temporary xfail until PR5367 will be resolved
...
llvm-svn: 85848
2009-11-03 00:37:36 +00:00
fbe0256b23
Revert r85049, it is causing PR5367
...
llvm-svn: 85847
2009-11-03 00:24:48 +00:00
a8a58efc03
Revert 85799 for now. It might be breaking llvm-gcc driver.
...
llvm-svn: 85827
2009-11-02 21:49:14 +00:00
2729543984
Initilize the machine LICM CSE map upon the first time an instruction is hoisted to
...
the loop preheader. Add instructions which are already in the preheader block that
may be common expressions of those that are hoisted out. These does get a few more
instructions CSE'ed.
llvm-svn: 85799
2009-11-02 08:09:49 +00:00
fb2d385221
Remove an irrelevant and poorly reduced test case.
...
llvm-svn: 85794
2009-11-02 07:11:54 +00:00
1708b06c0e
Unbreak ARMBaseRegisterInfo::copyRegToReg.
...
llvm-svn: 85787
2009-11-02 04:44:55 +00:00
4d23754b14
Handle splats of undefs properly. This includes the testcase for PR5364 as well.
...
llvm-svn: 85767
2009-11-02 00:12:06 +00:00
8cce1eb6aa
64-bit FP loads & stores operate on both NEON and VFP pipelines.
...
llvm-svn: 85765
2009-11-02 00:11:06 +00:00
43219997b6
Make use of imm12 version of Thumb2 ldr / str instructions more aggressively.
...
llvm-svn: 85743
2009-11-01 21:12:51 +00:00
50bc004b67
Fix tests.
...
llvm-svn: 85723
2009-11-01 18:13:29 +00:00
50ba5c3dc2
improve x86 codegen support for blockaddress. We now compile
...
the testcase into:
_test1: ## @test1
## BB#0: ## %entry
leaq L_test1_bb6(%rip), %rax
jmpq *%rax
L_test1_bb: ## Address Taken
LBB1_1: ## %bb
movb $1, %al
ret
L_test1_bb6: ## Address Taken
LBB1_2: ## %bb6
movb $2, %al
ret
Note, it is very very strange that BlockAddressSDNode doesn't carry
around TargetFlags. Dan, please fix this.
llvm-svn: 85703
2009-11-01 03:25:03 +00:00
6f29ad9170
Use cbz and cbnz instructions.
...
llvm-svn: 85698
2009-10-31 23:46:45 +00:00
5cba8de2c8
vml[as].f32 cause stalls in following advanced SIMD instructions. Avoid using
...
them for scalar floating point operations for now.
llvm-svn: 85697
2009-10-31 22:57:36 +00:00
403202aef1
Consolidate test files
...
llvm-svn: 85696
2009-10-31 22:20:56 +00:00
c79fb530d4
Change to use FileCheck
...
llvm-svn: 85695
2009-10-31 22:16:14 +00:00
69f364babc
Make tests more explicit about which instructions are expected.
...
llvm-svn: 85694
2009-10-31 22:14:17 +00:00
259c37cc55
Grammar tweak to comments
...
llvm-svn: 85693
2009-10-31 22:12:44 +00:00
2c3e618a06
Update test to be more explicit about what instruction sequences are expected for each operation.
...
llvm-svn: 85691
2009-10-31 22:10:38 +00:00
Anton Korobeynikov