Commit Graph

238367 Commits

Author SHA1 Message Date
James Molloy bade86cedc [SimplifyCFG] Fix nasty RAUW bug from r277325
Using RAUW was wrong here; if we have a switch transform such as:
  18 -> 6 then
  6 -> 0

If we use RAUW, while performing the second transform the  *transformed* 6
from the first will be also replaced, so we end up with:
  18 -> 0
  6 -> 0

Found by clang stage2 bootstrap; testcase added.

llvm-svn: 277332
2016-08-01 09:34:48 +00:00
Diana Picus ab5a4c7dbb [AArch64] Return the correct size for TLSDESC_CALLSEQ
The branch relaxation pass is computing the wrong offsets because it assumes
TLSDESC_CALLSEQ eats up 4 bytes, when in fact it is lowered to an instruction
sequence taking up 16 bytes. This can become a problem in huge files with lots
of TLS accesses, as it may slowly move branch targets out of the range computed
by the branch relaxation pass.

Fixes PR24234 https://llvm.org/bugs/show_bug.cgi?id=24234

Differential Revision: https://reviews.llvm.org/D22870

llvm-svn: 277331
2016-08-01 08:38:49 +00:00
Craig Topper d2b2d745ff [AVX-512] Fix a test missed in r277327.
llvm-svn: 277330
2016-08-01 08:15:30 +00:00
James Molloy 91821bd0b4 [SimplifyCFG] Try and pacify buildbots after r277325
It looks like the two independent parts of the rotate operation (a lshr and shl) are being reordered on some bots. Add CHECK-DAGs to account for this.

llvm-svn: 277329
2016-08-01 08:09:55 +00:00
Sylvestre Ledru 522c0ec295 scan-build: Add an option to show the description in the list of defect
Summary:
This patch adds an option //--show-description// to add the defect description to the list of defect. This helps to get a better understanding of the defect without opening the page.

For example, this is used for Firefox:
https://people.mozilla.org/~sledru/reports/fx-scan-build/

Reviewers: rizsotto.mailinglist, zaks.anna

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D22810

llvm-svn: 277328
2016-08-01 08:04:45 +00:00
Craig Topper c48c029610 [AVX-512] Fix duplicate column in AVX512 execution dependency table that was preventing VMOVDQU32/VMOVDQA32 from being recognized. Fix a bug in the code that stops execution dependency fix from turning operations on 32-bit integer element types into operations on 64-bit integer element types.
llvm-svn: 277327
2016-08-01 07:55:33 +00:00
Craig Topper ddc96cd33d [X86] Regenerate a test to pick up shuffle comments that were added at some point.
llvm-svn: 277326
2016-08-01 07:55:24 +00:00
James Molloy b2e436de42 [SimplifyCFG] Range reduce switches
If a switch is sparse and all the cases (once sorted) are in arithmetic progression, we can extract the common factor out of the switch and create a dense switch. For example:

    switch (i) {
    case 5: ...
    case 9: ...
    case 13: ...
    case 17: ...
    }

can become:

    if ( (i - 5) % 4 ) goto default;
    switch ((i - 5) / 4) {
    case 0: ...
    case 1: ...
    case 2: ...
    case 3: ...
    }

or even better:

   switch ( ROTR(i - 5, 2) {
   case 0: ...
   case 1: ...
   case 2: ...
   case 3: ...
   }

The division and remainder operations could be costly so we only do this if the factor is a power of two, and emit a right-rotate instead of a divide/remainder sequence. Dense switches can be lowered significantly better than sparse switches and can even be transformed into lookup tables.

llvm-svn: 277325
2016-08-01 07:45:11 +00:00
Maxim Ostapenko 9f0546b5a9 [asan] Reduce flakiness of heavy recovery mode tests.
When we run halt_on_error-torture.cc with 10 threads and 20 iterations with halt_on_error=false:suppress_equal_pcs=false, we write 200 reports to 10.txt file and sometimes have collisions.
We have CHECK-COLLISION check that greps 'AddressSanitizer: nested bug in the same thread, aborting' message in 10.txt, but it doesn't contain this line.
If I don't redirect stderr > 10.txt 'AddressSanitizer: nested bug in the same thread, aborting' is printed to my screen as expected.
Same happens for halt_on_error_suppress_equal_pcs.cc and halt_on_error-torture.cc. This happens because of kernel bug: https://lkml.org/lkml/2014/2/17/324
Furtunately, we can fix these tests by implicitly setting O_APPEND for opened files (use >> instead of > for stderr redirection).

Differential Revision: https://reviews.llvm.org/D22921

llvm-svn: 277324
2016-08-01 07:24:36 +00:00
Hrvoje Varga 00d96ee7b9 [mips] Clang generates unaligned offset for MSA instruction st.d
Differential Revision: https://reviews.llvm.org/D19475

llvm-svn: 277323
2016-08-01 06:46:20 +00:00
Diana Picus 850043b25a [AArch64] Register passes so they can be run by llc
Initialize all AArch64-specific passes in the TargetMachine so they can be run
by llc. This can lead to conflicts in opt with some command line options that
share the same name as the pass, so I took this opportunity to do some cleanups:
* rename all relevant command line options from "aarch64-blah" to
  "aarch64-enable-blah" and update the tests accordingly
* run clang-format on their declarations
* move all these declarations to a common place (the TargetMachine) as opposed
  to having them scattered around (AArch64BranchRelaxation and
  AArch64AddressTypePromotion were the only offenders)

llvm-svn: 277322
2016-08-01 05:56:57 +00:00
Craig Topper 749a111f1e [AVX-512] Teach X86InstrInfo::getLargestLegalSuperClass to inflate to FR32X/FR64X if AVX512 is supported and VR128X/VR256X if VLX is supported.
Had to update a stack folding test to clobber the other 16 registers since this now made them get used instead of spilling.

llvm-svn: 277321
2016-08-01 05:31:50 +00:00
Craig Topper 9161e4ec22 [AVX512] Replace scalar fp arithmetic intrinsics with native IR in an AVX512 test. The intrinsics aren't lowered to AVX512 instructions.
The intrinsics really should be removed and autoupgraded.

llvm-svn: 277320
2016-08-01 04:29:16 +00:00
Craig Topper 3946176314 [AVX-512] Use FR32X/FR64X/VR128X/VR256X register classes in addRegisterClass if AVX512(for FR32X/FR64) or VLX(for VR128X/VR256) is supported. This is a minimal requirement to be able to allocate all 32 registers.
llvm-svn: 277319
2016-08-01 04:29:13 +00:00
Craig Topper da50eec26d [X86] Move mask register handling into the main switch of getLoadStoreRegOpcode. No functional change intended.
llvm-svn: 277318
2016-08-01 04:29:11 +00:00
Sean Silva 423c7149dc Revert r277313 and r277314.
They seem to trigger an LSan failure:
http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/15140/steps/check-llvm%20asan/logs/stdio

Revert "Add the tests for r277313"

This reverts commit r277314.

Revert "CodeExtractor : Add ability to preserve profile data."

This reverts commit r277313.

llvm-svn: 277317
2016-08-01 04:16:09 +00:00
Sean Silva e5a5c966cd Move this test to x86-specific directory.
No bots have yelled yet, but this test references an x86 intrinsic.
Also, it invokes llc on x86 IR.

Fixup to r277315.

llvm-svn: 277316
2016-08-01 03:22:05 +00:00
Sean Silva a0a802abe3 Fix - CodeExtractor : Inherit Target Dependent Attributes from the parent function.
When extracting a set of blocks make sure to inherit all of the target
dependent attributes to make sure that the function will be valid for
lowering. One example is the "target-features" attribute for x86, if the
extracted region has functionality that relies on a specific feature it
will fail to be lowered.
This also allows for extracted functions to be valid for inlining, at
least back into the parent function, as the target attributes are tested
when inlining for compatibility.

Patch by River Riddle!

Differential Revision: https://reviews.llvm.org/D22713

llvm-svn: 277315
2016-08-01 03:15:32 +00:00
Sean Silva 72be9a6937 Add the tests for r277313
Forgot to `git add` them.

llvm-svn: 277314
2016-08-01 03:04:34 +00:00
Sean Silva 6208924323 CodeExtractor : Add ability to preserve profile data.
Added ability to estimate the entry count of the extracted function and
the branch probabilities of the exit branches.

Patch by River Riddle!

Differential Revision: https://reviews.llvm.org/D22744

llvm-svn: 277313
2016-08-01 02:59:26 +00:00
Xinliang David Li 52626f132c Fix a bug in lit var def: remove extra space
llvm-svn: 277312
2016-08-01 01:54:40 +00:00
Simon Pilgrim 8ae4354df6 [X86][SSE] Regenerate frem tests
llvm-svn: 277311
2016-07-31 21:59:23 +00:00
Simon Pilgrim b089ba4c65 [X86][SSE] Regenerate fpext tests
llvm-svn: 277310
2016-07-31 21:55:33 +00:00
Daniel Berlin 5130cc831a Fix the MemorySSA updating API to enable people to create memory accesses before removing old ones
llvm-svn: 277309
2016-07-31 21:08:20 +00:00
Daniel Berlin cdda3ce478 Comment fixes to MemorySSA.h
llvm-svn: 277308
2016-07-31 21:08:10 +00:00
Dimitry Andric f8099f256d Add more gcc compatibility names to clang's cpuid.h
Summary:
Some cpuid bit defines are named slightly different from how gcc's
cpuid.h calls them.

Define a few more compatibility names to appease software built for gcc:

* `bit_PCLMUL`      alias of `bit_PCLMULQDQ`
* `bit_SSE4_1`      alias of `bit_SSE41`
* `bit_SSE4_2`      alias of `bit_SSE42`
* `bit_AES`         alias of `bit_AESNI`
* `bit_CMPXCHG8B`   alias of `bit_CX8`

While here, add the misssing 29th bit, `bit_F16C` (which is how gcc
calls this bit).

Reviewers: joerg, rsmith

Subscribers: bruno, cfe-commits

Differential Revision: https://reviews.llvm.org/D22010

llvm-svn: 277307
2016-07-31 20:23:23 +00:00
Craig Topper c0097dc7d0 [X86] Simplify code for determing GR or FR reg classes by querying for super classes instead of manually listing individual classes.
llvm-svn: 277306
2016-07-31 20:20:08 +00:00
Craig Topper 7afdc0fb25 [AVX512] Always use EVEX encodings for 128/256-bit move instructions in getLoadStoreRegOpcode if VLX is supported.
llvm-svn: 277305
2016-07-31 20:20:05 +00:00
Craig Topper 4c53e60360 [AVX512] Add VLX packed move instructions to the execution dependency fix pass and update tests.
llvm-svn: 277304
2016-07-31 20:20:01 +00:00
Craig Topper eb1cc981a5 [AVX512] Move FR32X/FR64X handling in getLoadStoreRegOpcode into the main switch. No functional change intended.
llvm-svn: 277303
2016-07-31 20:19:55 +00:00
Craig Topper 338ec9a0cb [AVX512] Stop treating VR512 specially in getLoadStoreRegOpcode and use the regular switch which already tried to handle it, but was unreachable. This has the added benefit of enabling aligned loads/stores if the stack is aligned.
llvm-svn: 277302
2016-07-31 20:19:53 +00:00
Craig Topper 2a6bbb8203 [AVX512] Add X86::VR512RegClassID to X86RegisterInfo::getLargestLegalSuperClass.
llvm-svn: 277301
2016-07-31 20:19:50 +00:00
Dimitry Andric 41d9b3640c Fix ASan alloca_constant_size.cc test on FreeBSD.
On FreeBSD <alloca.h> does not exist: alloca(3) is defined in <stdlib.h>
instead.

llvm-svn: 277300
2016-07-31 20:16:59 +00:00
Simon Pilgrim 6be48e4aa7 [X86] Improve 64-bit shifts on 32-bit targets (PR14593)
As discussed on PR14593, this patch adds support for lowering to SHLD/SHRD from the patterns generated by DAGTypeLegalizer::ExpandShiftWithKnownAmountBit.

Differential Revision: https://reviews.llvm.org/D23000

llvm-svn: 277299
2016-07-31 19:50:45 +00:00
David Majnemer 6004952661 [COFF] Expose iterators for ImportAddressTableRVA
Patch by Bandzi Michal!

llvm-svn: 277298
2016-07-31 19:40:02 +00:00
Dimitry Andric 75534e23d0 XFAIL one sanitizer symbolizer test for FreeBSD
Summary:
Due to a QoI issuse in FreeBSD's libcxxrt-based demangler, one sanitizer
symbolizer test consistently appears to fail:

    Value of: DemangleSwiftAndCXX("foo")
      Actual: "float"
    Expected: "foo"

This is because libcxxrt's __cxa_demangle() incorrectly demangles the "foo"
identifier to "float".  It should return an error instead.

For now, XFAIL this particular test for FreeBSD, until we can fix libcxxrt
properly (which might take some time to coordinate with upstream).

Reviewers: rnk, zaks.anna, emaste

Subscribers: emaste, llvm-commits, kubabrecka

Differential Revision: https://reviews.llvm.org/D23001

llvm-svn: 277297
2016-07-31 19:27:46 +00:00
David Majnemer 1c0aa04e7e [COFF] Remove a duplicate import_directory_table_entry definition
We had import_directory_table_entry and
coff_import_directory_table_entry, remove one.  Also, factor out the
logic which determins if a descriptor is a terminator.

llvm-svn: 277296
2016-07-31 19:25:21 +00:00
David Majnemer 26bdcaf4d2 [bugpoint] Add a -Os option
llvm-svn: 277295
2016-07-31 19:25:16 +00:00
Etienne Bergeron 0b2d71373b [compiler-rt] Add support for interception redirect exports.
Summary:
On windows, an export can be redirected to an other DLL.
This patch is adding the required support to the internal
GetProcAddress implementation.

This case was encountered by instrumenting chromium (win 64-bits)
using this GN configuration:
```
is_component_build = true
is_debug = false
enable_nacl = false
is_clang = true
is_asan = true
clang_base_path = "d:\src\llvm\ninja64"
clang_use_chrome_plugins = false
clang_version = "4.0.0"
```

The operating system is win7 (x64).
Visual Studio: 2015 Professional



Reviewers: rnk

Subscribers: llvm-commits, chrisha

Differential Revision: https://reviews.llvm.org/D22880

llvm-svn: 277294
2016-07-31 17:56:26 +00:00
Simon Pilgrim 64845bb8b4 [X86] Add tests for the lowering SHLD/SHRD from manual pattern similar to those generated by ExpandShiftWithKnownAmountBit
Test for add(v,v) as well as shl(v,1)

llvm-svn: 277293
2016-07-31 17:51:37 +00:00
Craig Topper 00d34ed64f [AVX-512] Don't let ExeDependencyFix pass convert VPANDD/Q to VPANDPS/PD unless DQI instructions are supported. Same for ANDN, OR, and XOR.
Thanks to Igor Breger for pointing out my mistake.

llvm-svn: 277292
2016-07-31 17:15:07 +00:00
Simon Pilgrim 1e096b3a7a [X86] Add tests for the lowering SHLD/SHRD from manual patterns
As discussed on D23000

llvm-svn: 277291
2016-07-31 17:11:49 +00:00
Amjad Aboud 580498de17 Fixed "copy-paste" mistake from revision 255245.
llvm-svn: 277290
2016-07-31 14:41:50 +00:00
Elena Demikhovsky 6e9b16054f AVX-512: Removed AssertZext node before TRUNCATE
Removed AssertZext node, which was inserted between X86ISD::SETCC and "truncate to i1".

Differential Revision: https://reviews.llvm.org/D22850

llvm-svn: 277289
2016-07-31 06:48:01 +00:00
Chandler Carruth 974c67e7c6 [ADT] Add 'consume_front' and 'consume_back' methods to StringRef which
are very handy when parsing text.

They are essentially a combination of startswith and a self-modifying
drop_front, or endswith and drop_back respectively.

Differential Revision: https://reviews.llvm.org/D22723

llvm-svn: 277288
2016-07-31 02:19:13 +00:00
Faisal Vali 5e5501861a [NFC] Rearrange an example-file so the c++14 specific example is on top.
This makes it easier to add C++1z examples to the bottom, just before the #endif.

llvm-svn: 277287
2016-07-31 01:19:17 +00:00
Hubert Tong e4a0c0ec78 Reapply r276069 with workaround for MSVC 2013
llvm-svn: 277286
2016-07-30 22:33:34 +00:00
Davide Italiano d08e18fc7d [HexagonConstPropagation] Remove dead code.
llvm-svn: 277285
2016-07-30 22:07:21 +00:00
Davide Italiano 892d9f06d0 [HexagonBitSimplify] Remove dead code.
llvm-svn: 277284
2016-07-30 22:07:18 +00:00
Davide Italiano 3ebda7ed88 [ARMConstantIslandPass] Remove dead code.
llvm-svn: 277283
2016-07-30 22:07:15 +00:00