415c3dc501
Add MSP430 mem-mem insts support. Patch by Brian Lucas with some my refinements
...
llvm-svn: 83811
2009-10-11 23:03:28 +00:00
2c2deae5ac
remove some harmful code that would turn an insertelement on an undef
...
into a shuffle even if it was used by another insertelement. If the
visitation order of instcombine was wrong, this would turn a chain of
insertelements into a chain of shufflevectors, which was quite painful.
Since CollectShuffleElements handles these cases, the code can just
be nuked.
llvm-svn: 83810
2009-10-11 23:02:46 +00:00
c6cdbfbfdd
teach instcombine to simplify xor's harder, catching the
...
new testcase.
llvm-svn: 83799
2009-10-11 22:22:13 +00:00
6e6ac47125
cleanups
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llvm-svn: 83797
2009-10-11 22:00:32 +00:00
1639234775
cleanup, no functionality change.
...
llvm-svn: 83795
2009-10-11 21:36:10 +00:00
fd27f8a5b3
generalize a transformation even more: we don't care whether the
...
input the the mul is a zext from bool, just that it is all zeros
other than the low bit. This fixes some phase ordering issues
that would cause us to miss some xforms in mul.ll when the worklist
is visited differently.
llvm-svn: 83794
2009-10-11 21:29:45 +00:00
406cb75c6b
simplify a transformation by making it more general.
...
llvm-svn: 83792
2009-10-11 21:22:21 +00:00
f39f4f928a
temporarily revert previous patch
...
llvm-svn: 83791
2009-10-11 21:05:34 +00:00
bb058d3a23
populate instcombine's initial worklist more carefully, causing
...
it to visit instructions from the start of the function to the
end of the function in the first path. This greatly speeds up
some pathological cases (e.g. PR5150).
llvm-svn: 83790
2009-10-11 21:04:37 +00:00
8b3081350e
Remove CleanupDbgInfo, instcombine does this and its not worth duplicating it
...
here.
llvm-svn: 83789
2009-10-11 19:58:35 +00:00
907ec36943
LICM shouldn't sink/delete debug information. Fix this and add a testcase.
...
For now the metadata of sinked/hoisted instructions is still wrong, but that'll
be fixed when instructions will have debug metadata directly attached.
llvm-svn: 83786
2009-10-11 19:15:54 +00:00
6bce6bbf40
Implement 'm' memory operand properly
...
llvm-svn: 83785
2009-10-11 19:14:21 +00:00
a58a3f930a
Implement proper asmprinting for the globals. This eliminates bogus "call" modifier and also adds support for offsets wrt globals.
...
llvm-svn: 83784
2009-10-11 19:14:02 +00:00
3525a4a268
Implement asm printing for inline asm memory operands
...
llvm-svn: 83783
2009-10-11 19:13:34 +00:00
85c85c5e04
when folding duplicate conditions, delete the
...
now-probably-dead instruction tree feeding it.
llvm-svn: 83778
2009-10-11 18:39:58 +00:00
e374382b8f
implement rdar://7293527, a trivial instcombine that llvm-gcc
...
gets but clang doesn't, because it is implemented in GCC's
fold routine.
llvm-svn: 83761
2009-10-11 07:53:15 +00:00
97b1405207
implement a transformation in jump threading that is currently
...
done by condprop, but do it in a much more general form. The
basic idea is that we can do a limited form of tail duplication
in the case when we have a branch on a phi. Moving the branch
up in to the predecessor block makes instruction selection
much easier and encourages chained jump threadings.
llvm-svn: 83759
2009-10-11 07:24:57 +00:00
6ce85e85f5
restructure some code, no functionality change.
...
llvm-svn: 83756
2009-10-11 04:40:21 +00:00
f466bc84c9
factor some code better and move a function, no functionality change.
...
llvm-svn: 83755
2009-10-11 04:33:43 +00:00
f99a74e24b
make jump threading on a phi with undef inputs happen.
...
llvm-svn: 83754
2009-10-11 04:18:15 +00:00
71d353dd48
rewrite LCSSA to use SSAUpdate, to only return true if it modifies
...
the IR, and to implement the FIXME'd optimization.
llvm-svn: 83748
2009-10-11 02:53:37 +00:00
101dde30ed
clean up and simplify some code. Don't use setvector when things will be
...
inserted only once, just use vector. Don't compute ExitBlocks unless we
need it, change std::sort to array_pod_sort.
llvm-svn: 83747
2009-10-11 01:07:15 +00:00
b6c65faa64
switch GVN to use SSAUpdater. Besides removing a lot of complexity
...
from GVN, this also speeds it up, inserts fewer PHI nodes (see the
testcase) and allows it to remove more loads (due to fewer PHI nodes
standing in the way).
llvm-svn: 83746
2009-10-10 23:50:30 +00:00
9c382cebc5
add a simple helper method.
...
llvm-svn: 83745
2009-10-10 23:41:48 +00:00
249265de06
add ability for clients of SSAUpdater to find out about the
...
PHI nodes inserted.
llvm-svn: 83744
2009-10-10 23:15:24 +00:00
89d2a5c4f3
remove dead code
...
llvm-svn: 83742
2009-10-10 23:04:12 +00:00
67cdd8b567
add the ability to get a rewritten value from the middle of a block,
...
not just at the end. Add a big comment explaining when this could
be useful (which never happens for jump threading).
llvm-svn: 83741
2009-10-10 23:00:11 +00:00
e474a8d3a7
rename GetValueInBlock -> GetValueAtEndOfBlock to better reflect
...
what it does.
llvm-svn: 83740
2009-10-10 22:41:58 +00:00
5b8826b4da
It seems that OR operation does not affect status reg at all.
...
Remove impdef of SRW. This fixes PR4779
llvm-svn: 83739
2009-10-10 22:17:47 +00:00
65e69a77e1
use a typedef instead of spelling out an insane type. Yay for auto someday.
...
llvm-svn: 83707
2009-10-10 09:09:20 +00:00
84095071ea
Change jump threading to use the new SSAUpdater class instead of
...
DemoteRegToStack. This makes it more efficient (because it isn't
creating a ton of load/stores that are eventually removed by a later
mem2reg), and more slightly more effective (because those load/stores
don't get in the way of threading).
llvm-svn: 83706
2009-10-10 09:05:58 +00:00
60d4e69c81
Implement an efficient and fully general SSA update mechanism that
...
works on unstructured CFGs. This implements PR217, our oldest open PR.
llvm-svn: 83705
2009-10-10 09:04:27 +00:00
f30a2b0c86
random tidying
...
llvm-svn: 83701
2009-10-10 06:22:45 +00:00
b8120770b4
Create a new InstrEmitter class for translating SelectionDAG nodes
...
into MachineInstrs. This is mostly just moving the code from
ScheduleDAGSDNodesEmit.cpp into a new class. This decouples MachineInstr
emitting from scheduling.
llvm-svn: 83699
2009-10-10 01:32:21 +00:00
a22f2d8614
Make getMachineNode return a MachineSDNode* instead of a generic SDNode*
...
since it won't do any folding. This will help avoid some inconvenient
casting.
llvm-svn: 83698
2009-10-10 01:29:16 +00:00
1faa11521e
Remove a no-longer-necessary #include.
...
llvm-svn: 83697
2009-10-10 00:36:09 +00:00
e919de5acf
Replace X86's CanRematLoadWithDispOperand by calling the target-independent
...
MachineInstr::isInvariantLoad instead, which has the benefit of being
more complete.
llvm-svn: 83696
2009-10-10 00:34:18 +00:00
26e9b89b7c
Fix a missing initialization of PostRAScheduler's AA member.
...
llvm-svn: 83695
2009-10-10 00:15:38 +00:00
918ec53c64
The ScheduleDAG framework now requires an AliasAnalysis argument, though
...
it isn't needed in the ScheduleDAGSDNodes schedulers.
llvm-svn: 83691
2009-10-09 23:33:48 +00:00
4a72f7ab53
Mark the LDR instruction with isReMaterializable, as it is rematerializable
...
when loading from an invariant memory location.
llvm-svn: 83688
2009-10-09 23:28:27 +00:00
87b02d5bbc
Factor out LiveIntervalAnalysis' code to determine whether an instruction
...
is trivially rematerializable and integrate it into
TargetInstrInfo::isTriviallyReMaterializable. This way, all places that
need to know whether an instruction is rematerializable will get the
same answer.
This enables the useful parts of the aggressive-remat option by
default -- using AliasAnalysis to determine whether a memory location
is invariant, and removes the questionable parts -- rematting operations
with virtual register inputs that may not be live everywhere.
llvm-svn: 83687
2009-10-09 23:27:56 +00:00
df45c7f642
Extract scope information from the variable itself, instead of relying on alloca or llvm.dbg.declare location.
...
While recording beginning of a function, use scope info from the first location entry instead of just relying on first location entry itself.
llvm-svn: 83684
2009-10-09 22:42:28 +00:00
307c053f2e
ExecutionEngine::clearGlobalMappingsFromModule failed to remove reverse
...
mappings, which could cause errors and assert-failures. This patch fixes that,
adds a test, and refactors the global-mapping-removal code into a single place.
llvm-svn: 83678
2009-10-09 22:10:27 +00:00
f4eb6777e5
Add a const qualifier.
...
llvm-svn: 83677
2009-10-09 22:09:05 +00:00
96a5b87ae2
Use names instead of numbers for some of the magic
...
constants used in inlining heuristics (especially
those used in more than one file). No functional change.
llvm-svn: 83675
2009-10-09 21:42:02 +00:00
a2b99107c4
Added another bit of the ARM target assembler to llvm-mc to parse register
...
lists. Changed ARMAsmParser::MatchRegisterName to return -1 instead of 0 on
errors so 0-15 values could be returned as register numbers. Also added the
rest of the arm register names to the currently hacked up version to allow more
testing. Some changes to ARMAsmParser::ParseOperand to give different errors
for things not yet supported and some additions to the hacked
ARMAsmParser::MatchInstruction to allow more testing for now.
llvm-svn: 83673
2009-10-09 21:12:28 +00:00
e19c1810d7
isTriviallyReMaterializable checks the
...
TargetInstrDesc::isRematerializable flag, so it isn't necessary to do
this check in its callers.
llvm-svn: 83671
2009-10-09 21:02:10 +00:00
7d9dffb413
Fix the x86 test-shrink optimization so that it doesn't shrink comparisons
...
when one of the bits being tested would end up being the sign bit in the
narrower type, and a signed comparison is being performed, since this would
change the result of the signed comparison. This fixes PR5132.
llvm-svn: 83670
2009-10-09 20:35:19 +00:00
dd76bb23d1
Add basic infrastructure and x86 support for preserving MachineMemOperand
...
information when unfolding memory references.
llvm-svn: 83656
2009-10-09 18:10:05 +00:00
fafa1fe2ad
Check invalid debug info for enums. This may happen when underlyng enum is optimized away. Eventually DwarfChecker will clean this up during llvm verification stage.
...
llvm-svn: 83655
2009-10-09 17:51:49 +00:00
26070c5cff
when previous scratch register is killed, flag the value as no longer tracking
...
llvm-svn: 83653
2009-10-09 17:33:33 +00:00
dc4893abfe
Revert r83606 and add comments explaining why it isn't safe.
...
llvm-svn: 83649
2009-10-09 16:35:06 +00:00
7ddb844a2d
Give Dan and my recent changes, machine LICM is now code size neutral.
...
llvm-svn: 83624
2009-10-09 06:31:25 +00:00
ccd4545ecb
Fix a logic error that caused non-rematable loop invariants loads to be licm'ed out of loop.
...
llvm-svn: 83622
2009-10-09 06:21:52 +00:00
be27d61cbc
Reset kill markers after live interval is reconstructed.
...
llvm-svn: 83608
2009-10-09 01:17:11 +00:00
d65387a49f
Preserve HasNSW and HasNUW when constructing SCEVs for Add and Mul
...
instructions.
llvm-svn: 83606
2009-10-09 00:41:22 +00:00
3059924bdd
When considering whether to inline Callee into Caller,
...
and that will make Caller too big to inline, see if it
might be better to inline Caller into its callers instead.
This situation is described in PR 2973, although I haven't
tried the specific case in SPASS.
llvm-svn: 83602
2009-10-09 00:11:32 +00:00
816fe0a4aa
Add the ability to track HasNSW and HasNUW on more kinds of SCEV expressions.
...
llvm-svn: 83601
2009-10-09 00:10:36 +00:00
84e7967fae
Add codegen support for NEON vst4lane intrinsics with 128-bit vectors.
...
llvm-svn: 83600
2009-10-09 00:01:36 +00:00
c409030838
Add codegen support for NEON vst3lane intrinsics with 128-bit vectors.
...
llvm-svn: 83598
2009-10-08 23:51:31 +00:00
b851eb356a
Add codegen support for NEON vst2lane intrinsics with 128-bit vectors.
...
llvm-svn: 83596
2009-10-08 23:38:24 +00:00
38ba47225a
Add codegen support for NEON vld4lane intrinsics with 128-bit vectors.
...
Also fix some copy-and-paste errors in previous changes.
llvm-svn: 83590
2009-10-08 22:53:57 +00:00
e23984fbbe
Remove code that makes no sense.
...
llvm-svn: 83589
2009-10-08 22:42:35 +00:00
cf54e934f8
Add codegen support for NEON vld3lane intrinsics with 128-bit vectors.
...
llvm-svn: 83585
2009-10-08 22:27:33 +00:00
da3c79698c
Update CMake build yet again after a source file was removed
...
llvm-svn: 83575
2009-10-08 21:24:34 +00:00
3dc625cdce
It's possible for a global variable to be optimized out of a metadata object. So
...
we should allow a "null" with this dyn_cast.
llvm-svn: 83573
2009-10-08 20:52:51 +00:00
222b86cd54
Use lower16 / upper16 imm modifiers to asmprint 32-bit imms splitted via movt/movw pair.
...
llvm-svn: 83572
2009-10-08 20:43:22 +00:00
e1969dcd11
Clear variable debug info map at the end of the function.
...
llvm-svn: 83571
2009-10-08 20:41:17 +00:00
c2728f44a9
Add codegen support for NEON vld2lane intrinsics with 128-bit vectors.
...
llvm-svn: 83568
2009-10-08 18:56:10 +00:00
fac9476589
Clean up some unnecessary initializations.
...
llvm-svn: 83566
2009-10-08 18:52:56 +00:00
4facd965bd
Clean up a comment (indentation was wrong).
...
llvm-svn: 83565
2009-10-08 18:51:31 +00:00
2a45a65511
Add a SelectionDAG getTargetInsertSubreg convenience function,
...
similar to getTargetExtractSubreg.
llvm-svn: 83564
2009-10-08 18:49:46 +00:00
20b2a77765
Do not record line number to implicitly mark start of function if function has arguments. Extra line number entries trip gdb in some cases.
...
llvm-svn: 83563
2009-10-08 18:48:03 +00:00
02fda54e8f
Add missing names for the XCore specific LADD and LSUB nodes.
...
llvm-svn: 83556
2009-10-08 17:14:57 +00:00
09984279fd
Add a form of addPreserved which takes a string argument, to allow passes
...
to declare that they preserve other passes without needing to pull in
additional header file or library dependencies. Convert MachineFunctionPass
and CodeGenLICM to make use of this.
llvm-svn: 83555
2009-10-08 17:00:02 +00:00
4e13316bf9
Add some peepholes for signed comparisons using ashr X, X, 32.
...
llvm-svn: 83549
2009-10-08 15:38:17 +00:00
78765deded
remove LoopVR pass. According to Nick:
...
"LoopVR's logic was copied into ScalarEvolution::getUnsignedRange and
::getSignedRange. Please delete LoopVR."
llvm-svn: 83531
2009-10-08 06:42:44 +00:00
b6b0ab6117
Add codegen support for NEON vst4 intrinsics with <1 x i64> vectors.
...
llvm-svn: 83526
2009-10-08 05:18:18 +00:00
534ea5ae32
Cleanup up unused R3LiveIn tracking.
...
llvm-svn: 83522
2009-10-08 01:50:26 +00:00
c0615aa17f
Re-enable register scavenging in Thumb1 by default.
...
llvm-svn: 83521
2009-10-08 01:46:59 +00:00
48a805bc6c
bugfix. The target may use virtual registers that aren't tracked for re-use but are allocated by the scavenger. The re-use algorithm needs to watch for that.
...
llvm-svn: 83519
2009-10-08 01:09:45 +00:00
71387b4b2f
Add codegen support for NEON vst3 intrinsics with <1 x i64> vectors.
...
llvm-svn: 83518
2009-10-08 00:28:28 +00:00
d4f5670096
Add codegen support for NEON vst2 intrinsics with <1 x i64> vectors.
...
llvm-svn: 83513
2009-10-08 00:21:01 +00:00
dafd08ea7e
In instcombine's debug output, avoid printing ADD for instructions that are
...
already on the worklist, and print Visited when an instruction is about to be
visited. Net, on one input, this reduced the output size by at least 9x.
llvm-svn: 83510
2009-10-08 00:12:24 +00:00
32cc4ec304
Add codegen support for NEON vld4 intrinsics with <1 x i64> vectors.
...
llvm-svn: 83508
2009-10-07 23:54:04 +00:00
5ef3c6d9f4
Add codegen support for NEON vld3 intrinsics with <1 x i64> vectors.
...
llvm-svn: 83506
2009-10-07 23:39:57 +00:00
763be1a248
Add codegen support for NEON vld2 intrinsics with <1 x i64> vectors.
...
llvm-svn: 83502
2009-10-07 22:57:01 +00:00
456735c54b
reverting thumb1 scavenging default due to test failure while I figure out what's up.
...
llvm-svn: 83501
2009-10-07 22:49:41 +00:00
63fe7ff7d9
second half of lazy liveness removal.
...
llvm-svn: 83500
2009-10-07 22:49:30 +00:00
e32fe29d29
Fix handling of x86 'R' constraint.
...
llvm-svn: 83499
2009-10-07 22:47:20 +00:00
267fa622fa
Enable thumb1 register scavenging by default.
...
llvm-svn: 83496
2009-10-07 22:26:31 +00:00
37cf79e5a6
Enable thumb1 register scavenging by default.
...
llvm-svn: 83494
2009-10-07 22:26:14 +00:00
55571bd7bd
Extract subprogram and compile unit information from the debug info attached to an instruction.
...
llvm-svn: 83491
2009-10-07 22:04:08 +00:00
50820a2677
Add some instruction encoding bits for NEON load/store instructions.
...
llvm-svn: 83490
2009-10-07 21:53:04 +00:00
5b741f3d14
80-column and whitespace fixes.
...
llvm-svn: 83489
2009-10-07 21:14:25 +00:00
818b6b96cb
Fixed MCSectionMachO::ParseSectionSpecifier to allow an attribute of "none" so
...
that a symbol stub section with no attributes can be parsed as in:
.section __TEXT,__picsymbolstub4,symbol_stubs,none,16
llvm-svn: 83488
2009-10-07 20:57:20 +00:00
e7ef4a9a6b
Add codegen support for NEON vst4 intrinsics with 128-bit vectors.
...
llvm-svn: 83486
2009-10-07 20:49:18 +00:00
23464866ad
Add codegen support for NEON vst3 intrinsics with 128-bit vectors.
...
llvm-svn: 83484
2009-10-07 20:30:08 +00:00
63849cbd32
grammar
...
llvm-svn: 83483
2009-10-07 19:08:36 +00:00
3dcb5377ef
Add codegen support for NEON vst2 intrinsics with 128-bit vectors.
...
llvm-svn: 83482
2009-10-07 18:47:39 +00:00
Anton Korobeynikov