a6b3ce203a
Allow targets to specify their choice of calling conventions per
...
libcall. Take advantage of this in the ARM backend to rectify broken
choice of CC when hard float is in effect. PIC16 may want to see if
it could be of use in MakePIC16Libcall, which works unchanged.
Patch by Sandeep!
llvm-svn: 79033
2009-08-14 20:10:52 +00:00
dc49a8d3f1
Add Thumb2 lsr hooks.
...
llvm-svn: 79032
2009-08-14 20:09:37 +00:00
09c070f4ce
80 col violation.
...
llvm-svn: 79026
2009-08-14 19:11:20 +00:00
9a58aff837
Indentation.
...
llvm-svn: 79022
2009-08-14 19:01:37 +00:00
e41903b10d
Also shrink immediate branches; also more assembler workarounds.
...
llvm-svn: 79014
2009-08-14 18:31:44 +00:00
6f34e278c7
Now that all the legal Neon shuffles (or at least the ones that have been
...
implemented so far) are recognized during legalization, it is easy to fall
back to the default expansion for other shuffles.
llvm-svn: 78995
2009-08-14 05:16:33 +00:00
eb54d51759
Create a new ARM-specific DAG node, VDUP, to represent a splat from a
...
scalar_to_vector. Generate these VDUP nodes during legalization instead
of trying to recognize the pattern during selection.
llvm-svn: 78994
2009-08-14 05:13:08 +00:00
cce31f6831
During legalization, change Neon vdup_lane operations from shuffles to
...
target-specific VDUPLANE nodes. This allows the subreg handling for the
quad-register version to be done easily with Pats in the .td file, instead
of with custom code in ARMISelDAGToDAG.cpp.
llvm-svn: 78993
2009-08-14 05:08:32 +00:00
db73d68cbe
Shrink ADR and LDR from constantpool late during constantpool island pass.
...
llvm-svn: 78970
2009-08-14 00:32:16 +00:00
76fa6e6a8f
New entry.
...
llvm-svn: 78968
2009-08-14 00:16:47 +00:00
55f1c09e31
Push LLVMContexts through the IntegerType APIs.
...
llvm-svn: 78948
2009-08-13 21:58:54 +00:00
86c065dd68
Revert 78892 and 78895, these break generating working executables on
...
x86_64-apple-darwin10.
--- Reverse-merging r78895 into '.':
U test/CodeGen/PowerPC/2008-12-12-EH.ll
U lib/Target/DarwinTargetAsmInfo.cpp
--- Reverse-merging r78892 into '.':
U include/llvm/Target/DarwinTargetAsmInfo.h
U lib/Target/X86/X86TargetAsmInfo.cpp
U lib/Target/X86/X86TargetAsmInfo.h
U lib/Target/ARM/ARMTargetAsmInfo.h
U lib/Target/ARM/ARMTargetMachine.cpp
U lib/Target/ARM/ARMTargetAsmInfo.cpp
U lib/Target/PowerPC/PPCTargetAsmInfo.cpp
U lib/Target/PowerPC/PPCTargetAsmInfo.h
U lib/Target/PowerPC/PPCTargetMachine.cpp
G lib/Target/DarwinTargetAsmInfo.cpp
llvm-svn: 78919
2009-08-13 17:03:38 +00:00
eba70d85cf
Add missing defs of R2 and D1.
...
llvm-svn: 78918
2009-08-13 16:59:44 +00:00
a9c2aad939
Finalize itineraries for cortex-a8 integer multiply
...
llvm-svn: 78908
2009-08-13 15:51:13 +00:00
695e1c6087
Remove unnecessary newline
...
llvm-svn: 78905
2009-08-13 15:12:16 +00:00
c96e88f8a5
Correct comment wording
...
llvm-svn: 78904
2009-08-13 15:11:43 +00:00
f59e9f4288
tPOP_RET now has predicate operands.
...
llvm-svn: 78898
2009-08-13 06:05:07 +00:00
3e4c012d54
Add a fixme message about canonicalizing floating-point vector types.
...
llvm-svn: 78897
2009-08-13 06:01:30 +00:00
ef6e602bf4
Revert r78852 for now. I want to do this differently, but I don't have time
...
to fix it tonight.
llvm-svn: 78896
2009-08-13 05:58:56 +00:00
e5801bd220
It's ok to spill a tGPR register as long as it's still allocated a low register.
...
llvm-svn: 78893
2009-08-13 05:40:51 +00:00
eb68198145
fix a minor fixme. When building with SL and later tools, the ".eh" symbols
...
don't need to be exported from the .o files.
llvm-svn: 78892
2009-08-13 05:30:22 +00:00
607cd3b63a
Change MCSectionELF to represent a section semantically instead of
...
syntactically as a string, very similiar to what Chris did with MachO.
The parsing support and validation is not introduced yet.
llvm-svn: 78890
2009-08-13 05:07:35 +00:00
c6800b55e6
Add a comment to describe why vector shuffles are legalized to custom DAG nodes.
...
llvm-svn: 78884
2009-08-13 02:13:04 +00:00
fcd6361ad1
Use cast<> instead of dyn_cast<> in places where the type is known.
...
llvm-svn: 78881
2009-08-13 01:57:47 +00:00
ef3d457126
Various AsmWriter output cleanups. Use WriteAsOperand instead of
...
PrintUnmangledNameSafely.
llvm-svn: 78878
2009-08-13 01:36:44 +00:00
ff2db10211
Recognize Neon VDUP shuffles during legalization instead of selection.
...
llvm-svn: 78852
2009-08-12 22:54:19 +00:00
ea3a402ae7
Recognize Neon VREV shuffles during legalization instead of selection.
...
llvm-svn: 78850
2009-08-12 22:31:50 +00:00
1432ef864e
This void is implicit in C++.
...
llvm-svn: 78848
2009-08-12 22:10:57 +00:00
4b35448360
Generate Neon VTBL and VTBX instructions from the corresponding intrinsics.
...
llvm-svn: 78835
2009-08-12 20:51:55 +00:00
aee7e49c50
PredCC is meant to be 2 bits wide, like PredCC1.
...
llvm-svn: 78829
2009-08-12 18:35:50 +00:00
b369ee4c48
Enhance the InstrStage object to enable the specification of an Itinerary with overlapping stages. The default is to maintain the current behavior that the "next" stage immediately follows the previous one.
...
llvm-svn: 78827
2009-08-12 18:31:53 +00:00
3cfc6463c9
Add catch block handling to SjLj exception handling.
...
llvm-svn: 78817
2009-08-12 17:38:44 +00:00
25cae66713
Fix TableGen warnings. This partly reverts my previous change to this file,
...
leaving the mayLoad and mayStore settings around only the load/store
instructions where those can't be inferred from the patterns.
llvm-svn: 78815
2009-08-12 17:04:56 +00:00
a5fdfac6ca
register naming cleanup (s/ip/r12/)
...
llvm-svn: 78806
2009-08-12 15:21:13 +00:00
9a6cf91261
Change TargetAsmInfo to be constructed via TargetRegistry from a Target+Triple
...
pair instead of from a virtual method on TargetMachine. This cuts the final
ties of TargetAsmInfo to TargetMachine, meaning that MC can now use
TargetAsmInfo.
llvm-svn: 78802
2009-08-12 07:22:17 +00:00
bb2af3555c
Shrink Thumb2 movcc instructions.
...
llvm-svn: 78790
2009-08-12 05:17:19 +00:00
81348021b1
Remove another Darwin assembler workaround.
...
llvm-svn: 78779
2009-08-12 02:07:19 +00:00
fd10869d4b
80 col violation.
...
llvm-svn: 78778
2009-08-12 02:03:03 +00:00
608d92c943
Remove an Darwin assembler workaround.
...
llvm-svn: 78777
2009-08-12 01:56:42 +00:00
1e6c2a1c17
Shrink ADDS, ADC, RSB, and SUBS.
...
llvm-svn: 78776
2009-08-12 01:49:45 +00:00
f042eadd1e
Add missing chain operands for VLD* and VST* instructions.
...
Set "mayLoad" and "mayStore" on the load/store instructions.
llvm-svn: 78761
2009-08-12 00:49:01 +00:00
f6a9d06241
Shrinkify Thumb2 r = add sp, imm.
...
llvm-svn: 78745
2009-08-11 23:00:31 +00:00
abdcbc7ef2
Change the asmprinter to print the comment character before the
...
"inlineasmstart/end" strings so that the contents of the directive
are separate from the comment character. This lets elf targets
get #APP/#NOAPP for free even if they don't use "#" as the comment
character. This also allows hoisting the darwin stuff up to the
shared TAI class.
llvm-svn: 78737
2009-08-11 22:39:40 +00:00
fd5defed1d
Allow a zero cycle stage to reserve/require a FU without advancing the cycle counter.
...
llvm-svn: 78736
2009-08-11 22:38:43 +00:00
54075a78b4
factorize more darwin TAI stuff. Note that this gives
...
darwin/arm support for .no_dead_strip
llvm-svn: 78734
2009-08-11 22:31:42 +00:00
6747b39ca5
factorize darwin ProtectedDirective and SetDirective.
...
llvm-svn: 78732
2009-08-11 22:22:44 +00:00
d832c8e87c
all darwin targets have .space and .zerofill, pull up.
...
llvm-svn: 78730
2009-08-11 22:17:31 +00:00
f710f71839
eliminate template from arm TAI
...
llvm-svn: 78729
2009-08-11 22:14:59 +00:00
7faf1fd9a0
move LCOMMDirective = "\t.lcomm\t" up to DarwinTAI, eliminate
...
template in PPC backend for TAI.
llvm-svn: 78727
2009-08-11 22:06:07 +00:00
cc9ca3500d
Shrinkify Thumb2 load / store multiple instructions.
...
llvm-svn: 78717
2009-08-11 21:11:32 +00:00
9f94459d24
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while
...
the latter is capable of representing either a primitive or an extended type.
llvm-svn: 78713
2009-08-11 20:47:22 +00:00
2c30970b22
pass the TargetTriple down from each target ctor to the
...
LLVMTargetMachine ctor. It is currently unused.
llvm-svn: 78711
2009-08-11 20:42:37 +00:00
fe27130454
split "JumpTableDirective" (an existing hack) into a PIC and nonPIC
...
version. This allows TAI implementations to specify the directive to use
based on the mode being codegen'd for.
The real fix for this is to remove JumpTableDirective, but I don't feel
like diving into the jumptable snarl just now.
llvm-svn: 78709
2009-08-11 20:30:58 +00:00
841850ed26
Add Thumb2 eh_sjlj_setjmp implementation
...
llvm-svn: 78701
2009-08-11 19:42:21 +00:00
1d5350c08f
fix GetInstSizeInBytes for eh_sjlj_setjmp
...
llvm-svn: 78683
2009-08-11 17:08:15 +00:00
eda08015ee
This void is implicit in C++.
...
llvm-svn: 78678
2009-08-11 16:03:08 +00:00
f24f9d9cb6
Whitespace cleanup. Remove trailing whitespace.
...
llvm-svn: 78666
2009-08-11 15:33:49 +00:00
74eb9e7bfd
Move ~ARMConstantPoolValue() to the .cpp file to avoid needing to include <cstdlib> in the header.
...
llvm-svn: 78665
2009-08-11 15:26:27 +00:00
806845daec
Fix the previous accidental commit. Now shrinking common Thumb2 load / store instructions.
...
llvm-svn: 78659
2009-08-11 09:37:40 +00:00
3606467709
Fix Thumb2 load / store addressing mode matching code. Do not use so_reg form to
...
match base only address, i.e. [r] since Thumb2 requires a offset register field.
For those, use [r + imm12] where the immediate is zero.
Note the generated assembly code does not look any different after the patch.
But the bug would have broken the JIT (if there is Thumb2 support) and it can
break later passes which expect the address mode to be well-formed.
llvm-svn: 78658
2009-08-11 08:52:18 +00:00
d4d352c663
80 column violation.
...
llvm-svn: 78657
2009-08-11 08:47:46 +00:00
192d7c0752
Cosmetic changes.
...
llvm-svn: 78655
2009-08-11 07:36:14 +00:00
6e62e93a8d
Adding a blank line back.
...
llvm-svn: 78654
2009-08-11 07:32:58 +00:00
12842f9865
Use vAny type to get rid of Neon intrinsics that differed only in whether
...
the overloaded vector types allowed floating-point or integer vector elements.
Most of these operations actually depend on the element type, so bitcasting
was not an option.
If you include the vpadd intrinsics that I updated earlier, this gets rid
of 20 intrinsics.
llvm-svn: 78646
2009-08-11 05:39:44 +00:00
741a9c7bf6
Use new EVT::vAny type to combine Neon intrinsics for VPADD.
...
llvm-svn: 78632
2009-08-11 01:15:26 +00:00
b80734bb15
Fix bug in NEON convert for single-precision FP. This also fixes the tblgen warnings.
...
llvm-svn: 78629
2009-08-11 01:07:38 +00:00
9382d5ac05
Add stdlib.h
...
llvm-svn: 78627
2009-08-11 00:20:00 +00:00
693e36a3e8
SjLj based exception handling unwinding support. This patch is nasty, brutish
...
and short. Well, it's kinda short. Definitely nasty and brutish.
The front-end generates the register/unregister calls into the SjLj runtime,
call-site indices and landing pad dispatch. The back end fills in the LSDA
with the call-site information provided by the front end. Catch blocks are
not yet implemented.
Built on Darwin and verified no llvm-core "make check" regressions.
llvm-svn: 78625
2009-08-11 00:09:57 +00:00
475f8a4fa2
Enable Thumb2 instruction shrinking (32-bit to 16-bit) pass. Convert a bunch of thumb2 tests to FileCheck.
...
llvm-svn: 78622
2009-08-10 23:56:04 +00:00
733a64db57
Fix a bug where DAGCombine was producing an illegal ConstantFP
...
node after legalize, and remove the workaround code from the
ARM backend.
llvm-svn: 78615
2009-08-10 23:15:10 +00:00
53aa7a960c
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.
...
llvm-svn: 78610
2009-08-10 22:56:29 +00:00
85b5b027f7
Use NEON for single-precision int<->FP conversions.
...
llvm-svn: 78604
2009-08-10 22:17:39 +00:00
3e77df2bcd
SimpleValueType-ify a few more methods on TargetLowering.
...
llvm-svn: 78595
2009-08-10 20:46:15 +00:00
f72c13bdf5
Handle the constantfp created during post-legalization dag combiner phase.
...
llvm-svn: 78594
2009-08-10 20:25:59 +00:00
246617857f
Continue the SimpleValueType-ification.
...
llvm-svn: 78593
2009-08-10 20:18:46 +00:00
6c20391d38
split MachO section handling stuff out to its out .h/.cpp file.
...
llvm-svn: 78576
2009-08-10 18:15:01 +00:00
fbcafd4c6c
arm only needs to emit one .align directive for hidden nlp's, not one
...
per pointer.
llvm-svn: 78574
2009-08-10 18:02:16 +00:00
292472d3d3
make sure that arm nonlazypointers are aligned properly
...
llvm-svn: 78573
2009-08-10 18:01:34 +00:00
62e053b790
Checkpoint scheduling itinerary changes.
...
llvm-svn: 78564
2009-08-10 15:56:13 +00:00
5bb93ce769
Watch out for empty BB.
...
llvm-svn: 78562
2009-08-10 08:10:13 +00:00
8a640ae504
rev, rev16, and revsh do not set CPSR.
...
llvm-svn: 78561
2009-08-10 07:58:45 +00:00
f16a1d5b79
Duh. Most 16-bit Thumb rr instructions are two-address. Fix table.
...
llvm-svn: 78560
2009-08-10 07:20:37 +00:00
1f5bee14a1
CPSR can be livein; transfer predicate operands correctly; tMUL is two-address.
...
llvm-svn: 78559
2009-08-10 06:57:42 +00:00
092b701a2c
Add support for folding loads / stores into 16-bit moves used by Thumb2.
...
llvm-svn: 78558
2009-08-10 06:32:05 +00:00
55c014a9f3
80 col violation.
...
llvm-svn: 78557
2009-08-10 05:51:48 +00:00
f5b73869f2
Use tMOVgpr2gpr instead of t2MOVr.
...
llvm-svn: 78556
2009-08-10 05:49:43 +00:00
51cbd2d6c4
Add support to reduce most of 32-bit Thumb2 arithmetic instructions.
...
llvm-svn: 78550
2009-08-10 02:37:24 +00:00
5b4c308f0c
Always use the 16-bit tMOVgpr2gpr instead of the 32-bit t2MOVr.
...
llvm-svn: 78549
2009-08-10 02:06:53 +00:00
cb307a27bf
Make the big switch: Change MCSectionMachO to represent a section *semantically*
...
instead of syntactically as a string. This means that it keeps track of the
segment, section, flags, etc directly and asmprints them in the right format.
This also includes parsing and validation support for llvm-mc and
"attribute(section)", so we should now start getting errors about invalid
section attributes from the compiler instead of the assembler on darwin.
Still todo:
1) Uniquing of darwin mcsections
2) Move all the Darwin stuff out to MCSectionMachO.[cpp|h]
3) there are a few FIXMEs, for example what is the syntax to get the
S_GB_ZEROFILL segment type?
llvm-svn: 78547
2009-08-10 01:39:42 +00:00
d461c1c559
Add support to convert 32-bit instructions to 16-bit non-two-address ones.
...
llvm-svn: 78540
2009-08-09 19:17:19 +00:00
cfed3005e5
Use subclassing to print lane-like immediates (w/o hash) eliminating
...
'no_hash' modifier. Hopefully this will make Daniel happy :)
llvm-svn: 78514
2009-08-08 23:10:41 +00:00
1cb9396f4f
1. Make MCSection an abstract class.
...
2. Move section switch printing to MCSection virtual method which takes a
TAI. This eliminates textual formatting stuff from TLOF.
3. Eliminate SwitchToSectionDirective, getSectionFlagsAsString, and
TLOFELF::AtIsCommentChar.
llvm-svn: 78510
2009-08-08 22:41:53 +00:00
ce7d14032b
now that getOrCreateSection is all object-file specific,
...
give the impls an object-file-specific name. In the future
they can take different arguments etc.
llvm-svn: 78495
2009-08-08 20:22:20 +00:00
028f6dc4c2
Update CMake
...
llvm-svn: 78475
2009-08-08 17:03:13 +00:00
7167f33872
Add insert_elt / extract_elt patterns for v4f32 stuff.
...
Did anyone tests v4f32 ever?
llvm-svn: 78470
2009-08-08 14:06:07 +00:00
4218516f5d
Lane number should be printed w/o hash
...
llvm-svn: 78469
2009-08-08 14:05:53 +00:00
887d05ce9b
Use VLDM / VSTM to spill/reload 128-bit Neon registers
...
llvm-svn: 78468
2009-08-08 13:35:48 +00:00
e2231070ff
Implement Neon VZIP and VUZP instructions. These are very similar to VTRN,
...
so I generalized the class for VTRN in the .td file to handle all 3 of them.
llvm-svn: 78460
2009-08-08 06:13:25 +00:00
db46af0461
Implement Neon VTRN instructions. For now, anyway, these are selected
...
directly from the intrinsics produced by the frontend. If it is more
convenient to have a custom DAG node for using these to implement shuffles,
we can add that later.
llvm-svn: 78459
2009-08-08 05:53:00 +00:00
1be453b462
Add a skeleton Thumb2 instruction size reduction pass.
...
llvm-svn: 78456
2009-08-08 03:21:23 +00:00
2aa91cc2be
Code refactoring. No functionality change.
...
llvm-svn: 78455
2009-08-08 03:20:32 +00:00
274fcbe43e
tADDhirr should target GPR, not tGPR.
...
llvm-svn: 78454
2009-08-08 03:19:44 +00:00
4dc201eb64
I can type.
...
llvm-svn: 78453
2009-08-08 02:54:37 +00:00
b94284b5e2
make printInstruction return void since its result is omitted. Make the
...
error condition get trapped with an assert.
llvm-svn: 78449
2009-08-08 01:32:19 +00:00
742db6a6d4
Make NEON single-precision FP support the default for cortex-a8 (again).
...
llvm-svn: 78430
2009-08-07 23:32:33 +00:00
d28a26dfab
Unbreak the stuff
...
llvm-svn: 78425
2009-08-07 22:51:13 +00:00
23b28cb824
2 more vdup.32 cases
...
llvm-svn: 78419
2009-08-07 22:36:50 +00:00
fb93be2b6f
A big oops. Thumb1 default CC is a def of CPSR, not a use of CPSR.
...
llvm-svn: 78418
2009-08-07 22:36:37 +00:00
6e130db3b7
Thumb2 32-bit ldm / stm needs .w suffix if submode is ia.
...
llvm-svn: 78410
2009-08-07 21:19:10 +00:00
b64ec07ea6
This is done.
...
llvm-svn: 78399
2009-08-07 19:34:52 +00:00
f0237b1aa6
Use 16-bit tMOVgpr2gpr instead of tMOVr to copy GPR registers in Thumb2 mode.
...
llvm-svn: 78398
2009-08-07 19:34:35 +00:00
4c3b1ca5a0
Fix support to use NEON for single precision fp math.
...
llvm-svn: 78397
2009-08-07 19:30:41 +00:00
82ff022ed2
Error out, rather than infinite looping, if constant island pass can't converge.
...
llvm-svn: 78377
2009-08-07 07:35:21 +00:00
317bd7aab2
tBfar is bl, which clobbers LR.
...
llvm-svn: 78370
2009-08-07 05:45:07 +00:00
a6d0afcb74
Fix a bunch of namespace pollution.
...
llvm-svn: 78363
2009-08-07 01:32:21 +00:00
b972e5633f
It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing.
...
This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time.
This fixes PR4659 and PR4682.
llvm-svn: 78361
2009-08-07 00:34:42 +00:00
0127031c20
Implement Neon VST[234] operations.
...
llvm-svn: 78330
2009-08-06 18:47:44 +00:00
b062c236c5
Add parameter to pattern classes to enable an itinerary to be specified for instructions. For now just use the existing itineraries or NoItinerary.
...
llvm-svn: 78321
2009-08-06 16:52:47 +00:00
488db94e7b
Neon does not actually have VLD{234}.64 instructions.
...
These operations will have to be synthesized from other instructions.
llvm-svn: 78263
2009-08-06 00:24:27 +00:00
e148ceaf65
Add a new pre-allocation pass to assign adjacent registers for Neon instructions
...
that have that constraint. This is currently just assigning a fixed set of
registers, and it only handles VLDn for n=2,3,4 with DPR registers.
I'm going to expand it to handle more operations next; we can make it smarter
once everything is working correctly.
llvm-svn: 78256
2009-08-05 23:12:45 +00:00
e5b5d8fbb3
When using NEON for single-precision FP, the NEON result must be placed in D0-D15 as these are the only D registers with S subregs. Introduce a new regclass to represent D0-D15 and use it in the NEON single-precision FP patterns.
...
llvm-svn: 78244
2009-08-05 21:02:22 +00:00
ef98dbe3de
Remove redundand checks: the only way to have, e.g. f32 RegVT is exactly
...
hardfloat case.
llvm-svn: 78237
2009-08-05 20:15:19 +00:00
ef42862ef5
Unbreak the stuff, this is ugly, but we cannot do better for now with 'plain' C calling conv.
...
llvm-svn: 78232
2009-08-05 19:40:16 +00:00
22ef75155e
Missed pieces for ARM HardFP ABI.
...
Patch by Sandeep Patel!
llvm-svn: 78225
2009-08-05 19:04:42 +00:00
4cc1feff4f
Remove some dead code.
...
llvm-svn: 78219
2009-08-05 18:12:37 +00:00
9ede773c4e
Remove a redundant declaration.
...
llvm-svn: 78216
2009-08-05 17:39:44 +00:00
21788bef7c
Disable NEON single-precision FP support for Cortex-A8, for now...
...
llvm-svn: 78209
2009-08-05 16:40:57 +00:00
44c4417812
Remove dead code. MDNode and MDString are not Constant anymore.
...
llvm-svn: 78207
2009-08-05 16:40:02 +00:00
a307edbdd5
By default, for cortex-a8 use NEON for single-precision FP.
...
llvm-svn: 78200
2009-08-05 16:01:19 +00:00
e219be7346
80 col violations.
...
llvm-svn: 78175
2009-08-05 06:41:25 +00:00
85f60cc5a8
Oops. I didn't mean to commit this piece yet.
...
llvm-svn: 78146
2009-08-05 02:47:13 +00:00
f9bbcd1afd
Major calling convention code refactoring.
...
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 01:29:28 +00:00
c6b5e8a5c5
Don't flush the raw_ostream between each MachineFunction. These flush
...
calls were originally put in place because errs() at one time was
not unbuffered, and these print routines are commonly used with errs()
for debugging. However, errs() is now properly unbuffered, so the
flush calls are no longer needed. This significantly reduces the
number of write(2) calls for regular asm printing when there are many
small functions.
llvm-svn: 78137
2009-08-05 00:49:25 +00:00
20f79e321e
Change DAG nodes for Neon VLD2/3/4 operations to return multiple results.
...
Get rid of yesterday's code to fix the register usage during isel.
Select the new DAG nodes to machine instructions. The new pre-alloc pass
to choose adjacent registers for these results is not done, so the
results of this will generally not assemble yet.
llvm-svn: 78136
2009-08-05 00:49:09 +00:00
7cc6aca1e6
Fix part 1 of pr4682. PICADD is a 16-bit instruction even in thumb2 mode.
...
llvm-svn: 78126
2009-08-04 23:47:55 +00:00
a8720101b5
Replace dregsingle operand modifier with explicit escaped curly brackets.
...
For other VLDn and VSTn operations, we need to list the multiple registers
explicitly anyway, so there's no point in special-casing this one usage.
llvm-svn: 78109
2009-08-04 21:39:33 +00:00
783b65b546
Enable load / store multiple pass for Thumb2. It's not using ldrd / strd yet.
...
llvm-svn: 78104
2009-08-04 21:12:13 +00:00
30bf625ac2
Add NEON single-precision FP support for fabs and fneg.
...
llvm-svn: 78101
2009-08-04 20:39:05 +00:00
a3abe2a7ce
In thumb mode, r7 is used as frame register. This fixes pr4681.
...
llvm-svn: 78086
2009-08-04 18:46:17 +00:00
a3839bc6c0
Match common pattern for FNMAC. Add NEON SP support.
...
llvm-svn: 78085
2009-08-04 18:44:29 +00:00
3b9c52c5c1
Initial support for single-precision FP using NEON. Added "neonfp" attribute to enable. Added patterns for some binary FP operations.
...
llvm-svn: 78081
2009-08-04 17:53:06 +00:00
d0a53d380a
Ooops, I was too fast to commit the wrong fix :(
...
llvm-svn: 78060
2009-08-04 11:18:31 +00:00
3c5b68e2a7
Fix a typo - this unbreaks llvm-gcc build on arm
...
llvm-svn: 78059
2009-08-04 11:12:51 +00:00
3870fbb561
Thumb2 does not have ib (increment before) and da (decrement after) forms of ldm / stm.
...
llvm-svn: 78057
2009-08-04 08:34:18 +00:00
f43cf709cb
Remove ARM specific getInlineAsmLength. We'll rely on the simpler (and faster) generic algorithm for now. If more accurate computation is needed, we'll rely on the disassembler.
...
llvm-svn: 78032
2009-08-04 01:56:09 +00:00
71756e789b
Load / store multiple pass fixes for Thumb2. Not enabled yet.
...
llvm-svn: 78031
2009-08-04 01:43:45 +00:00
03eb0e3c33
Emit sub r, #c instead of transforming it to add r, #-c if c fits in 8-bit. This is a bit of pre-mature optimization. 8-bit variant makes it likely it will be narrowed to a 16-bit instruction.
...
llvm-svn: 78030
2009-08-04 01:41:15 +00:00
f45dee3ad2
Lower Neon VLD* intrinsics to custom DAG nodes, and manually allocate the
...
results to fixed registers.
llvm-svn: 78025
2009-08-04 00:36:16 +00:00
17f8878114
Minor cleanup. No functional changes intended.
...
llvm-svn: 78024
2009-08-04 00:25:01 +00:00
09441faba9
use TLOF to compute the section for a function instead of
...
replicating the logic manually.
llvm-svn: 78011
2009-08-03 22:32:50 +00:00
73ebe435ca
convert macho stub emission to use SwitchToSection instead of
...
textual sections.
llvm-svn: 78007
2009-08-03 22:18:15 +00:00
f307e0bd6d
Lower CONCAT_VECTOR during legalization instead of matching it during isel.
...
Add a testcase.
llvm-svn: 77992
2009-08-03 20:36:38 +00:00
c28b306423
llvm_report_error already prints "LLVM ERROR:". So stop reporting errors like "LLVM ERROR: llvm: error:" or "LLVM ERROR: ERROR:".
...
llvm-svn: 77971
2009-08-03 13:33:33 +00:00
97f7dfb862
These are done.
...
llvm-svn: 77949
2009-08-03 04:08:36 +00:00
8b9deebba3
Use the i12 variant of load / store opcodes if offset is zero. Now we pass all of multisource as well.
...
llvm-svn: 77939
2009-08-03 02:38:06 +00:00
c3719c36e6
Move most targets TargetMachine constructor to only taking a target triple.
...
- The C, C++, MSIL, and Mips backends still need the module.
llvm-svn: 77927
2009-08-02 23:37:13 +00:00
31b44e8f6c
Normalize Subtarget constructors to take a target triple string instead of
...
Module*.
Also, dropped uses of TargetMachine where unnecessary. The only target which
still takes a TargetMachine& is Mips, I would appreciate it if someone would
normalize this to match other targets.
llvm-svn: 77918
2009-08-02 22:11:08 +00:00
1472cf5b3f
move dwarf debug info section selection stuff from TAI to
...
TLOF, unifying all the dwarf targets at the same time.
llvm-svn: 77889
2009-08-02 07:24:22 +00:00
8a0db7516e
ARM TAI no longer needs a TM, but createTargetAsmInfo() still does.
...
llvm-svn: 77878
2009-08-02 05:23:52 +00:00
e98a3c3ca3
Move the getInlineAsmLength virtual method from TAI to TII, where
...
the only real caller (GetFunctionSizeInBytes) uses it.
The custom ARM implementation of this is basically reimplementing
an assembler poorly for negligible gain. It should be removed
IMNSHO, but I'll leave that to ARMish folks to decide.
llvm-svn: 77877
2009-08-02 05:20:37 +00:00
1fe76c385b
turn some templated inline functions into static functions.
...
llvm-svn: 77873
2009-08-02 04:52:00 +00:00
fb53861ee0
remove the dead ELFTargetAsmInfo.h/cpp file. TargetAsmInfo
...
defaults to being ELF.
llvm-svn: 77866
2009-08-02 04:33:09 +00:00
b25afe081c
remove TargetAsmInfo::TM, which is now dead. The basic TAI class now
...
no longer depends on TM!
llvm-svn: 77863
2009-08-02 04:27:24 +00:00
4e7dfafc03
convert ctors/dtors section to be in TLOF instead of
...
TAI.
llvm-svn: 77842
2009-08-02 00:34:36 +00:00
b2bbb61f33
REmove dead fields of TAI.
...
llvm-svn: 77820
2009-08-01 22:40:22 +00:00
e64f48ba8b
Workaround a couple of Darwin assembler bugs.
...
llvm-svn: 77781
2009-08-01 06:13:52 +00:00
e6e8289d72
Split t2MOVCCs since some assemblers do not recognize mov shifted register alias with predicate.
...
llvm-svn: 77764
2009-08-01 01:43:45 +00:00
6ab54fdb0a
Fix Thumb2 function call isel. Thumb1 and Thumb2 should share the same
...
instructions for calls since BL and BLX are always 32-bit long and BX is always
16-bit long.
Also, we should be using BLX to call external function stubs.
llvm-svn: 77756
2009-08-01 00:16:10 +00:00
95d6325859
t2BR_JT is mov pc, it's 2 byte long, not 4.
...
llvm-svn: 77744
2009-07-31 22:22:22 +00:00
9eb3f88048
Thumb2 movcc need .w suffix.
...
llvm-svn: 77743
2009-07-31 22:21:55 +00:00
4d2c0f9008
switch off of 'Section' onto MCSection. We're not properly using
...
MCSection subclasses yet, but this is a step in the right direction.
llvm-svn: 77708
2009-07-31 18:48:30 +00:00
be8422e8e0
Until we have a "ALIGN" pseudo instruction, have asm printer emitted a .align
...
to ensure the instruction that follows a TBB (when the number of table entries
is odd) is 2-byte aligned.
Patch by Sandeep Patel.
llvm-svn: 77705
2009-07-31 18:35:56 +00:00
f6d0fa3d33
- Teach TBB / TBH offset limits are 510 and 131070 respectively since the offset
...
is scaled by two.
- Teach GetInstSizeInBytes about TBB and TBH.
llvm-svn: 77701
2009-07-31 18:28:05 +00:00
51d5b43cda
refactor section construction in TLOF to be through an explicit
...
initialize method, which can be called when an MCContext is available.
llvm-svn: 77687
2009-07-31 17:42:42 +00:00
5811ab5cf3
When fp is not eliminated, instructions with T2_i12 modes will be changed to T2_i8 ones. Take that into consideration when determining stack size limit for reserving register scavenging slot.
...
llvm-svn: 77642
2009-07-30 23:29:25 +00:00
5aae45fb6f
Remove redundant match for frame index from imm8 addrmode, it is handled by the imm12 addrmode.
...
llvm-svn: 77632
2009-07-30 22:45:52 +00:00
0bfc8312c2
Darwin assembler now recognizes "orn", so remove workaround.
...
llvm-svn: 77627
2009-07-30 21:51:41 +00:00
ce774e2383
Darwin assembler now supports "rrx", so remove workaround.
...
llvm-svn: 77625
2009-07-30 21:38:40 +00:00
79c079b478
Cleanup and include code selection for some frame index cases.
...
llvm-svn: 77622
2009-07-30 18:56:48 +00:00
cab137d294
Add missing D* register clobbers for Thumb-2 call.
...
llvm-svn: 77611
2009-07-30 18:01:09 +00:00
c667b60b93
add a random codegen deficiency.
...
llvm-svn: 77598
2009-07-30 16:08:58 +00:00
6afdc5e694
Switch obvious clients to Twine instead of utostr (when they were already using
...
a Twine, e.g., for names).
- I am a little ambivalent about this; we don't want the string conversion of
utostr, but using overload '+' mixed with string and integer arguments is
sketchy. On the other hand, this particular usage is something of an idiom.
llvm-svn: 77579
2009-07-30 04:20:37 +00:00
0dbdec8042
Lower a 128-bit BUILD_VECTOR with 2 elements to a pair of INSERT_VECTOR_ELTs.
...
llvm-svn: 77557
2009-07-30 00:31:25 +00:00
e3493a91cc
tbb / tbh instructions only branch forward, not backwards.
...
llvm-svn: 77522
2009-07-29 23:20:20 +00:00
1f58eed638
Add VFP3 D registers to the DPR register class.
...
llvm-svn: 77521
2009-07-29 23:03:41 +00:00
175bd14967
Make sure Thumb2 uses the right call instructions.
...
llvm-svn: 77507
2009-07-29 21:26:42 +00:00
ee68a483ec
Give getPointerRegClass() a "kind" value so that targets can
...
support multiple different pointer register classes.
llvm-svn: 77501
2009-07-29 20:31:52 +00:00
0d98d8b8b3
- Fix an obvious copy and paste error.
...
- Darwin Thumb2 call clobbers r9.
llvm-svn: 77500
2009-07-29 20:10:36 +00:00
cf19885a32
Change Neon VLDn intrinsics to return multiple values instead of really
...
wide vectors. Likewise, change VSTn intrinsics to take separate arguments
for each vector in a multi-vector struct. Adjust tests accordingly.
llvm-svn: 77468
2009-07-29 16:39:22 +00:00
5034329f8d
pass the mangler down into the various SectionForGlobal methods.
...
No functionality change.
llvm-svn: 77432
2009-07-29 05:09:30 +00:00
c6d70ae063
Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword.
...
llvm-svn: 77422
2009-07-29 02:18:14 +00:00
0830980141
Thumb-2: fix typo that caused incorrect stack elimination for VFP operations and very large stack frames.
...
llvm-svn: 77401
2009-07-28 23:52:33 +00:00
a4f43fb5dd
Rename MDNode.h header. It defines MDnode and other metadata classes.
...
New name is Metadata.h.
llvm-svn: 77370
2009-07-28 21:49:47 +00:00
c8bed03349
In thumb2 mode, add pc is unpredictable. Use add + mov pc instead (that is until more optimization goes in).
...
llvm-svn: 77364
2009-07-28 20:53:24 +00:00
68bb69d6e3
Remove support for ORN to workaround <rdar://problem/7096522>.
...
llvm-svn: 77363
2009-07-28 20:51:25 +00:00
d6b4b29706
more simplifications and cleanup. :)
...
llvm-svn: 77350
2009-07-28 18:48:43 +00:00
865c6298d7
Add workaround for <rdar://problem/7098328>.
...
llvm-svn: 77340
2009-07-28 18:15:38 +00:00
a3242e93b7
the apple "ld_classic" linker doesn't support .literal16 in 32-bit
...
mode, and "ld64" (the default linker) falls back to it in -static
mode.
llvm-svn: 77334
2009-07-28 17:50:28 +00:00
e82862e24e
Add Thumb-2 patterns for ARMsrl_flag and ARMsra_flag.
...
llvm-svn: 77329
2009-07-28 17:06:49 +00:00
12da273f90
tADDrSPI doesn't have a predicate operand, but tADDhirr and tADDi3 have.
...
llvm-svn: 77305
2009-07-28 07:38:35 +00:00
73a5119675
Code clean up. No functionality changes.
...
llvm-svn: 77301
2009-07-28 06:24:12 +00:00
780748d565
- More refactoring. This gets rid of all of the getOpcode calls.
...
- This change also makes it possible to switch between ARM / Thumb on a
per-function basis.
- Fixed thumb2 routine which expand reg + arbitrary immediate. It was using
using ARM so_imm logic.
- Use movw and movt to do reg + imm when profitable.
- Other code clean ups and minor optimizations.
llvm-svn: 77300
2009-07-28 05:48:47 +00:00
5e693ed07b
Rip all of the global variable lowering logic out of TargetAsmInfo. Since
...
it is highly specific to the object file that will be generated in the end,
this introduces a new TargetLoweringObjectFile interface that is implemented
for each of ELF/MachO/COFF/Alpha/PIC16 and XCore.
Though still is still a brutal and ugly refactoring, this is a major step
towards goodness.
This patch also:
1. fixes a bunch of dangling pointer problems in the PIC16 backend.
2. disables the TargetLowering copy ctor which PIC16 was accidentally using.
3. gets us closer to xcore having its own crazy target section flags and
pic16 not having to shadow sections with its own objects.
4. fixes wierdness where ELF targets would set CStringSection but not
CStringSection_. Factor the code better.
5. fixes some bugs in string lowering on ELF targets.
llvm-svn: 77294
2009-07-28 03:13:23 +00:00
57b51d9f82
ORN does not require (and can not have) the ".w" suffix. "Orthogonality" is a dirty word at ARM.
...
llvm-svn: 77275
2009-07-27 23:34:12 +00:00
e5b969f6a6
Remove TPat. No patterns depend on just isThumb(). Must use either T1Pat (isThumb1Only()) or T2Pat (is Thumb2).
...
llvm-svn: 77242
2009-07-27 19:59:26 +00:00
375a01c34a
remove dead code.
...
llvm-svn: 77233
2009-07-27 19:00:33 +00:00
38b7eee164
More DCE.
...
llvm-svn: 77231
2009-07-27 18:48:45 +00:00
0e075e2429
convertToThreeAddress can't handle Thumb2 instructions (which don't have same address mode as ARM instructions).
...
llvm-svn: 77230
2009-07-27 18:44:00 +00:00
18688f431d
Get rid of more dead code.
...
llvm-svn: 77227
2009-07-27 18:38:54 +00:00
239ed4b343
Cosmetic change.
...
llvm-svn: 77222
2009-07-27 18:31:40 +00:00
8f2ed1bc5a
Clean up.
...
llvm-svn: 77221
2009-07-27 18:25:24 +00:00
056c669e93
Get rid of some more getOpcode calls.
...
This also fixes potential problems in ARMBaseInstrInfo routines not recognizing thumb1 instructions when 32-bit and 16-bit instructions mix.
llvm-svn: 77218
2009-07-27 18:20:05 +00:00
007031d1b4
Thumb-2 does not have RSC.
...
llvm-svn: 77201
2009-07-27 16:39:05 +00:00
782f242fd7
Add ".w" suffix for wide thumb-2 instructions.
...
llvm-svn: 77199
2009-07-27 16:31:55 +00:00
86b7255776
Eliminate getNamed/getUnnamedSection, adding a new and unified getOrCreateSection
...
instead.
llvm-svn: 77186
2009-07-27 06:17:14 +00:00
149465ea06
Eliminate SectionFlags, just embed a SectionKind into Section
...
instead and drive things based off of that.
llvm-svn: 77184
2009-07-27 05:32:16 +00:00
371ec9e810
If CPSR is modified but the def is dead, then it's ok to fold the load / store.
...
llvm-svn: 77182
2009-07-27 04:18:04 +00:00
c47e109335
Use t2LDRi12 and t2STRi12 to load / store to / from stack frames. Eliminate more getOpcode calls.
...
llvm-svn: 77181
2009-07-27 03:14:20 +00:00
186332f898
Use the right instructions to copy between GPR and the more strictive tGPR classes. t2MOV does not match the RC requirements.
...
llvm-svn: 77175
2009-07-27 00:33:08 +00:00
0e5b149930
Merge isLoadFromStackSlot into one since it behaves the same regardless of sub-target.
...
llvm-svn: 77174
2009-07-27 00:24:36 +00:00
26b51b15ed
Just use a single isMoveInstr to catch all the cases.
...
llvm-svn: 77173
2009-07-27 00:05:15 +00:00
faede73a32
Rename tMOVhi2lor to tMOVgpr2tgpr. It's not moving from a high register to a low register. It's moving from a GPR register class to a more restrictive tGPR class. Also change tMOVlor2hir, and tMOVhir2hir.
...
llvm-svn: 77172
2009-07-26 23:59:01 +00:00
602d44fa70
untangle a TargetAsmInfo hack where ELFTargetAsmInfo would create a
...
'unnamed' bss section, but some impls would want a named one. Since
they don't have consistent behavior, just make each target do their
own thing, instead of doing something "sortof common" then having
targets change immutable objects later.
llvm-svn: 77165
2009-07-26 19:23:28 +00:00
8953720f23
Refactor. Get rid of a few more getOpcode() calls.
...
llvm-svn: 77164
2009-07-26 18:55:14 +00:00
9813b0b025
Eliminate some uses of DOUT, cerr, and getNameStart().
...
llvm-svn: 77145
2009-07-26 07:49:05 +00:00
ee01b242e8
Factor commonality in triple match routines into helper template for registering
...
classes, and migrate existing targets over.
llvm-svn: 77126
2009-07-26 05:03:33 +00:00
bc981d8efa
Kill Target specific ModuleMatchQuality stuff.
...
- This was overkill and inconsistently implemented.
llvm-svn: 77114
2009-07-26 02:22:58 +00:00
8a37bbebfd
Add support for ARM Neon VREV instructions.
...
Patch by Anton Korzh, with some modifications from me.
llvm-svn: 77101
2009-07-26 00:39:34 +00:00
e03eecb75f
Remove Value::{isName, getNameRef}.
...
Also, change MDString to use a StringRef.
llvm-svn: 77098
2009-07-25 23:55:21 +00:00
691a4784db
Simplify JIT target selection.
...
- Instead of requiring targets to define a JIT quality match function, we just
have them specify if they support a JIT.
- Target selection for the JIT just gets the host triple and looks for the best
target which matches the triple and has a JIT.
llvm-svn: 77060
2009-07-25 10:09:50 +00:00
5680b4f285
Add new helpers for registering targets.
...
- Less boilerplate == good.
llvm-svn: 77052
2009-07-25 06:49:55 +00:00
ea23c3ba46
80 col violation.
...
llvm-svn: 77041
2009-07-25 01:55:25 +00:00
c1a5cfa9a0
Get rid of a couple of unnecessary getOpcode calls.
...
llvm-svn: 77035
2009-07-25 01:25:08 +00:00
b2c22f00de
Another TODO.
...
llvm-svn: 77026
2009-07-25 00:39:37 +00:00
f3a1fce8ae
Change Thumb2 jumptable codegen to one that uses two level jumps:
...
Before:
adr r12, #LJTI3_0_0
ldr pc, [r12, +r0, lsl #2 ]
LJTI3_0_0:
.long LBB3_24
.long LBB3_30
.long LBB3_31
.long LBB3_32
After:
adr r12, #LJTI3_0_0
add pc, r12, +r0, lsl #2
LJTI3_0_0:
b.w LBB3_24
b.w LBB3_30
b.w LBB3_31
b.w LBB3_32
This has several advantages.
1. This will make it easier to optimize this to a TBB / TBH instruction +
(smaller) table.
2. This eliminate the need for ugly asm printer hack to force the address
into thumb addresses (bit 0 is one).
3. Same codegen for pic and non-pic.
4. This eliminate the need to align the table so constantpool island pass
won't have to over-estimate the size.
Based on my calculation, the later is probably slightly faster as well since
ldr pc with shifter address is very slow. That is, it should be a win as long
as the HW implementation can do a reasonable job of branch predict the second
branch.
llvm-svn: 77024
2009-07-25 00:33:29 +00:00
0dd5e1ed39
More migration to raw_ostream, the water has dried up around the iostream hole.
...
- Some clients which used DOUT have moved to DEBUG. We are deprecating the
"magic" DOUT behavior which avoided calling printing functions when the
statement was disabled. In addition to being unnecessary magic, it had the
downside of leaving code in -Asserts builds, and of hiding potentially
unnecessary computations.
llvm-svn: 77019
2009-07-25 00:23:56 +00:00
f297256136
ARM code emitter can't handle Thumb2 instructions yet. So don't even try.
...
llvm-svn: 77018
2009-07-25 00:13:11 +00:00
edb4a70325
Revert the ConstantInt constructors back to their 2.5 forms where possible, thanks to contexts-on-types. More to come.
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llvm-svn: 77011
2009-07-24 23:12:02 +00:00
c64ce30c67
Uh. It would be useful to actually print the operand.
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llvm-svn: 77004
2009-07-24 20:47:38 +00:00
c26c76ec1d
Disable my constant island pass optimization (to make use soimm more effectively). It caused infinite looping on lencod.
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llvm-svn: 76995
2009-07-24 19:31:03 +00:00
5a49c54061
Add a workaround for Darwin assembler bug where it's not setting the thumb bit in Thumb2 jumptable entries. We now pass Olden.
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llvm-svn: 76991
2009-07-24 18:54:23 +00:00
666c912ce3
Make sure thumb2 jumptable entries are aligned.
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llvm-svn: 76986
2009-07-24 18:20:44 +00:00
886f303480
Clean up.
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llvm-svn: 76984
2009-07-24 18:20:16 +00:00
986fc8e74b
Replace use of std::set with SmallPtrSet.
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llvm-svn: 76983
2009-07-24 18:19:46 +00:00
95fc6ee51a
Remove unused member functions.
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llvm-svn: 76960
2009-07-24 07:43:59 +00:00
1553fdee55
use section flags more correctly.
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llvm-svn: 76944
2009-07-24 04:08:17 +00:00
07bd1cd8c5
reduce api exposure: clients shouldn't call SectionKindForGlobal directly.
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llvm-svn: 76941
2009-07-24 03:49:17 +00:00
c3259f3ffb
Thumb2 should use the register scavenger.
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llvm-svn: 76930
2009-07-24 01:05:51 +00:00
6cfbe61361
FLDD, FLDS, FCPYD, FCPYS, FSTD, FSTS, VMOVD, VMOVQ maps to the same instructions on all sub-targets.
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llvm-svn: 76925
2009-07-24 00:53:56 +00:00
cdd405d804
Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index elimination more exactly for Thumb-2 to get better code gen.
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llvm-svn: 76919
2009-07-24 00:16:18 +00:00
Anton Korobeynikov