eab572a8ff
EXTRACT_VECTOR_ELEMENT can have result type different from element type.
...
Remove the assertion and generalize the code for ARM NEON stuff.
llvm-svn: 80498
2009-08-30 17:14:54 +00:00
ece642a54c
Do not assert on too wide splats we don't support.
...
llvm-svn: 80409
2009-08-29 00:08:18 +00:00
cd41d07f29
Add missed extract_element pattern
...
llvm-svn: 80408
2009-08-28 23:41:26 +00:00
43b9ca6f42
Let Darwin linker auto-synthesize stubs and lazy-pointers. This deletes a bunch of nasty code in ARM asm printer.
...
llvm-svn: 80404
2009-08-28 23:18:09 +00:00
3033db2448
Fix -Asserts warning, round two.
...
llvm-svn: 80354
2009-08-28 08:08:22 +00:00
4047b53a40
Print a nl before pic labels so they start at a new line. This makes assembly more readable.
...
llvm-svn: 80350
2009-08-28 06:59:37 +00:00
d46e3466e7
Fix -Asserts warning.
...
llvm-svn: 80338
2009-08-28 05:47:56 +00:00
6da267de23
v4, v5 does not support sxtb / sxth.
...
llvm-svn: 80322
2009-08-28 00:31:43 +00:00
ba53af58f0
Hopefully the final missing part :(
...
scalar_to_vector is fully legal now
llvm-svn: 80251
2009-08-27 16:25:49 +00:00
076f105d86
Forgot about actual change :)
...
llvm-svn: 80250
2009-08-27 16:10:17 +00:00
58ebae4acd
Transform float scalar_to_vector into subreg accesses.
...
No idea whether this is profitable or not.
llvm-svn: 80245
2009-08-27 14:38:44 +00:00
209baa5c48
STRD and LDRD require ARMv5TE, not just ARMv5T.
...
See http://llvm.org/PR4687 for more info and links.
llvm-svn: 80244
2009-08-27 14:14:21 +00:00
7a37b1a2ca
Fix PR4789. Teach eliminateFrameIndex how to handle VLDRQ and VSTRQ which cannot fold any immediate offset.
...
llvm-svn: 80191
2009-08-27 01:23:50 +00:00
e0636a7aed
Remove unneeded ARM-specific DAG nodes for VLD* and VST* Neon operations.
...
The instructions can be selected directly from the intrinsics. We will need
to add some ARM-specific nodes for VLD/VST of 3 and 4 128-bit vectors, but
those are not yet implemented.
llvm-svn: 80117
2009-08-26 17:39:53 +00:00
0f756b27ae
Expand scalar_to_vector - we don't have any isel logic for it now
...
llvm-svn: 80107
2009-08-26 16:26:09 +00:00
f1beef9f48
Remove some unused SDNode definitions.
...
llvm-svn: 80015
2009-08-25 17:52:39 +00:00
9129376719
Expose the instruction contraint string as an argument to the NLdSt class.
...
llvm-svn: 80011
2009-08-25 17:46:06 +00:00
6bbeda41b9
Make linkerprivate work for ARM and PPC. Testcase covers
...
all Darwin targets; could be split into separate tests for
the chip subdirectories, but from Chris' last mail on testing
I assume he'd rather have only one test. Generic seems to be
the best available, maybe there should be a Darwin subdirectory?
llvm-svn: 79877
2009-08-24 01:03:42 +00:00
30ebdc4311
remove the last uses of Config/alloca.h
...
llvm-svn: 79873
2009-08-23 22:57:38 +00:00
940fbb0e3c
Remove Streams.h from the targets.
...
llvm-svn: 79853
2009-08-23 11:52:17 +00:00
af29ea6d57
eliminate the last DOUTs from the targets.
...
llvm-svn: 79833
2009-08-23 06:49:22 +00:00
a6f074fb3a
remove various std::ostream version of printing methods from
...
MachineInstr and MachineOperand. This required eliminating a
bunch of stuff that was using DOUT, I hope that bill doesn't
mind me stealing his fun. ;-)
llvm-svn: 79813
2009-08-23 03:41:05 +00:00
f7b571726a
Forgot to update some CMakeLists.
...
llvm-svn: 79780
2009-08-22 22:20:11 +00:00
e9a75a6654
rename TAI -> MAI, being careful not to make MAILJMP instructions :)
...
llvm-svn: 79777
2009-08-22 21:43:10 +00:00
054574666a
rename COFFMCAsmInfo -> MCAsmInfoCOFF, likewise for darwin.
...
llvm-svn: 79773
2009-08-22 21:03:30 +00:00
7b26fce23e
Rename TargetAsmInfo (and its subclasses) to MCAsmInfo.
...
llvm-svn: 79763
2009-08-22 20:48:53 +00:00
0939595711
Record variable debug info at ISel time directly.
...
llvm-svn: 79742
2009-08-22 17:12:53 +00:00
682d8c1881
Make x86 test actually test x86 code generation. Fix the
...
construct on ARM, which was breaking by coincidence, and add a similar
testcase for ARM.
llvm-svn: 79719
2009-08-22 03:13:10 +00:00
ceffeb6abd
Rename ARM "lane_cst" operands to "nohash_imm" since they are used for
...
several things other than Neon vector lane numbers. For inline assembly
operands with a "c" print code, check that they really are immediates.
llvm-svn: 79676
2009-08-21 21:58:55 +00:00
a70623102e
Match VTRN, VZIP, and VUZP shuffles. Restore the tests for these operations,
...
now using shuffles instead of intrinsics.
llvm-svn: 79673
2009-08-21 20:54:19 +00:00
232b19c3d5
Fix some typos and use type-based isel for VZIP/VUZP/VTRN
...
llvm-svn: 79625
2009-08-21 12:41:42 +00:00
9a232f46a8
Add lowering of ARM 4-element shuffles to multiple instructios via perfectshuffle-generated table.
...
llvm-svn: 79624
2009-08-21 12:41:24 +00:00
ce3ff1be8a
Add nodes & dummy matchers for some v{zip,uzp,trn} instructions
...
llvm-svn: 79622
2009-08-21 12:40:50 +00:00
e3046618de
Expand EXTRACT_SUBVECTOR
...
llvm-svn: 79621
2009-08-21 12:40:35 +00:00
38f284f2ae
Provide vext.{16,32}
...
llvm-svn: 79620
2009-08-21 12:40:21 +00:00
c32e99e3ed
Use masks not nodes for vector shuffle predicates. Provide set of 'legal' masks, so legalizer won't infinite cycle
...
llvm-svn: 79619
2009-08-21 12:40:07 +00:00
51c7aa04ec
Remove Neon intrinsics for VZIP, VUZP, and VTRN. We will represent these as
...
vector shuffles. Temporarily remove the tests for these operations until the
new implementation is working.
llvm-svn: 79579
2009-08-21 00:01:42 +00:00
01de985ae6
Fix an obvious copy-n-paste bug.
...
llvm-svn: 79535
2009-08-20 17:01:04 +00:00
a7c2dfbca1
Update Cortex-A8 instruction itineraries for integer instructions.
...
llvm-svn: 79436
2009-08-19 18:00:44 +00:00
32cd8550ce
Add support for Neon VEXT (vector extract) shuffles.
...
This is derived from a patch by Anton Korzh. I modified it to recognize
the VEXT shuffles during legalization and lower them to a target-specific
DAG node.
llvm-svn: 79428
2009-08-19 17:03:43 +00:00
4b7dadb76e
eliminate AsmPrinter::SwitchToSection and just have clients
...
talk to the MCStreamer directly instead.
llvm-svn: 79405
2009-08-19 05:49:37 +00:00
36d747745e
Simplify RegScavenger::FindUnusedReg.
...
- Drop the Candidates argument and fix all callers. Now that RegScavenger
tracks available registers accurately, there is no need to restict the
search.
- Make sure that no aliases of the found register are in use. This was a potential bug.
llvm-svn: 79369
2009-08-18 21:14:54 +00:00
dd406177de
Fix revsh pattern.
...
llvm-svn: 79318
2009-08-18 05:43:23 +00:00
2c64130c43
Fix use after free in Thumb2SizeReduction (PR4707). A MachineInstr was used after erasure.
...
llvm-svn: 79189
2009-08-16 11:56:42 +00:00
bae6b2cca3
Reapply r79127. It was fixed by d0k.
...
llvm-svn: 79136
2009-08-15 21:21:19 +00:00
d3fade656f
Revert r79127. It was causing compilation errors.
...
llvm-svn: 79135
2009-08-15 21:14:01 +00:00
52d4e64711
Change allowsUnalignedMemoryAccesses to take type argument since some targets
...
support unaligned mem access only for certain types. (Should it be size
instead?)
ARM v7 supports unaligned access for i16 and i32, some v6 variants support it
as well.
llvm-svn: 79127
2009-08-15 19:23:44 +00:00
6ddd7bcdd1
Turn on if-conversion for thumb2.
...
llvm-svn: 79084
2009-08-15 07:59:10 +00:00
75c9e535c6
Do not use frame register to reference fixed stack objects if the function is frameless.
...
llvm-svn: 79067
2009-08-15 02:05:35 +00:00
7dae88d2c9
Leaf functions which do not save CSRs can be frameless even with -disable-fp-elim.
...
llvm-svn: 79039
2009-08-14 20:48:13 +00:00
a6b3ce203a
Allow targets to specify their choice of calling conventions per
...
libcall. Take advantage of this in the ARM backend to rectify broken
choice of CC when hard float is in effect. PIC16 may want to see if
it could be of use in MakePIC16Libcall, which works unchanged.
Patch by Sandeep!
llvm-svn: 79033
2009-08-14 20:10:52 +00:00
dc49a8d3f1
Add Thumb2 lsr hooks.
...
llvm-svn: 79032
2009-08-14 20:09:37 +00:00
09c070f4ce
80 col violation.
...
llvm-svn: 79026
2009-08-14 19:11:20 +00:00
9a58aff837
Indentation.
...
llvm-svn: 79022
2009-08-14 19:01:37 +00:00
e41903b10d
Also shrink immediate branches; also more assembler workarounds.
...
llvm-svn: 79014
2009-08-14 18:31:44 +00:00
6f34e278c7
Now that all the legal Neon shuffles (or at least the ones that have been
...
implemented so far) are recognized during legalization, it is easy to fall
back to the default expansion for other shuffles.
llvm-svn: 78995
2009-08-14 05:16:33 +00:00
eb54d51759
Create a new ARM-specific DAG node, VDUP, to represent a splat from a
...
scalar_to_vector. Generate these VDUP nodes during legalization instead
of trying to recognize the pattern during selection.
llvm-svn: 78994
2009-08-14 05:13:08 +00:00
cce31f6831
During legalization, change Neon vdup_lane operations from shuffles to
...
target-specific VDUPLANE nodes. This allows the subreg handling for the
quad-register version to be done easily with Pats in the .td file, instead
of with custom code in ARMISelDAGToDAG.cpp.
llvm-svn: 78993
2009-08-14 05:08:32 +00:00
db73d68cbe
Shrink ADR and LDR from constantpool late during constantpool island pass.
...
llvm-svn: 78970
2009-08-14 00:32:16 +00:00
76fa6e6a8f
New entry.
...
llvm-svn: 78968
2009-08-14 00:16:47 +00:00
55f1c09e31
Push LLVMContexts through the IntegerType APIs.
...
llvm-svn: 78948
2009-08-13 21:58:54 +00:00
86c065dd68
Revert 78892 and 78895, these break generating working executables on
...
x86_64-apple-darwin10.
--- Reverse-merging r78895 into '.':
U test/CodeGen/PowerPC/2008-12-12-EH.ll
U lib/Target/DarwinTargetAsmInfo.cpp
--- Reverse-merging r78892 into '.':
U include/llvm/Target/DarwinTargetAsmInfo.h
U lib/Target/X86/X86TargetAsmInfo.cpp
U lib/Target/X86/X86TargetAsmInfo.h
U lib/Target/ARM/ARMTargetAsmInfo.h
U lib/Target/ARM/ARMTargetMachine.cpp
U lib/Target/ARM/ARMTargetAsmInfo.cpp
U lib/Target/PowerPC/PPCTargetAsmInfo.cpp
U lib/Target/PowerPC/PPCTargetAsmInfo.h
U lib/Target/PowerPC/PPCTargetMachine.cpp
G lib/Target/DarwinTargetAsmInfo.cpp
llvm-svn: 78919
2009-08-13 17:03:38 +00:00
eba70d85cf
Add missing defs of R2 and D1.
...
llvm-svn: 78918
2009-08-13 16:59:44 +00:00
a9c2aad939
Finalize itineraries for cortex-a8 integer multiply
...
llvm-svn: 78908
2009-08-13 15:51:13 +00:00
695e1c6087
Remove unnecessary newline
...
llvm-svn: 78905
2009-08-13 15:12:16 +00:00
c96e88f8a5
Correct comment wording
...
llvm-svn: 78904
2009-08-13 15:11:43 +00:00
f59e9f4288
tPOP_RET now has predicate operands.
...
llvm-svn: 78898
2009-08-13 06:05:07 +00:00
3e4c012d54
Add a fixme message about canonicalizing floating-point vector types.
...
llvm-svn: 78897
2009-08-13 06:01:30 +00:00
ef6e602bf4
Revert r78852 for now. I want to do this differently, but I don't have time
...
to fix it tonight.
llvm-svn: 78896
2009-08-13 05:58:56 +00:00
e5801bd220
It's ok to spill a tGPR register as long as it's still allocated a low register.
...
llvm-svn: 78893
2009-08-13 05:40:51 +00:00
eb68198145
fix a minor fixme. When building with SL and later tools, the ".eh" symbols
...
don't need to be exported from the .o files.
llvm-svn: 78892
2009-08-13 05:30:22 +00:00
607cd3b63a
Change MCSectionELF to represent a section semantically instead of
...
syntactically as a string, very similiar to what Chris did with MachO.
The parsing support and validation is not introduced yet.
llvm-svn: 78890
2009-08-13 05:07:35 +00:00
c6800b55e6
Add a comment to describe why vector shuffles are legalized to custom DAG nodes.
...
llvm-svn: 78884
2009-08-13 02:13:04 +00:00
fcd6361ad1
Use cast<> instead of dyn_cast<> in places where the type is known.
...
llvm-svn: 78881
2009-08-13 01:57:47 +00:00
ef3d457126
Various AsmWriter output cleanups. Use WriteAsOperand instead of
...
PrintUnmangledNameSafely.
llvm-svn: 78878
2009-08-13 01:36:44 +00:00
ff2db10211
Recognize Neon VDUP shuffles during legalization instead of selection.
...
llvm-svn: 78852
2009-08-12 22:54:19 +00:00
ea3a402ae7
Recognize Neon VREV shuffles during legalization instead of selection.
...
llvm-svn: 78850
2009-08-12 22:31:50 +00:00
1432ef864e
This void is implicit in C++.
...
llvm-svn: 78848
2009-08-12 22:10:57 +00:00
4b35448360
Generate Neon VTBL and VTBX instructions from the corresponding intrinsics.
...
llvm-svn: 78835
2009-08-12 20:51:55 +00:00
aee7e49c50
PredCC is meant to be 2 bits wide, like PredCC1.
...
llvm-svn: 78829
2009-08-12 18:35:50 +00:00
b369ee4c48
Enhance the InstrStage object to enable the specification of an Itinerary with overlapping stages. The default is to maintain the current behavior that the "next" stage immediately follows the previous one.
...
llvm-svn: 78827
2009-08-12 18:31:53 +00:00
3cfc6463c9
Add catch block handling to SjLj exception handling.
...
llvm-svn: 78817
2009-08-12 17:38:44 +00:00
25cae66713
Fix TableGen warnings. This partly reverts my previous change to this file,
...
leaving the mayLoad and mayStore settings around only the load/store
instructions where those can't be inferred from the patterns.
llvm-svn: 78815
2009-08-12 17:04:56 +00:00
a5fdfac6ca
register naming cleanup (s/ip/r12/)
...
llvm-svn: 78806
2009-08-12 15:21:13 +00:00
9a6cf91261
Change TargetAsmInfo to be constructed via TargetRegistry from a Target+Triple
...
pair instead of from a virtual method on TargetMachine. This cuts the final
ties of TargetAsmInfo to TargetMachine, meaning that MC can now use
TargetAsmInfo.
llvm-svn: 78802
2009-08-12 07:22:17 +00:00
bb2af3555c
Shrink Thumb2 movcc instructions.
...
llvm-svn: 78790
2009-08-12 05:17:19 +00:00
81348021b1
Remove another Darwin assembler workaround.
...
llvm-svn: 78779
2009-08-12 02:07:19 +00:00
fd10869d4b
80 col violation.
...
llvm-svn: 78778
2009-08-12 02:03:03 +00:00
608d92c943
Remove an Darwin assembler workaround.
...
llvm-svn: 78777
2009-08-12 01:56:42 +00:00
1e6c2a1c17
Shrink ADDS, ADC, RSB, and SUBS.
...
llvm-svn: 78776
2009-08-12 01:49:45 +00:00
f042eadd1e
Add missing chain operands for VLD* and VST* instructions.
...
Set "mayLoad" and "mayStore" on the load/store instructions.
llvm-svn: 78761
2009-08-12 00:49:01 +00:00
f6a9d06241
Shrinkify Thumb2 r = add sp, imm.
...
llvm-svn: 78745
2009-08-11 23:00:31 +00:00
abdcbc7ef2
Change the asmprinter to print the comment character before the
...
"inlineasmstart/end" strings so that the contents of the directive
are separate from the comment character. This lets elf targets
get #APP/#NOAPP for free even if they don't use "#" as the comment
character. This also allows hoisting the darwin stuff up to the
shared TAI class.
llvm-svn: 78737
2009-08-11 22:39:40 +00:00
fd5defed1d
Allow a zero cycle stage to reserve/require a FU without advancing the cycle counter.
...
llvm-svn: 78736
2009-08-11 22:38:43 +00:00
54075a78b4
factorize more darwin TAI stuff. Note that this gives
...
darwin/arm support for .no_dead_strip
llvm-svn: 78734
2009-08-11 22:31:42 +00:00
6747b39ca5
factorize darwin ProtectedDirective and SetDirective.
...
llvm-svn: 78732
2009-08-11 22:22:44 +00:00
d832c8e87c
all darwin targets have .space and .zerofill, pull up.
...
llvm-svn: 78730
2009-08-11 22:17:31 +00:00
f710f71839
eliminate template from arm TAI
...
llvm-svn: 78729
2009-08-11 22:14:59 +00:00
7faf1fd9a0
move LCOMMDirective = "\t.lcomm\t" up to DarwinTAI, eliminate
...
template in PPC backend for TAI.
llvm-svn: 78727
2009-08-11 22:06:07 +00:00
cc9ca3500d
Shrinkify Thumb2 load / store multiple instructions.
...
llvm-svn: 78717
2009-08-11 21:11:32 +00:00
9f94459d24
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while
...
the latter is capable of representing either a primitive or an extended type.
llvm-svn: 78713
2009-08-11 20:47:22 +00:00
2c30970b22
pass the TargetTriple down from each target ctor to the
...
LLVMTargetMachine ctor. It is currently unused.
llvm-svn: 78711
2009-08-11 20:42:37 +00:00
fe27130454
split "JumpTableDirective" (an existing hack) into a PIC and nonPIC
...
version. This allows TAI implementations to specify the directive to use
based on the mode being codegen'd for.
The real fix for this is to remove JumpTableDirective, but I don't feel
like diving into the jumptable snarl just now.
llvm-svn: 78709
2009-08-11 20:30:58 +00:00
841850ed26
Add Thumb2 eh_sjlj_setjmp implementation
...
llvm-svn: 78701
2009-08-11 19:42:21 +00:00
1d5350c08f
fix GetInstSizeInBytes for eh_sjlj_setjmp
...
llvm-svn: 78683
2009-08-11 17:08:15 +00:00
eda08015ee
This void is implicit in C++.
...
llvm-svn: 78678
2009-08-11 16:03:08 +00:00
f24f9d9cb6
Whitespace cleanup. Remove trailing whitespace.
...
llvm-svn: 78666
2009-08-11 15:33:49 +00:00
74eb9e7bfd
Move ~ARMConstantPoolValue() to the .cpp file to avoid needing to include <cstdlib> in the header.
...
llvm-svn: 78665
2009-08-11 15:26:27 +00:00
806845daec
Fix the previous accidental commit. Now shrinking common Thumb2 load / store instructions.
...
llvm-svn: 78659
2009-08-11 09:37:40 +00:00
3606467709
Fix Thumb2 load / store addressing mode matching code. Do not use so_reg form to
...
match base only address, i.e. [r] since Thumb2 requires a offset register field.
For those, use [r + imm12] where the immediate is zero.
Note the generated assembly code does not look any different after the patch.
But the bug would have broken the JIT (if there is Thumb2 support) and it can
break later passes which expect the address mode to be well-formed.
llvm-svn: 78658
2009-08-11 08:52:18 +00:00
d4d352c663
80 column violation.
...
llvm-svn: 78657
2009-08-11 08:47:46 +00:00
192d7c0752
Cosmetic changes.
...
llvm-svn: 78655
2009-08-11 07:36:14 +00:00
6e62e93a8d
Adding a blank line back.
...
llvm-svn: 78654
2009-08-11 07:32:58 +00:00
12842f9865
Use vAny type to get rid of Neon intrinsics that differed only in whether
...
the overloaded vector types allowed floating-point or integer vector elements.
Most of these operations actually depend on the element type, so bitcasting
was not an option.
If you include the vpadd intrinsics that I updated earlier, this gets rid
of 20 intrinsics.
llvm-svn: 78646
2009-08-11 05:39:44 +00:00
741a9c7bf6
Use new EVT::vAny type to combine Neon intrinsics for VPADD.
...
llvm-svn: 78632
2009-08-11 01:15:26 +00:00
b80734bb15
Fix bug in NEON convert for single-precision FP. This also fixes the tblgen warnings.
...
llvm-svn: 78629
2009-08-11 01:07:38 +00:00
9382d5ac05
Add stdlib.h
...
llvm-svn: 78627
2009-08-11 00:20:00 +00:00
693e36a3e8
SjLj based exception handling unwinding support. This patch is nasty, brutish
...
and short. Well, it's kinda short. Definitely nasty and brutish.
The front-end generates the register/unregister calls into the SjLj runtime,
call-site indices and landing pad dispatch. The back end fills in the LSDA
with the call-site information provided by the front end. Catch blocks are
not yet implemented.
Built on Darwin and verified no llvm-core "make check" regressions.
llvm-svn: 78625
2009-08-11 00:09:57 +00:00
475f8a4fa2
Enable Thumb2 instruction shrinking (32-bit to 16-bit) pass. Convert a bunch of thumb2 tests to FileCheck.
...
llvm-svn: 78622
2009-08-10 23:56:04 +00:00
733a64db57
Fix a bug where DAGCombine was producing an illegal ConstantFP
...
node after legalize, and remove the workaround code from the
ARM backend.
llvm-svn: 78615
2009-08-10 23:15:10 +00:00
53aa7a960c
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.
...
llvm-svn: 78610
2009-08-10 22:56:29 +00:00
85b5b027f7
Use NEON for single-precision int<->FP conversions.
...
llvm-svn: 78604
2009-08-10 22:17:39 +00:00
3e77df2bcd
SimpleValueType-ify a few more methods on TargetLowering.
...
llvm-svn: 78595
2009-08-10 20:46:15 +00:00
f72c13bdf5
Handle the constantfp created during post-legalization dag combiner phase.
...
llvm-svn: 78594
2009-08-10 20:25:59 +00:00
246617857f
Continue the SimpleValueType-ification.
...
llvm-svn: 78593
2009-08-10 20:18:46 +00:00
6c20391d38
split MachO section handling stuff out to its out .h/.cpp file.
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llvm-svn: 78576
2009-08-10 18:15:01 +00:00
fbcafd4c6c
arm only needs to emit one .align directive for hidden nlp's, not one
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per pointer.
llvm-svn: 78574
2009-08-10 18:02:16 +00:00
292472d3d3
make sure that arm nonlazypointers are aligned properly
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llvm-svn: 78573
2009-08-10 18:01:34 +00:00
62e053b790
Checkpoint scheduling itinerary changes.
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llvm-svn: 78564
2009-08-10 15:56:13 +00:00
5bb93ce769
Watch out for empty BB.
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llvm-svn: 78562
2009-08-10 08:10:13 +00:00
8a640ae504
rev, rev16, and revsh do not set CPSR.
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llvm-svn: 78561
2009-08-10 07:58:45 +00:00
f16a1d5b79
Duh. Most 16-bit Thumb rr instructions are two-address. Fix table.
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llvm-svn: 78560
2009-08-10 07:20:37 +00:00
1f5bee14a1
CPSR can be livein; transfer predicate operands correctly; tMUL is two-address.
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llvm-svn: 78559
2009-08-10 06:57:42 +00:00
092b701a2c
Add support for folding loads / stores into 16-bit moves used by Thumb2.
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llvm-svn: 78558
2009-08-10 06:32:05 +00:00
55c014a9f3
80 col violation.
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llvm-svn: 78557
2009-08-10 05:51:48 +00:00
f5b73869f2
Use tMOVgpr2gpr instead of t2MOVr.
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llvm-svn: 78556
2009-08-10 05:49:43 +00:00
51cbd2d6c4
Add support to reduce most of 32-bit Thumb2 arithmetic instructions.
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llvm-svn: 78550
2009-08-10 02:37:24 +00:00
5b4c308f0c
Always use the 16-bit tMOVgpr2gpr instead of the 32-bit t2MOVr.
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llvm-svn: 78549
2009-08-10 02:06:53 +00:00
cb307a27bf
Make the big switch: Change MCSectionMachO to represent a section *semantically*
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instead of syntactically as a string. This means that it keeps track of the
segment, section, flags, etc directly and asmprints them in the right format.
This also includes parsing and validation support for llvm-mc and
"attribute(section)", so we should now start getting errors about invalid
section attributes from the compiler instead of the assembler on darwin.
Still todo:
1) Uniquing of darwin mcsections
2) Move all the Darwin stuff out to MCSectionMachO.[cpp|h]
3) there are a few FIXMEs, for example what is the syntax to get the
S_GB_ZEROFILL segment type?
llvm-svn: 78547
2009-08-10 01:39:42 +00:00
d461c1c559
Add support to convert 32-bit instructions to 16-bit non-two-address ones.
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llvm-svn: 78540
2009-08-09 19:17:19 +00:00
cfed3005e5
Use subclassing to print lane-like immediates (w/o hash) eliminating
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'no_hash' modifier. Hopefully this will make Daniel happy :)
llvm-svn: 78514
2009-08-08 23:10:41 +00:00
1cb9396f4f
1. Make MCSection an abstract class.
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2. Move section switch printing to MCSection virtual method which takes a
TAI. This eliminates textual formatting stuff from TLOF.
3. Eliminate SwitchToSectionDirective, getSectionFlagsAsString, and
TLOFELF::AtIsCommentChar.
llvm-svn: 78510
2009-08-08 22:41:53 +00:00
ce7d14032b
now that getOrCreateSection is all object-file specific,
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give the impls an object-file-specific name. In the future
they can take different arguments etc.
llvm-svn: 78495
2009-08-08 20:22:20 +00:00
028f6dc4c2
Update CMake
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llvm-svn: 78475
2009-08-08 17:03:13 +00:00
7167f33872
Add insert_elt / extract_elt patterns for v4f32 stuff.
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Did anyone tests v4f32 ever?
llvm-svn: 78470
2009-08-08 14:06:07 +00:00
4218516f5d
Lane number should be printed w/o hash
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llvm-svn: 78469
2009-08-08 14:05:53 +00:00
887d05ce9b
Use VLDM / VSTM to spill/reload 128-bit Neon registers
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llvm-svn: 78468
2009-08-08 13:35:48 +00:00
e2231070ff
Implement Neon VZIP and VUZP instructions. These are very similar to VTRN,
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so I generalized the class for VTRN in the .td file to handle all 3 of them.
llvm-svn: 78460
2009-08-08 06:13:25 +00:00
db46af0461
Implement Neon VTRN instructions. For now, anyway, these are selected
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directly from the intrinsics produced by the frontend. If it is more
convenient to have a custom DAG node for using these to implement shuffles,
we can add that later.
llvm-svn: 78459
2009-08-08 05:53:00 +00:00
1be453b462
Add a skeleton Thumb2 instruction size reduction pass.
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llvm-svn: 78456
2009-08-08 03:21:23 +00:00
2aa91cc2be
Code refactoring. No functionality change.
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llvm-svn: 78455
2009-08-08 03:20:32 +00:00
274fcbe43e
tADDhirr should target GPR, not tGPR.
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llvm-svn: 78454
2009-08-08 03:19:44 +00:00
4dc201eb64
I can type.
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llvm-svn: 78453
2009-08-08 02:54:37 +00:00
b94284b5e2
make printInstruction return void since its result is omitted. Make the
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error condition get trapped with an assert.
llvm-svn: 78449
2009-08-08 01:32:19 +00:00
742db6a6d4
Make NEON single-precision FP support the default for cortex-a8 (again).
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llvm-svn: 78430
2009-08-07 23:32:33 +00:00
d28a26dfab
Unbreak the stuff
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llvm-svn: 78425
2009-08-07 22:51:13 +00:00
23b28cb824
2 more vdup.32 cases
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llvm-svn: 78419
2009-08-07 22:36:50 +00:00
fb93be2b6f
A big oops. Thumb1 default CC is a def of CPSR, not a use of CPSR.
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llvm-svn: 78418
2009-08-07 22:36:37 +00:00
6e130db3b7
Thumb2 32-bit ldm / stm needs .w suffix if submode is ia.
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llvm-svn: 78410
2009-08-07 21:19:10 +00:00
b64ec07ea6
This is done.
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llvm-svn: 78399
2009-08-07 19:34:52 +00:00
f0237b1aa6
Use 16-bit tMOVgpr2gpr instead of tMOVr to copy GPR registers in Thumb2 mode.
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llvm-svn: 78398
2009-08-07 19:34:35 +00:00
4c3b1ca5a0
Fix support to use NEON for single precision fp math.
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llvm-svn: 78397
2009-08-07 19:30:41 +00:00
82ff022ed2
Error out, rather than infinite looping, if constant island pass can't converge.
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llvm-svn: 78377
2009-08-07 07:35:21 +00:00
317bd7aab2
tBfar is bl, which clobbers LR.
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llvm-svn: 78370
2009-08-07 05:45:07 +00:00
a6d0afcb74
Fix a bunch of namespace pollution.
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llvm-svn: 78363
2009-08-07 01:32:21 +00:00
b972e5633f
It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing.
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This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time.
This fixes PR4659 and PR4682.
llvm-svn: 78361
2009-08-07 00:34:42 +00:00
0127031c20
Implement Neon VST[234] operations.
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llvm-svn: 78330
2009-08-06 18:47:44 +00:00
b062c236c5
Add parameter to pattern classes to enable an itinerary to be specified for instructions. For now just use the existing itineraries or NoItinerary.
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llvm-svn: 78321
2009-08-06 16:52:47 +00:00
488db94e7b
Neon does not actually have VLD{234}.64 instructions.
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These operations will have to be synthesized from other instructions.
llvm-svn: 78263
2009-08-06 00:24:27 +00:00
e148ceaf65
Add a new pre-allocation pass to assign adjacent registers for Neon instructions
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that have that constraint. This is currently just assigning a fixed set of
registers, and it only handles VLDn for n=2,3,4 with DPR registers.
I'm going to expand it to handle more operations next; we can make it smarter
once everything is working correctly.
llvm-svn: 78256
2009-08-05 23:12:45 +00:00
e5b5d8fbb3
When using NEON for single-precision FP, the NEON result must be placed in D0-D15 as these are the only D registers with S subregs. Introduce a new regclass to represent D0-D15 and use it in the NEON single-precision FP patterns.
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llvm-svn: 78244
2009-08-05 21:02:22 +00:00
ef98dbe3de
Remove redundand checks: the only way to have, e.g. f32 RegVT is exactly
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hardfloat case.
llvm-svn: 78237
2009-08-05 20:15:19 +00:00
ef42862ef5
Unbreak the stuff, this is ugly, but we cannot do better for now with 'plain' C calling conv.
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llvm-svn: 78232
2009-08-05 19:40:16 +00:00
22ef75155e
Missed pieces for ARM HardFP ABI.
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Patch by Sandeep Patel!
llvm-svn: 78225
2009-08-05 19:04:42 +00:00
4cc1feff4f
Remove some dead code.
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llvm-svn: 78219
2009-08-05 18:12:37 +00:00
9ede773c4e
Remove a redundant declaration.
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llvm-svn: 78216
2009-08-05 17:39:44 +00:00
21788bef7c
Disable NEON single-precision FP support for Cortex-A8, for now...
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llvm-svn: 78209
2009-08-05 16:40:57 +00:00
44c4417812
Remove dead code. MDNode and MDString are not Constant anymore.
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llvm-svn: 78207
2009-08-05 16:40:02 +00:00
a307edbdd5
By default, for cortex-a8 use NEON for single-precision FP.
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llvm-svn: 78200
2009-08-05 16:01:19 +00:00
e219be7346
80 col violations.
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llvm-svn: 78175
2009-08-05 06:41:25 +00:00
85f60cc5a8
Oops. I didn't mean to commit this piece yet.
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llvm-svn: 78146
2009-08-05 02:47:13 +00:00
f9bbcd1afd
Major calling convention code refactoring.
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Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 01:29:28 +00:00
c6b5e8a5c5
Don't flush the raw_ostream between each MachineFunction. These flush
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calls were originally put in place because errs() at one time was
not unbuffered, and these print routines are commonly used with errs()
for debugging. However, errs() is now properly unbuffered, so the
flush calls are no longer needed. This significantly reduces the
number of write(2) calls for regular asm printing when there are many
small functions.
llvm-svn: 78137
2009-08-05 00:49:25 +00:00
20f79e321e
Change DAG nodes for Neon VLD2/3/4 operations to return multiple results.
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Get rid of yesterday's code to fix the register usage during isel.
Select the new DAG nodes to machine instructions. The new pre-alloc pass
to choose adjacent registers for these results is not done, so the
results of this will generally not assemble yet.
llvm-svn: 78136
2009-08-05 00:49:09 +00:00
7cc6aca1e6
Fix part 1 of pr4682. PICADD is a 16-bit instruction even in thumb2 mode.
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llvm-svn: 78126
2009-08-04 23:47:55 +00:00
a8720101b5
Replace dregsingle operand modifier with explicit escaped curly brackets.
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For other VLDn and VSTn operations, we need to list the multiple registers
explicitly anyway, so there's no point in special-casing this one usage.
llvm-svn: 78109
2009-08-04 21:39:33 +00:00
783b65b546
Enable load / store multiple pass for Thumb2. It's not using ldrd / strd yet.
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llvm-svn: 78104
2009-08-04 21:12:13 +00:00
30bf625ac2
Add NEON single-precision FP support for fabs and fneg.
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llvm-svn: 78101
2009-08-04 20:39:05 +00:00
a3abe2a7ce
In thumb mode, r7 is used as frame register. This fixes pr4681.
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llvm-svn: 78086
2009-08-04 18:46:17 +00:00
a3839bc6c0
Match common pattern for FNMAC. Add NEON SP support.
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llvm-svn: 78085
2009-08-04 18:44:29 +00:00
3b9c52c5c1
Initial support for single-precision FP using NEON. Added "neonfp" attribute to enable. Added patterns for some binary FP operations.
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llvm-svn: 78081
2009-08-04 17:53:06 +00:00
d0a53d380a
Ooops, I was too fast to commit the wrong fix :(
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llvm-svn: 78060
2009-08-04 11:18:31 +00:00
3c5b68e2a7
Fix a typo - this unbreaks llvm-gcc build on arm
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llvm-svn: 78059
2009-08-04 11:12:51 +00:00
3870fbb561
Thumb2 does not have ib (increment before) and da (decrement after) forms of ldm / stm.
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llvm-svn: 78057
2009-08-04 08:34:18 +00:00
f43cf709cb
Remove ARM specific getInlineAsmLength. We'll rely on the simpler (and faster) generic algorithm for now. If more accurate computation is needed, we'll rely on the disassembler.
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llvm-svn: 78032
2009-08-04 01:56:09 +00:00
71756e789b
Load / store multiple pass fixes for Thumb2. Not enabled yet.
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llvm-svn: 78031
2009-08-04 01:43:45 +00:00
03eb0e3c33
Emit sub r, #c instead of transforming it to add r, #-c if c fits in 8-bit. This is a bit of pre-mature optimization. 8-bit variant makes it likely it will be narrowed to a 16-bit instruction.
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llvm-svn: 78030
2009-08-04 01:41:15 +00:00
f45dee3ad2
Lower Neon VLD* intrinsics to custom DAG nodes, and manually allocate the
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results to fixed registers.
llvm-svn: 78025
2009-08-04 00:36:16 +00:00
17f8878114
Minor cleanup. No functional changes intended.
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llvm-svn: 78024
2009-08-04 00:25:01 +00:00
09441faba9
use TLOF to compute the section for a function instead of
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replicating the logic manually.
llvm-svn: 78011
2009-08-03 22:32:50 +00:00
Anton Korobeynikov