b98755472e
Print out the connected components in the verifier after complaining about their
...
multiplicity.
llvm-svn: 117630
2010-10-29 00:40:57 +00:00
a2578fe7f3
Run a verification pass before any splitting to better distribute blame.
...
llvm-svn: 117629
2010-10-29 00:40:55 +00:00
5d6f6a061b
add simple support for addrmode5 operands, allowing
...
vldr.64 to work. I have no idea if this is fully right, but
it is in the right direction.
llvm-svn: 117626
2010-10-29 00:27:31 +00:00
6e0d58968d
Ignore empty blocks.
...
llvm-svn: 117615
2010-10-28 22:11:59 +00:00
d27b05e54a
give better error diagnostics, for example:
...
t.s:1:14: error: invalid operand for instruction
vldr.64 d17, [r0]
^
instead of:
t.s:1:1: error: unrecognized instruction
vldr.64 d17, [r0]
^
llvm-svn: 117611
2010-10-28 21:41:58 +00:00
f20f79808e
hook up getOpcodeName for ARM so that "llc -show-mc-inst" includes
...
the opcode string in the inst dump, e.g.:
vmov r2, r3, d17 @ encoding: [0x31,0x2b,0x53,0xec]
@ <MCInst #989 VMOVRRD
@ <MCOperand Reg:68>
@ <MCOperand Reg:69>
@ <MCOperand Reg:19>
@ <MCOperand Imm:14>
@ <MCOperand Reg:0>>
The "VMOVRRD" is new.
llvm-svn: 117609
2010-10-28 21:37:33 +00:00
8aefb66376
Improvements to .section parsing:
...
* If we have a M or a G, reject sections without the type
* Only parse the flag specific arguments if we have M or G
* Parse the corresponding arguments for M and G
We ignore the G arguments and flag for now.
llvm-svn: 117608
2010-10-28 21:33:33 +00:00
9487de6160
move a method out of line.
...
llvm-svn: 117605
2010-10-28 21:28:01 +00:00
9f9f4ebf0c
remove the rest of hte owningptr's, no functionality change.
...
llvm-svn: 117603
2010-10-28 20:52:15 +00:00
dc5e7065a4
One day, physical register live ranges will be sensible.
...
llvm-svn: 117602
2010-10-28 20:44:22 +00:00
c9f90c2a32
Replace SplitKit SSA update with an iterative algorithm very similar to the one
...
in SSAUpdaterImpl.h
Verifying live intervals revealed that the old method was completely wrong, and
we need an iterative approach to calculating PHI placemant. Fortunately, we have
MachineDominators available, so we don't have to compute that over and over
like SSAUpdaterImpl.h must.
Live-out values are cached between calls to mapValue() and computed in a greedy
way, so most calls will be working with very small block sets.
Thanks to Bob for explaining how this should work.
llvm-svn: 117599
2010-10-28 20:34:52 +00:00
e172a8b794
Make MachineDominators available for SplitEditor. We are going to need it for
...
proper SSA updating.
This doesn't cause MachineDominators to be recomputed since we are already
requiring MachineLoopInfo which uses dominators as well.
llvm-svn: 117598
2010-10-28 20:34:50 +00:00
1005cf323d
Add a temporary command line option to verify machine code after each spill or
...
split.
llvm-svn: 117597
2010-10-28 20:34:47 +00:00
47215f4e04
Revert r117582, which reverted r77396. Searching PATH for a string
...
which contains slashes is inconsistent with the meaning of PATH on
Unix-type platforms, and pretty surprising.
If the user has given a specific path to execute and we can't
execute it, we should fail and say why. (Apparently the new
posix_spawn code doesn't always say why, but that's a separate
issue.)
llvm-svn: 117596
2010-10-28 20:34:33 +00:00
63760ba38e
Add support for the .string directive.
...
llvm-svn: 117592
2010-10-28 20:02:27 +00:00
1c75865037
Do not work too hard to find type's file info. There is a special field to record file info.
...
llvm-svn: 117588
2010-10-28 19:50:08 +00:00
3c5a54e4b9
Defined weak symbols should have non-zero value.
...
llvm-svn: 117585
2010-10-28 19:39:57 +00:00
4b94986562
llvmc: Make ExecuteProgram() look in the driver directory first.
...
llvm-svn: 117584
2010-10-28 19:33:08 +00:00
fdba1308ee
Remove an unnecessary check and an unnecessary temporary.
...
llvm-svn: 117583
2010-10-28 19:33:04 +00:00
d7faab5c95
Revert r77396.
...
Original commit message:
On "Unix", if Program::FindProgramByName is given a name containing
slashes, just go with it, regardless of whether it looks like it will
be executable. This follows the behavior of sh(1) more closely.
It's better when behaviour is consistent between platforms. This change also
makes FindExecutable() behave as expected on unix-likes (before this commit, it
used to always succeed).
llvm-svn: 117582
2010-10-28 19:32:58 +00:00
0e9d9b51eb
Trailing whitespace.
...
llvm-svn: 117581
2010-10-28 19:32:53 +00:00
29f70afbae
Fix relocations with renamed symbols.
...
llvm-svn: 117575
2010-10-28 19:08:03 +00:00
851a994a42
Reduce malloc thrashing.
...
llvm-svn: 117572
2010-10-28 18:41:23 +00:00
505607e4c6
PLD, PLDW, PLI encodings, plus refactor their use of addrmode2.
...
llvm-svn: 117571
2010-10-28 18:34:10 +00:00
6cd76e63f8
Aliases defined with .symver should copy the binding of the symbols they alias.
...
Move the existing patching for undefined symbols so that all the patching
is done in the same function.
llvm-svn: 117570
2010-10-28 18:33:03 +00:00
c4b69051b7
Technically DIFile scope should also be handled here.
...
llvm-svn: 117563
2010-10-28 17:30:52 +00:00
b24ba7be49
rearrange ParseRegisterList.
...
llvm-svn: 117560
2010-10-28 17:23:41 +00:00
bd7c9fa36b
refactor some code to simplify it, eliminating some owningptr's.
...
llvm-svn: 117559
2010-10-28 17:20:03 +00:00
f63da12be9
Teach the DAG combiner to fold a splat of a splat. Radar 8597790.
...
Also do some minor refactoring to reduce indentation.
llvm-svn: 117558
2010-10-28 17:06:14 +00:00
41e6cebb40
Use the IDVal directly as there's no need to convert to std::string.
...
Pointed out by Chris!
llvm-svn: 117557
2010-10-28 16:57:58 +00:00
fdac6365ab
Implement .equ directive as a synonym to .set.
...
llvm-svn: 117553
2010-10-28 16:22:58 +00:00
89d412a140
Fix PR8494: when reading invalid bitcode, getTypeByID may return
...
a null pointer.
llvm-svn: 117551
2010-10-28 15:47:26 +00:00
936ba3af28
Implement R_X86_64_DTPOFF32.
...
llvm-svn: 117548
2010-10-28 15:11:03 +00:00
2dbec3f762
Implement TLSLD.
...
llvm-svn: 117547
2010-10-28 15:02:40 +00:00
e8f08be11c
Implement DTPOFF.
...
llvm-svn: 117546
2010-10-28 14:48:59 +00:00
6f23eb380d
Implement TLSLDM.
...
llvm-svn: 117544
2010-10-28 14:37:09 +00:00
b3b49bbc39
Implement VK_GOTNTPOFF and switch RelocNeedsGOT to use VariantKind.
...
llvm-svn: 117543
2010-10-28 14:22:44 +00:00
080d86fecc
Reindent.
...
llvm-svn: 117538
2010-10-28 08:25:44 +00:00
ff310737e5
Re-commit 117518 and 117519 now that ARM MC test failures are out of the way.
...
llvm-svn: 117531
2010-10-28 06:47:08 +00:00
e2c211c1b9
Revert 117518 and 117519 for now. They changed scheduling and cause MC tests to fail. Ugh.
...
llvm-svn: 117520
2010-10-28 02:00:25 +00:00
ff1c862f8e
- Assign load / store with shifter op address modes the right itinerary classes.
...
- For now, loads of [r, r] addressing mode is the same as the
[r, r lsl/lsr/asr #] variants. ARMBaseInstrInfo::getOperandLatency() should
identify the former case and reduce the output latency by 1.
- Also identify [r, r << 2] case. This special form of shifter addressing mode
is "free".
llvm-svn: 117519
2010-10-28 01:49:06 +00:00
523fa3a2e8
Fix a major bug in operand latency computation. The use index must be adjusted
...
by the number of defs first for it to match the instruction itinerary.
llvm-svn: 117518
2010-10-28 01:46:29 +00:00
9c3f6bf2bf
Fix pastos in handling of AVX cvttsd2si, PR8491.
...
Bruno, please review, but I'm pretty sure this is right.
Patch by Alex Mac!
llvm-svn: 117514
2010-10-28 00:35:54 +00:00
2ef668840a
Add correct NEON encodings for vtbl and vtbx.
...
llvm-svn: 117513
2010-10-28 00:18:46 +00:00
14be930317
Add correct NEON encodings for vext, vtrn, vuzp, and vzip.
...
llvm-svn: 117512
2010-10-27 23:56:39 +00:00
6c55007edb
Fix compiler warnings about signed/unsigned comparisons.
...
llvm-svn: 117511
2010-10-27 23:49:00 +00:00
16bb87a90e
Teach InstCombine not to use Add and Neg on FP. PR 8490.
...
llvm-svn: 117510
2010-10-27 23:45:18 +00:00
59bbc545e0
Shifter ops are not always free. Do not fold them (especially to form
...
complex load / store addressing mode) when they have higher cost and
when they have more than one use.
llvm-svn: 117509
2010-10-27 23:41:30 +00:00
cbdf7e874a
Putting r117193 back except for the compile time cost. Rather than assuming fallthroughs uses all registers, just gather the union of all successor liveins.
...
llvm-svn: 117506
2010-10-27 23:17:17 +00:00
338de3ee56
Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like
...
the LDR instructions have. This makes the literal/register forms of the
instructions explicit and allows us to assign scheduling itineraries
appropriately. rdar://8477752
llvm-svn: 117505
2010-10-27 23:12:14 +00:00
fadb951e5b
Provide correct encodings for NEON vcvt, which has its own special immediate encoding
...
for specifying fractional bits for fixed point conversions.
llvm-svn: 117501
2010-10-27 22:49:00 +00:00
055de2c789
Trailing whitespace
...
llvm-svn: 117496
2010-10-27 21:39:08 +00:00
ed9652f959
Provide correct encodings for the get_lane and set_lane variants of vmov.
...
llvm-svn: 117495
2010-10-27 21:28:09 +00:00
f8537165bd
Add support for R_386_TLS_GD, R_386_TLS_LE_32, R_386_TLS_IE and R_386_TLS_LE.
...
llvm-svn: 117494
2010-10-27 21:23:52 +00:00
5e7cb5fc27
Added the x86 instruction ud2b (2nd official undefined instruction).
...
llvm-svn: 117485
2010-10-27 20:46:49 +00:00
f4ea7084c5
JIT imm12 encoding for constant pool entry references.
...
llvm-svn: 117483
2010-10-27 20:39:40 +00:00
c7334a146e
SelectionDAG shuffle nodes do not allow operands with different numbers of
...
elements than the result vector type. So, when an instruction like:
%8 = shufflevector <2 x float> %4, <2 x float> %7, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
is translated to a DAG, each operand is changed to a concat_vectors node that appends 2 undef elements. That is:
shuffle [a,b], [c,d] is changed to:
shuffle [a,b,u,u], [c,d,u,u]
That's probably the right thing for x86 but for NEON, we'd much rather have:
shuffle [a,b,c,d], undef
Teach the DAG combiner how to do that transformation for ARM. Radar 8597007.
llvm-svn: 117482
2010-10-27 20:38:28 +00:00
24c8b04d5f
Implement R_X86_64_GOTTPOFF, R_X86_64_TLSGD and R_X86_64_TPOFF32.
...
llvm-svn: 117481
2010-10-27 20:28:07 +00:00
333b0a9e74
ARM JIT fix for LDRi12 and company.
...
llvm-svn: 117478
2010-10-27 19:55:59 +00:00
14807270be
Replace pointer arithmetic with StringRef::substr.
...
llvm-svn: 117477
2010-10-27 19:53:52 +00:00
40d24a4abf
Provide correct NEON encodings for vdup.
...
llvm-svn: 117475
2010-10-27 19:25:54 +00:00
7db918f1e9
x86-Win32: Switch ftol2 calling convention from stdcall to C.
...
llvm-svn: 117474
2010-10-27 18:52:38 +00:00
0f83d96852
COFF: Add IMAGE_SCN_MEM_READ to text sections.
...
There are currently 100 references to COFF::IMAGE_SCN in 6 files
and 11 different functions. Section to attribute mapping really
needs to happen in one place to avoid problems like this.
llvm-svn: 117473
2010-10-27 18:52:29 +00:00
fbdab0d633
Fix whitespace.
...
llvm-svn: 117472
2010-10-27 18:52:20 +00:00
095fa9e5cc
Set default type and flags for .init and .fini.
...
llvm-svn: 117471
2010-10-27 18:45:20 +00:00
26496e6835
Produce an error for an invalid use of .symver.
...
llvm-svn: 117462
2010-10-27 17:56:18 +00:00
ba1c6cd62f
The new LDR* instruction patterns should handle the necessary encoding of
...
operands in the TableGen'erated bits, so we don't need to do the additional
magic explicitly.
llvm-svn: 117461
2010-10-27 17:52:51 +00:00
8576a42cf3
Add correct NEON encodings for vsli and vsri.
...
llvm-svn: 117459
2010-10-27 17:40:08 +00:00
d7e8135e1e
Add correct NEON encodings for vsra and vrsra.
...
llvm-svn: 117458
2010-10-27 17:29:29 +00:00
8bf1483a3d
The immediate operands of an LDRi12 instruction doesn't need the addrmode2
...
encoding tricks. Handle the 'imm doesn't fit in the insn' case.
llvm-svn: 117454
2010-10-27 16:50:31 +00:00
e4992c88a4
Formatting.
...
llvm-svn: 117453
2010-10-27 16:30:18 +00:00
cc1b168ef6
Symbols defined as the difference of other two end up in the ABS section.
...
llvm-svn: 117451
2010-10-27 16:04:30 +00:00
eb0c2c170d
Add support for the .symver directive. This is really ugly, but most of it is
...
contained in the ELF object writer.
llvm-svn: 117448
2010-10-27 15:18:17 +00:00
a5efd6a27c
Move more logic to isInSymtab and simplify.
...
llvm-svn: 117447
2010-10-27 14:44:52 +00:00
258b8e1dc8
80-col violation.
...
llvm-svn: 117443
2010-10-27 09:09:10 +00:00
32acd741d2
Remove try/catch(...) from Win32/Signals.inc.
...
catch(...) is used in Win32/Signals.inc for catching Win32 structured
exceptions, but according to [1], this is wrong.
We can't simply change try/catch to __try/__finally, since this syntax is not
supported by MinGW. We can use __try/__finally on MSVC and __try1/__except1
macros on MinGW [2], but I think that that solution obfuscates the code too
much.
The use of try/catch(...) in Signals.inc makes it impossible to link
MinGW-compiled libSystem with llvm-gcc compiled executables. I propose that we
just remove try/catch(...) from Signals.inc, since the meaning of the code won't
change.
[1] http://members.cox.net/doug_web/eh.htm
[2] http://article.gmane.org/gmane.comp.compilers.llvm.cvs/81315
llvm-svn: 117442
2010-10-27 09:09:04 +00:00
9ad2166899
Yet another tweak to X86 instructions to add ud2a as an alias to ud2
...
(still to add ud2b).
llvm-svn: 117435
2010-10-27 03:01:02 +00:00
20b021c970
Another tweak to X86 instructions to add the missing flex instruction (without
...
the wait prefix).
llvm-svn: 117434
2010-10-27 02:53:04 +00:00
a1917c7555
Tweaks to X86 instructions to allow the 'w' suffix in places it makes
...
sense, when the instruction takes the 16-bit ax register or m16 memory
location. These changes to llvm-mc matches what the darwin assembler
allows for these instructions. Done differently than in r117031 that
caused a valgrind error which was later reverted.
llvm-svn: 117433
2010-10-27 02:32:19 +00:00
9d2d1f0f00
LDRi12 machine instructions handle negative offset operands normally (simple
...
integer values), not with the addrmode2 encoding.
llvm-svn: 117429
2010-10-27 01:19:41 +00:00
ba985d9dd5
Added some aliases to the fcomip and fucompi Intel instructions. So that llvm-mc
...
will accept versions that the darwin assembler allows. Forms ending in "pi" and
forms without all the operands.
llvm-svn: 117427
2010-10-27 00:59:28 +00:00
79e1407c11
Handle critical loop predecessors by making both inside and outside registers
...
live out.
This doesn't prevent us from inserting a loop preheader later on, if that is
better.
llvm-svn: 117424
2010-10-27 00:39:07 +00:00
795ed98180
Compute critical loop predecessors in the same way as critical loop exits.
...
Critical edges going into a loop are not as bad as critical exits. We can handle
them by splitting the critical edge, or by having both inside and outside
registers live out of the predecessor.
llvm-svn: 117423
2010-10-27 00:39:05 +00:00
0e7a011a00
Physical registers trivially have multiple connected components all the time.
...
Only virtuals should be requires to be connected.
llvm-svn: 117422
2010-10-27 00:39:01 +00:00
2577b2e8b1
One more spot where the new arm mode LDR instruction representation
...
doesn't need the additional addrmode2 register operand. Missed it the first
time around.
llvm-svn: 117421
2010-10-27 00:38:16 +00:00
e9b429e96f
Adding disassembler to the MicroBlaze backend.
...
llvm-svn: 117420
2010-10-27 00:23:01 +00:00
5a7c715470
Split ARM::LDRB into LDRBi12 and LDRBrs. Adjust accordingly. Continuing on
...
rdar://8477752.
llvm-svn: 117419
2010-10-27 00:19:44 +00:00
a92801b695
Since I parameterized this bit, I should probably actually use said parameter.
...
llvm-svn: 117418
2010-10-26 23:58:04 +00:00
e660f4d072
Use a MemIntrinsicSDNode for ISD::PREFETCH, which touches
...
memory, so a MachineMemOperand is useful (not propagated
into the MachineInstr yet). No functional change except
for dump output.
llvm-svn: 117413
2010-10-26 23:11:10 +00:00
5f88cc34e1
Remove the vector of live vregs. I thought we would need to track
...
them, but hopefully we won't. And this is not the right data structure
to do it anyway.
llvm-svn: 117412
2010-10-26 22:58:24 +00:00
825b2d1946
Add correct NEON encodings for vqshl, vqshrn, vqshrun, vqrshl, vqshrn, and vqrshrun.
...
llvm-svn: 117411
2010-10-26 22:50:46 +00:00
1e4d9a17c2
First part of refactoring ARM addrmode2 (load/store) instructions to be more
...
explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.
llvm-svn: 117409
2010-10-26 22:37:02 +00:00
e4f3317cda
After splitting, compute connected components of all new registers, not just for
...
the remainder register.
Example:
bb0:
x = 1
bb1:
use(x)
...
x = 2
jump bb1
When x is isolated in bb1, the inner part breaks into two components, x1 and x2:
bb0:
x0 = 1
bb1:
x1 = x0
use(x1)
...
x2 = 2
x0 = x2
jump bb1
llvm-svn: 117408
2010-10-26 22:36:09 +00:00
260fa289df
Verify that live intervals are connected. If there are multiple connected
...
components, each should get its own virtual register.
llvm-svn: 117407
2010-10-26 22:36:07 +00:00
022e7795cf
Call RenumberValues for all new registers created during splitting. This is
...
necessary to get correct hasPHIKill flags.
llvm-svn: 117406
2010-10-26 22:36:05 +00:00
4453324e5b
Preserve PHIDef bits in cloned values during splitting.
...
llvm-svn: 117405
2010-10-26 22:36:02 +00:00
05561e8b7b
Assign source ordering to nodes created for StoreInst.
...
llvm-svn: 117404
2010-10-26 22:14:52 +00:00
2888e2c7f9
Correct NEON encodings for vshrn, vrshl, vrshr, vrshrn.
...
llvm-svn: 117402
2010-10-26 21:58:41 +00:00
e18579976f
Simplify classes for shift instructions, which are never commutable.
...
llvm-svn: 117398
2010-10-26 21:13:59 +00:00
3665fee8de
Provide correct NEON encodings for vshl, register and immediate forms.
...
llvm-svn: 117394
2010-10-26 20:56:57 +00:00
b7050233fb
Teach MachineBasicBlock::print() to annotate instructions and blocks with
...
SlotIndexes when available.
llvm-svn: 117392
2010-10-26 20:21:46 +00:00
db594373bd
Remmeber to print full live interval on verification error.
...
llvm-svn: 117391
2010-10-26 20:21:43 +00:00
c9fb35e73b
Add support for .ident.
...
llvm-svn: 117389
2010-10-26 19:35:47 +00:00
9302bfdd5a
Grammar.
...
llvm-svn: 117388
2010-10-26 19:34:41 +00:00
79b3bf4d81
Nuke extraneous comment. It's applicable elsewhere, but not in this func.
...
llvm-svn: 117387
2010-10-26 19:22:23 +00:00
84aef49e32
Jakob's review of the basic register allocator.
...
llvm-svn: 117384
2010-10-26 18:34:01 +00:00
691ce68d3c
Add correct NEON encoding for vpadal.
...
llvm-svn: 117380
2010-10-26 18:18:03 +00:00
d94f3b4ae9
handle X86::EH_RETURN64 and X86::EH_RETURN.
...
llvm-svn: 117378
2010-10-26 18:09:55 +00:00
b5694e702c
s/beginScope/beginInstruction/g
...
s/endScope/endInstruction/g
llvm-svn: 117376
2010-10-26 17:49:02 +00:00
284cb361d1
Add NEON encodings for vmov and vmvn of immediates.
...
llvm-svn: 117374
2010-10-26 17:40:54 +00:00
9eabfa3a39
Don't verify physical registers going into landing pads.
...
Magic is happening that we don't understand.
llvm-svn: 117370
2010-10-26 16:49:23 +00:00
e8ae98817a
Implement some relaxations for arithmetic instructions. The limitation
...
on RIP relative relocations looks artificial, but this is a superset of
what we were able to do before.
llvm-svn: 117364
2010-10-26 14:09:12 +00:00
a49d062234
Change v64 datalayout in SPU.
...
The SPU ABI does not mention v64, and all examples
in C suggest v128 are treated similarily to arrays,
we use array alignment for v64 too. This makes the
alignment of e.g. [2 x <2 x i32>] behave "intuitively"
and similar to as if the elements were e.g. i32s.
This also makes an "unaligned store" test to be
aligned, with different (but functionally equivalent)
code generated.
llvm-svn: 117360
2010-10-26 10:45:47 +00:00
e96b8d7ab6
Use instruction itinerary to determine what instructions are 'cheap'.
...
llvm-svn: 117348
2010-10-26 02:08:50 +00:00
b45591979b
NEON vmov's are in Neon domain.
...
llvm-svn: 117347
2010-10-26 02:03:05 +00:00
90b2ac2696
For statistics that are only used in functions declared in !NDEBUG, wrap the
...
declarations in !NDEBUG to avoid -Wunused-variable warnings. Patch by
Matt Beaumont-Gay!
llvm-svn: 117345
2010-10-26 00:51:57 +00:00
e2c340c8d0
InlineSpiller can also update LiveStacks.
...
llvm-svn: 117338
2010-10-26 00:11:35 +00:00
7cdc1e5f16
Make the spiller responsible for updating the LiveStacks analysis.
...
llvm-svn: 117337
2010-10-26 00:11:33 +00:00
e1961fe289
When the "true" and "false" blocks of a diamond if-conversion are the same,
...
do not double-count the duplicate instructions by counting once from the
beginning and again from the end. Keep track of where the duplicates from
the beginning ended and don't go past that point when counting duplicates
at the end. Radar 8589805.
This change causes one of the MC/ARM/simple-fp-encoding tests to produce
different (better!) code without the vmovne instruction being tested.
I changed the test to produce vmovne and vmoveq instructions but moving
between register files in the opposite direction. That's not quite the same
but predicated versions of those instructions weren't being tested before,
so at least the test coverage is not any worse, just different.
llvm-svn: 117333
2010-10-26 00:02:24 +00:00
efd360c535
Change if-conversion to keep track of the extra cost due to microcoded
...
instructions separately from the count of non-predicated instructions. The
instruction count is used in places to determine how many instructions to
copy, predicate, etc. and things get confused if that count includes the
extra cost for microcoded ops.
llvm-svn: 117332
2010-10-26 00:02:21 +00:00
59f7cdaf98
Tidy up redundant check.
...
llvm-svn: 117331
2010-10-26 00:02:19 +00:00
43d6f34e9f
Neuter r117193 as it causes significant post-ra scheduler compile time regression.
...
llvm-svn: 117329
2010-10-25 23:56:21 +00:00
d9d0c348df
Produce the headers directly in the Finish method. This allows us to use
...
the existing streamer methods that are endian safe.
llvm-svn: 117323
2010-10-25 22:26:55 +00:00
ec57ac1c3c
An stdcall function calling a non-stdcall function
...
cannot use tailcall. PR 8461.
llvm-svn: 117322
2010-10-25 22:17:05 +00:00
c6096263e2
Support TBAA attachments on calls. This is somewhat experimental.
...
llvm-svn: 117317
2010-10-25 21:38:20 +00:00
43c3f4b63c
Simplify.
...
Do not count use of sdisel for single call instruction.
llvm-svn: 117316
2010-10-25 21:31:46 +00:00
1f6aad053d
Add correct encodings for NEON vabal.
...
llvm-svn: 117315
2010-10-25 21:29:04 +00:00
82b2e0da9c
Fix chaining in TBAA's pointsToConstantMemory.
...
llvm-svn: 117314
2010-10-25 21:24:55 +00:00
3bc6d198fb
Add counters to count basic blocks and machine basic blocks with out of order line number info.
...
Add counters to count how many basic blocks are entirely selected by fastisel.
llvm-svn: 117310
2010-10-25 20:55:43 +00:00
b9c91679aa
Add correct NEON encodings for vaba.
...
llvm-svn: 117309
2010-10-25 20:52:57 +00:00
a86114b961
Add simple counter to count no. of basic blocks without any line number information. At -O0, these basic block coule cause less than optimial debugging experience.
...
llvm-svn: 117307
2010-10-25 20:45:32 +00:00
e6715d0755
Only read one bit for testing for a readonly type, leaving the other
...
bits open for future uses.
llvm-svn: 117301
2010-10-25 20:22:29 +00:00
b3a48f3459
MC/AsmParser: Fix relative precedence of {+,-} and comparison ops.
...
llvm-svn: 117299
2010-10-25 20:18:56 +00:00
7484d2cbec
MC/AsmLexer: Fix bug in source location for Slash token.
...
llvm-svn: 117298
2010-10-25 20:18:53 +00:00
dd001b89d7
Attempt to provide correct encodings for NEON vbit and vbif, even though we can't test them at the moment.
...
llvm-svn: 117294
2010-10-25 20:17:22 +00:00
dea09c7564
Provide correct NEON encodings for vbsl.
...
llvm-svn: 117293
2010-10-25 20:13:13 +00:00
e6fe1a03c7
imm12 operands aren't Thumb2 only, so rename the printer helper function.
...
llvm-svn: 117291
2010-10-25 20:00:01 +00:00
fd864a1d31
Add a comment.
...
llvm-svn: 117288
2010-10-25 19:47:25 +00:00
2477446ee5
Add correct instruction encodings for vbic, vorn, and vmvn.
...
llvm-svn: 117282
2010-10-25 18:43:52 +00:00
752913d6ba
Add a virtual destructor.
...
llvm-svn: 117280
2010-10-25 18:38:32 +00:00
dff239c5f9
Provide correct NEON encodings for vand, veor, and vorr.
...
llvm-svn: 117279
2010-10-25 18:28:30 +00:00
feb3ee0c93
Add NEON encoding tests for vcgt and vacgt.
...
llvm-svn: 117276
2010-10-25 18:03:59 +00:00
0ed1543d4e
Add support for emitting ARM file attributes.
...
llvm-svn: 117275
2010-10-25 17:50:35 +00:00
e5d0677173
Add tests for NEON encodings of vcge and vacge.
...
llvm-svn: 117274
2010-10-25 17:49:32 +00:00
c178b80f65
Add a warning about our inability to test the encoding of vceq with immediate zero.
...
llvm-svn: 117273
2010-10-25 17:33:02 +00:00
912db6d9d0
In which I learn how to forward declare template classes.
...
llvm-svn: 117272
2010-10-25 17:27:30 +00:00
abaf2d8d3b
Update comments; BasicAA is no longer necessarily the end of the chain.
...
llvm-svn: 117268
2010-10-25 16:29:52 +00:00
1033ce669b
Reintroduce these asserts, now that BasicAA is a normal AliasAnalysis pass.
...
llvm-svn: 117266
2010-10-25 16:28:57 +00:00
2e20dfb0f2
Fix a case where instcombine was stripping metadata (and alignment)
...
from stores when folding in bitcasts.
llvm-svn: 117265
2010-10-25 16:16:27 +00:00
22fe18625d
Add a new 'hotpatch' attribute. This attribute will insert a two-byte no-op
...
instruction at the beginning of each function that has the attribute, allowing
the function to be easily hooked and/or patched.
llvm-svn: 117264
2010-10-25 15:37:09 +00:00
Jakob Stoklund Olesen