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42737 Commits

Author SHA1 Message Date
Jim Grosbach fddf36d254 Add 'IsThumb' predicate to patterns marked as 'IsThumb1Only'. The latter gates 
codegen using the patterns; the latter gates the assembler recognizing the
instruction.

llvm-svn: 117931
 2010-11-01 17:08:58 +00:00
Rafael Espindola 13ddd6d410 Write the line info to .debug_line. 
llvm-svn: 117930
 2010-11-01 17:07:14 +00:00
Jim Grosbach 0190a649e8 Mark ARM subtarget features that are available for the assembler. 
llvm-svn: 117929
 2010-11-01 16:59:54 +00:00
Jim Grosbach 99710a871c trailing whitespace 
llvm-svn: 117927
 2010-11-01 16:44:21 +00:00
Rafael Espindola 72b5488680 Move EmitInstruction to MCObjectStreamer so that ELF and MachO can share it. 
llvm-svn: 117925
 2010-11-01 16:27:31 +00:00
Jim Grosbach 5b373341fc The T2 extract/pack instructions are only valid in Thumb2 mode. Mark the 
patterns as such

llvm-svn: 117923
 2010-11-01 15:59:52 +00:00
Rafael Espindola 144fb8af58 Add support for .value. 
llvm-svn: 117922
 2010-11-01 15:29:07 +00:00
Rafael Espindola 1614597873 Implement .weakref. 
llvm-svn: 117911
 2010-11-01 14:28:48 +00:00
Bill Wendling 2623343625 Move instruction encoding bits into the parent class and remove the temporary 
*_Encode classes. These instructions are the only ones which use those classes,
so a subclass isn't necessary.

llvm-svn: 117906
 2010-11-01 06:00:39 +00:00
Bill Wendling 7a23c1fb7d The testcase is now XFAILed. Sorry about the breakage. 
llvm-svn: 117904
 2010-11-01 05:50:55 +00:00
Chris Lattner 1acd6b1edc "mov[zs]x (mem), GR16" are not ambiguous: the mem 
must be 8 bits.  Support this memory form.

llvm-svn: 117902
 2010-11-01 05:41:10 +00:00
Chris Lattner dd3b09c234 Implement enough of the missing instalias support to get 
aliases installed and working.  They now work when the
matched pattern and the result instruction have exactly
the same operand list.

This is now enough for us to define proper aliases for
movzx and movsx, implementing rdar://8017633 and PR7459.

Note that we do not accept instructions like:
  movzx 0(%rsp), %rsi

GAS accepts this instruction, but it doesn't make any
sense because we don't know the size of the memory
operand.  It could be 8/16/32 bits.

llvm-svn: 117901
 2010-11-01 05:34:34 +00:00
Chris Lattner 178f4bb62d make the asm matcher emitter reject instructions that have comments 
in their asmstring.  Fix the two x86 "NOREX" instructions that have them.
If these comments are important, the instlowering stuff can print them.

llvm-svn: 117897
 2010-11-01 04:44:29 +00:00
Chris Lattner 941c19b7ba reject instructions that contain a \n in their asmstring. Mark 
various X86 and ARM instructions that are bitten by this as isCodeGenOnly,
as they are.

llvm-svn: 117884
 2010-11-01 00:46:16 +00:00
Eric Christopher ef5a1c3ec3 Revert r117876 for now, it's causing more testsuite failures. 
llvm-svn: 117879
 2010-10-31 22:42:55 +00:00
Bill Wendling 0392f1b437 Disable the peephole optimizer until 186.crafty on armv6 is fixed. This is what 
looks like is happening:

Without the peephole optimizer:
  (1)   sub     r6, r6, #32
        orr     r12, r12, lr, lsl r9
        orr     r2, r2, r3, lsl r10
  (x)   cmp     r6, #0
        ldr     r9, LCPI2_10
        ldr     r10, LCPI2_11
  (2)   sub     r8, r8, #32
  (a)   movge   r12, lr, lsr r6
  (y)   cmp     r8, #0
LPC2_10:
        ldr     lr, [pc, r10]
  (b)   movge   r2, r3, lsr r8

With the peephole optimizer:
        ldr     r9, LCPI2_10
        ldr     r10, LCPI2_11
  (1*)  subs    r6, r6, #32
  (2*)  subs    r8, r8, #32
  (a*)  movge   r12, lr, lsr r6
  (b*)  movge   r2, r3, lsr r8

(1) is used by (x) for the conditional move at (a). (2) is used by (y) for the
conditional move at (b). After the peephole optimizer, these the flags resulting
from (1*) are ignored and only the flags from (2*) are considered for both
conditional moves.

llvm-svn: 117876
 2010-10-31 22:07:12 +00:00
Nicolas Geoffray 3dbe6cc155 Attach a GCModuleInfo to a MachineFunction. 
llvm-svn: 117867
 2010-10-31 20:38:38 +00:00
Chris Lattner 7ff334687d fix the !eq operator in tblgen to return a bit instead of an int. 
Use this to make the X86 and ARM targets set isCodeGenOnly=1 
automatically for their instructions that have Format=Pseudo,
resolving a hack in tblgen.

llvm-svn: 117862
 2010-10-31 19:22:57 +00:00
Chris Lattner 9492c17baf two changes: make the asmmatcher generator ignore ARM pseudos properly, 
and make it a hard error for instructions to not have an asm string.
These instructions should be marked isCodeGenOnly.

llvm-svn: 117861
 2010-10-31 19:15:18 +00:00
Chris Lattner 33fc3e095b reapply r117858 with apparent editor malfunction fixed (somehow I 
got a dulicated line).

llvm-svn: 117860
 2010-10-31 19:10:56 +00:00
Chris Lattner e59eef3dd1 revert r117858 while I check out a failure I missed. 
llvm-svn: 117859
 2010-10-31 19:05:32 +00:00
Chris Lattner 9293008e90 the asm matcher can't handle operands with modifiers (like ${foo:bar}). 
Instead of silently ignoring these instructions, emit a hard error and
force the target author to either refactor the target or mark the 
instruction 'isCodeGenOnly'.

Mark a few instructions in ARM and MBlaze as isCodeGenOnly the are 
doing this.

llvm-svn: 117858
 2010-10-31 18:48:12 +00:00
Chris Lattner eb8c0fc2eb sketch out the planned instruction alias mechanism, add some comments about 
how the push/pop mnemonic aliases are wrong.

llvm-svn: 117857
 2010-10-31 18:43:46 +00:00
Duncan Sands fb0a48ef96 Factorize the duplicated logic for choosing the right argument 
calling convention out of the fast and normal ISel files, and
into the calling convention TD file.

llvm-svn: 117856
 2010-10-31 13:21:44 +00:00
Duncan Sands fa7e6f2417 Remove CCAssignFnForRet from X86 FastISel in favour of RetCC_X86, 
which has the same logic specified in the CallingConv TD file.
This brings FastISel in line with the standard X86 ISel.

llvm-svn: 117855
 2010-10-31 13:02:38 +00:00
Rafael Espindola 3fe87a1eed Add support for files with more than 65280 sections. No testcase since 
it would be a bit too big :-)

llvm-svn: 117849
 2010-10-31 00:16:26 +00:00
Eric Christopher 04b0a3e651 Make sure we have a legal type (and simple) before continuing. 
llvm-svn: 117848
 2010-10-30 21:25:26 +00:00
Chris Lattner aac142cc06 Resolve a terrible hack in tblgen: instead of hardcoding 
"In32BitMode" and "In64BitMode" into tblgen, allow any
predicate that inherits from AssemblerPredicate.

llvm-svn: 117831
 2010-10-30 19:38:20 +00:00
Chris Lattner 2cb092dc55 Implement (and document!) support for MnemonicAlias's to have Requires 
directives, allowing things like this:

def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>;
def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>;

Move the rest of the X86 MnemonicAliases over to the .td file.

llvm-svn: 117830
 2010-10-30 19:23:13 +00:00
Chris Lattner 57bfc66d60 really zap alias. 
llvm-svn: 117824
 2010-10-30 18:23:25 +00:00
Chris Lattner 462bc666d2 move fcompi alias to .td file and zap some useless code. 
llvm-svn: 117823
 2010-10-30 18:22:53 +00:00
Chris Lattner daae9eea8a move rep aliases to td file 
llvm-svn: 117822
 2010-10-30 18:17:33 +00:00
Chris Lattner fa40aee871 move sal aliases to .td file. 
llvm-svn: 117821
 2010-10-30 18:14:54 +00:00
Chris Lattner 4d9f157203 fix an encoding mismatch where "sal %eax, 1" was not using the short encoding 
for shl.  Caught by inspection.

llvm-svn: 117820
 2010-10-30 18:13:10 +00:00
Chris Lattner 069132311a move a bunch more aliases from .cpp -> .td file. 
llvm-svn: 117819
 2010-10-30 18:07:17 +00:00
Chris Lattner b4a1674421 move cmov aliases to .td file. 
llvm-svn: 117818
 2010-10-30 17:56:50 +00:00
Chris Lattner f04cbe6291 move setcc and jcc aliases from .cpp to .td 
llvm-svn: 117817
 2010-10-30 17:51:45 +00:00
Chris Lattner 72c0b59e81 move some code. 
llvm-svn: 117816
 2010-10-30 17:38:55 +00:00
Chris Lattner ba7b4fea97 implement (and document!) the first kind of MC assembler alias, which 
just remaps one mnemonic to another.  Convert a few of the X86 aliases
from .cpp to .td code.

llvm-svn: 117815
 2010-10-30 17:36:36 +00:00
Duncan Sands e659aba516 Now that the MallocInst no longer exists, this workaround for 
it claiming not to have side-effects is no longer needed.

llvm-svn: 117789
 2010-10-30 16:12:16 +00:00
Jim Grosbach bbe2bbd7f7 Add FIXME. 
llvm-svn: 117787
 2010-10-30 14:54:23 +00:00
Jim Grosbach 4cf25f5ba9 Clean up comments. 
llvm-svn: 117785
 2010-10-30 13:48:28 +00:00
Duncan Sands b8f3b14dfb If a function does a volatile load from a global constant, do not 
consider it to be readonly.  In fact, don't even consider it to be
readonly if it does a volatile load from an AllocaInst either (it
is debatable as to whether readonly would be correct or not in this
case; play safe for the moment).  This fixes PR8279.

llvm-svn: 117783
 2010-10-30 12:59:44 +00:00
Jim Grosbach a71c9e2ebf Tidy up. 
llvm-svn: 117782
 2010-10-30 12:59:16 +00:00
Chris Lattner de30afc3d9 stay out of the reserved namespace 
llvm-svn: 117773
 2010-10-30 04:57:14 +00:00
Chris Lattner 549a31cd34 simplify this code. 
llvm-svn: 117771
 2010-10-30 04:35:59 +00:00
Chris Lattner 44e5981c1b split MaybeParseRegister into its two logical uses, eliminating malloc+free traffic. 
llvm-svn: 117769
 2010-10-30 04:09:10 +00:00
Jim Grosbach 7b275105d6 Avoid re-evaluating MI.getNumOperands() every iteration of the loop. 
llvm-svn: 117766
 2010-10-30 01:40:16 +00:00
Jakob Stoklund Olesen 80717dd7c6 Include MachineBasicBlock numbers in viewCFG() output. 
llvm-svn: 117765
 2010-10-30 01:26:19 +00:00
Jakob Stoklund Olesen 0cfc497f19 Make sure copies are inserted after any exception handling labels at the top of 
a basic block.

llvm-svn: 117764
 2010-10-30 01:26:16 +00:00