04cbcca319
Add sizes non-floating point versions for the eh sjlj intrinsic expansions.
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rdar://7895451
llvm-svn: 102526
2010-04-28 20:33:09 +00:00
4c18a3ac80
Update tests. Now DBG_VALUE instruction is created only if alloca corresponding to llvm.dbg.declare is missing.
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llvm-svn: 102524
2010-04-28 20:27:48 +00:00
ee3576e8f1
declare targets with (void) instead of () since this is a C header.
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Patch by Lars R in PR6961.
llvm-svn: 102523
2010-04-28 20:24:45 +00:00
450e29cb4c
fix PR6112 - When globalopt (or any other pass) does RAUW(@G, %G),
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metadata references in non-function-local MDNodes should drop to
null.
llvm-svn: 102519
2010-04-28 20:16:12 +00:00
d4d1a51895
Pretty print DBG_VALUE machine instructions.
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Before:
DBG_VALUE %RSI, 0, !-1; dbg:SimpleRegisterCoalescing.cpp:2707
Now:
DBG_VALUE %RSI, 0, !"this"; dbg:SimpleRegisterCoalescing.cpp:2707
llvm-svn: 102518
2010-04-28 20:03:13 +00:00
08e9e72fa9
Rework global alignment computation again. Now we do round up
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alignment of globals to the preferred alignment, but only when
there is no section specified on the global (by far the common
case).
llvm-svn: 102515
2010-04-28 19:58:07 +00:00
888c17073a
While lowering dbg_declare, emit DBG_VALUE machine instruction if alloca matching llvm.dbg.declare intrinsic is missing.
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llvm-svn: 102513
2010-04-28 19:27:33 +00:00
06e7242d32
Recompute kill flags from live intervals after coalescing instead of trying to
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update them. Computing kill flags is notoriously difficult, and the coalescer
would get it wrong sometimes, and it would completely skip physical registers.
Now we simply remove kill flags based on the live intervals after coalescing.
This is a few percent slower, but now we get correct kill flags for physical
registers after coalescing.
llvm-svn: 102510
2010-04-28 18:28:39 +00:00
96fad31694
Teach X86FloatingPoint that a register can be killed multiple times by the same
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instruction.
This instruction would crash the pass:
INLINEASM <es:foo $0 $1>, 9, %FP0<kill>, 9, %FP0<kill>, 14, %EFLAGS<earlyclobber,def,dead>
Now it doesn't.
llvm-svn: 102509
2010-04-28 18:28:37 +00:00
7ebb5e4cb0
Undo most of my previous whitespace fix. I think I like it better this way
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after all.
llvm-svn: 102508
2010-04-28 18:18:36 +00:00
a2dbebc431
Fix inconsistent use of HOSTS and TARGETS variables.
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llvm-svn: 102505
2010-04-28 18:06:27 +00:00
5f1074adde
Fix whitespace.
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llvm-svn: 102504
2010-04-28 17:50:03 +00:00
050df1b8de
Enable i16 to i32 promotion by default.
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llvm-svn: 102493
2010-04-28 08:30:49 +00:00
f100557c9a
Try operation promotion only if regular dag combine and target-specific ones failed to do anything.
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llvm-svn: 102492
2010-04-28 07:10:39 +00:00
d21f564543
Unbreak the build. Only form shld / shrd after legalization.
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llvm-svn: 102488
2010-04-28 02:25:18 +00:00
fe420adde0
Update tests.
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llvm-svn: 102487
2010-04-28 01:53:13 +00:00
50c9431203
Emit debug info for byval parameters.
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llvm-svn: 102486
2010-04-28 01:39:28 +00:00
347e3b8f15
Rather than having a ton of patterns for double shift instructions, e.g. SHLD16rrCL, just perform custom dag combine to form x86 specific dag so they match to the same pattern. This also makes sure later dag combine do not cause isel to miss them (e.g. promoting i16 to i32).
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llvm-svn: 102485
2010-04-28 01:18:01 +00:00
a3facc5cb5
further simplify EmitAlignment by eliminating the
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ForcedAlignBits argument, tweaking the single client of it.
llvm-svn: 102484
2010-04-28 01:08:40 +00:00
72bdee4c10
remove a dead argument to EmitAlignment.
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llvm-svn: 102483
2010-04-28 01:06:02 +00:00
9e06e53fc6
remove some default arguments to EmitAlignment.
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llvm-svn: 102482
2010-04-28 01:05:45 +00:00
173b2b9d05
Refactor.
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llvm-svn: 102481
2010-04-28 01:03:09 +00:00
2f1ae06c45
Rewrite the section on trap values to contain a generic description
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of dependence and define trap values in terms of dependence, instead
of trying to cover the concept with a flurry of ad-hoc rules.
The dependence model isn't complete yet, but it's already much more
rigorous than the description it replaces.
llvm-svn: 102479
2010-04-28 00:49:41 +00:00
61110aed26
Fix spelling errors.
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llvm-svn: 102478
2010-04-28 00:36:01 +00:00
c0458f1a40
Tweak x86 INC/DEC generation to look for CopyToReg or SETCC. Radar 7866163.
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llvm-svn: 102477
2010-04-28 00:35:10 +00:00
4bd85e47bf
further clarify alignment of globals, fix instcombine
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to not increase the alignment of globals with an assigned
alignment and section.
llvm-svn: 102476
2010-04-28 00:31:12 +00:00
78e00bcb76
improve the global variable alignment description.
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it is not generally valid for targets to overalign
them when an alignment is specified.
llvm-svn: 102474
2010-04-28 00:13:42 +00:00
12f6855f85
Use MachineOperand::is* predicates.
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llvm-svn: 102472
2010-04-27 22:24:37 +00:00
cfc76fdaf1
Use isReg(), isImm() and isFPImm().
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llvm-svn: 102470
2010-04-27 22:04:41 +00:00
1f34c2727d
Check operand type first.
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llvm-svn: 102468
2010-04-27 21:49:04 +00:00
9e3a4ef089
Fix obvious typos.
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llvm-svn: 102467
2010-04-27 21:46:03 +00:00
1a0bbe25e3
Ignore DBG_VALUE instructions that points to undef values.
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llvm-svn: 102463
2010-04-27 20:54:45 +00:00
3b928af28f
SRA promotion is also not free.
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llvm-svn: 102456
2010-04-27 19:48:31 +00:00
e813690b7a
- When legal, promote a load to zextload rather than ext load.
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- Catch more further dag combine opportunities as result of operand promotion, e.g. (i32 anyext (i16 trunc (i32 x))) -> (i32 x)
llvm-svn: 102455
2010-04-27 19:48:13 +00:00
6c74a872a8
Identify when a lexical scope is split in to multiple instruction ranges. Emit such ranges using DW_AT_ranges.
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This patch fixes bug (PR6894) introduced by previous version of this patch.
llvm-svn: 102454
2010-04-27 19:46:33 +00:00
eb828b6391
Do not count kill, implicit_def instructions as printed instructions.
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llvm-svn: 102453
2010-04-27 19:38:45 +00:00
64d43d80be
round zero-byte .zerofill directives up to 1 byte. This
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should fix some "g++.dg-struct-layout-1" failures,
rdar://7886017
llvm-svn: 102421
2010-04-27 07:41:44 +00:00
a3cc83bc82
fix wordo
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llvm-svn: 102418
2010-04-27 07:28:11 +00:00
0260a975ba
remove some comments.
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llvm-svn: 102417
2010-04-27 06:57:10 +00:00
eb61a7d616
Revert a small part of 102372; this fixes at least one
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of the dbg testsuite regressions. I don't think this is
really the right fix; this change exposed an existing problem
upstream somewhere.
llvm-svn: 102410
2010-04-27 02:10:05 +00:00
633c48ec1d
r98363 deleted a '!' when cleaning up whitespace. This caused globals which are
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*not* declarations to *not* be placed in the "preserve" list.
<rdar://problem/7870735>
llvm-svn: 102405
2010-04-27 00:55:25 +00:00
022e7b900f
Un-XFAIL this on ppc. My enabling of dbg_declare handling
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in ISel fixed it.
llvm-svn: 102404
2010-04-27 00:01:42 +00:00
44a27efdf9
Fix a problem that lower invoke has with allocas (PR6694), and
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add a version of createLowerInvokePass that allows the client
to specify whether it wants "expensive" or "cheap" lowering.
Patch by Alex Mac!
llvm-svn: 102402
2010-04-26 23:49:32 +00:00
3af635a296
add a comment in verbose-asm mode indicating why a noop is being generated.
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llvm-svn: 102401
2010-04-26 23:41:43 +00:00
6a5e706e3c
on darwin empty functions need to codegen into something of non-zero length,
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otherwise labels get incorrectly merged. We handled this by emitting a
".byte 0", but this isn't correct on thumb/arm targets where the text segment
needs to be a multiple of 2/4 bytes. Handle this by emitting a noop. This
is more gross than it should be because arm/ppc are not fully mc'ized yet.
This fixes rdar://7908505
llvm-svn: 102400
2010-04-26 23:37:21 +00:00
b8b85c1ddb
Integrate Jeffery Yasskin's suggestions with respect to
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traps flowing through memory references, add some text to
better cover phi nodes and externally-visible side effects,
add an example of instructions being control-dependent
on a trap value, and reword some of the existing trap rules.
llvm-svn: 102399
2010-04-26 23:36:52 +00:00
25f85947a3
Handle register-to-register copies within the tGPR class.
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Radar 7896289
llvm-svn: 102396
2010-04-26 23:20:08 +00:00
a1e343095f
Avoid adding a null MD node operand, which crashes with "-debug" when trying
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to print the operand.
llvm-svn: 102395
2010-04-26 22:56:56 +00:00
bd798ce8dd
Use DW_AT_entry_pc instead of DW_AT_low_pc/DW_AT_high_pc pair. This simplifies debug range entries.
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llvm-svn: 102394
2010-04-26 22:54:28 +00:00
58b0470592
When checking whether the special handling for an addrec increment which
...
doesn't dominate the header is needed, don't check whether the increment
expression has computable loop evolution. While the operands of an
addrec are required to be loop-invariant, they're not required to
dominate any part of the loop. This fixes PR6914.
llvm-svn: 102389
2010-04-26 21:46:36 +00:00
Jim Grosbach