llvm-project

Author	SHA1	Message	Date
Craig Topper	b05d9e9bea	Add X86 SARX, SHRX, and SHLX instructions. llvm-svn: 142779	2011-10-23 22:18:24 +00:00
Craig Topper	980d59832a	Add X86 RORX instruction llvm-svn: 142741	2011-10-23 07:34:00 +00:00
Craig Topper	ef309c3384	Rename PEXTR to PEXT. Add intrinsics for BMI instructions. llvm-svn: 142480	2011-10-19 07:48:35 +00:00
Craig Topper	96fa597828	Add X86 PEXTR and PDEP instructions. llvm-svn: 142141	2011-10-16 16:50:08 +00:00
Craig Topper	aea148c366	Add X86 BZHI instruction as well as BMI2 feature detection. llvm-svn: 142122	2011-10-16 07:55:05 +00:00
Craig Topper	25ea4e5ad3	Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen llvm-svn: 142105	2011-10-16 03:51:13 +00:00
Craig Topper	27ad12539d	Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension. llvm-svn: 142082	2011-10-15 20:46:47 +00:00