Craig Topper
916d0cf649
[X86] Move the 'vmovq.s' and similar assembly strings for EVEX vector moves with reversed operands to InstAliases.
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The .s assembly strings allow the reversed forms to be targeted from assembly which matches gas behavior. But when printing the instructions we should print them without the .s to match other tooling like objdump. By using InstAliases we can use the normal string in the instruction and just hide it from the assembly parser.
Ideally we'd add the .s versions to the legacy SSE and VEX versions as well for full compatibility with gas. Not sure how we got to state where only EVEX was supported.
llvm-svn: 334920
2018-06-18 01:28:05 +00:00
Craig Topper
e538fc74d4
[X86] Remove checks for FeatureAVX512 from the X86 assembly parser. Remove mcpu/mattr from assembly test command lines.
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Summary:
We should always be able to accept AVX512 registers and instructions in llvm-mc. The only subtarget mode that should be checked is 16-bit vs 32-bit vs 64-bit mode.
I've also removed all the mattr/mcpu lines from test RUN lines to be consistent with this. Most were due to AVX512, but a few were for other features.
Fixes PR36202
Reviewers: RKSimon, echristo, bkramer
Reviewed By: echristo
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D42824
llvm-svn: 324106
2018-02-02 17:02:58 +00:00
Craig Topper
b6da65403a
[AVX512] VPACKUSWB/VPACKSSWB should not be encoded with EVEX.W=1. While there fix the execution domain for VPACKSSDW/VPACKUSDW.
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llvm-svn: 268200
2016-05-01 17:38:32 +00:00
Igor Breger
81b79de54c
AVX512: Implemented encoding for the follow instructions.
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vmovapd.s, vmovaps.s, vmovdqa32.s, vmovdqa64.s, vmovdqu16.s, vmovdqu32.s, vmovdqu64.s, vmovdqu8.s, vmovupd.s, vmovups.s
Differential Revision: http://reviews.llvm.org/D14768
llvm-svn: 253546
2015-11-19 07:43:43 +00:00
Igor Breger
21296d230a
AVX512: Implemented encoding and intrinsics for VPBROADCASTB/W/D/Q instructions.
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Differential Revision: http://reviews.llvm.org/D13884
llvm-svn: 250819
2015-10-20 11:56:42 +00:00
Igor Breger
1a6fd1cc0f
AVX512: Change encoding of vpshuflw and vpshufhw instructions. Implement WIG as W0 and not W1, like all other instruction have been implemented.
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Add encoding tests.
Differential Revision: http://reviews.llvm.org/D13471
llvm-svn: 249521
2015-10-07 06:31:18 +00:00
Asaf Badouh
d2c3599c5f
[X86][AVX512VLBW] add support in byte shift and SAD
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add byte shift left/right
add SAD - compute sum of absolute differences
Differential Revision: http://reviews.llvm.org/D12479
llvm-svn: 246654
2015-09-02 14:21:54 +00:00
Igor Breger
f3ded811b2
AVX512: Implemented encoding and intrinsics for vdbpsadbw
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Added tests for intrinsics and encoding.
Differential Revision: http://reviews.llvm.org/D12491
llvm-svn: 246436
2015-08-31 13:09:30 +00:00
Igor Breger
2ae0fe3ac3
AVX512: Implemented encoding and intrinsics for vpalignr
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Added tests for intrinsics and encoding.
Differential Revision: http://reviews.llvm.org/D12270
llvm-svn: 246428
2015-08-31 11:14:02 +00:00
Igor Breger
47a7b95b1d
AVX512: Add encoding tests to vptestnm instructions
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Differential Revision: http://reviews.llvm.org/D11521
llvm-svn: 243391
2015-07-28 07:00:00 +00:00
Igor Breger
f2460112ad
Implemented encoding and intrinsics of the following instructions
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vunpckhps/pd, vunpcklps/pd,
vpunpcklbw, vpunpckhbw, vpunpcklwd, vpunpckhwd, vpunpckldq, vpunpckhdq, vpunpcklqdq, vpunpckhqdq
Added tests for intrinsics and encoding.
Differential Revision: http://reviews.llvm.org/D11509
llvm-svn: 243246
2015-07-26 14:41:44 +00:00
Igor Breger
074a64e72c
AVX-512: Implemented encoding , DAG lowering and intrinsics for Integer Truncate with/without saturation
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Added tests for DAG lowering ,encoding and intrinsic
Differential Revision: http://reviews.llvm.org/D11218
llvm-svn: 243122
2015-07-24 17:24:15 +00:00
Chandler Carruth
fe414353db
Revert r242990: "AVX-512: Implemented encoding , DAG lowering and ..."
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This commit broke the build. Numerous build bots broken, and it was
blocking my progress so reverting.
It should be trivial to reproduce -- enable the BPF backend and it
should fail when running llvm-tblgen.
llvm-svn: 242992
2015-07-23 08:03:44 +00:00
Igor Breger
da1b2ea955
AVX-512: Implemented encoding , DAG lowering and intrinsics for Integer Truncate with/without saturation
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Added tests for DAG lowering ,encoding and intrinsic
Differential Revision: http://reviews.llvm.org/D11218
llvm-svn: 242990
2015-07-23 07:39:21 +00:00
Igor Breger
f7fd547e27
AVX512 : Implemented VPMADDUBSW and VPMADDWD instruction ,
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Added tests for intrinsics and encoding.
Differential Revision: http://reviews.llvm.org/D11351
llvm-svn: 242761
2015-07-21 07:11:28 +00:00
Asaf Badouh
c6f3c82ffc
[X86][AVX512] Multiply Packed Unsigned Integers with Round and Scale
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pmulhrsw
review:
http://reviews.llvm.org/D10948
llvm-svn: 241443
2015-07-06 14:03:40 +00:00
Asaf Badouh
73f26f8ffc
[x86][AVX512] add Multiply High Op
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include encoding and intrinsics tests.
review
http://reviews.llvm.org/D10896
llvm-svn: 241406
2015-07-05 12:23:20 +00:00
Elena Demikhovsky
55a997437c
AVX-512: added VPSHUFB instruction - all SKX forms
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Added intrinsics and encoding tests.
llvm-svn: 240277
2015-06-22 13:00:42 +00:00
Asaf Badouh
81f03c30a5
[AVX512]
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add instructions: VPAVGB and VPAVGW
review
http://reviews.llvm.org/D10504
llvm-svn: 240012
2015-06-18 12:30:53 +00:00
Elena Demikhovsky
d3057e5e37
AVX-512: (fixed) Added encoding of all forms of VPERMT2W/D/Q/PS/PD and VPERMI2W/D/Q/PS/PD.
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Intrinsics and tests for them are comming in the next patch.
llvm-svn: 240003
2015-06-18 08:56:19 +00:00
Elena Demikhovsky
4f13f3f9b8
reverted 239999 due to test failures
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llvm-svn: 240001
2015-06-18 08:06:49 +00:00
Elena Demikhovsky
975a637cd9
AVX-512: Added encoding of all forms of VPERMT2W/D/Q/PS/PD
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and VPERMI2W/D/Q/PS/PD.
Intrinsics and tests for them are comming in the next patch.
llvm-svn: 239999
2015-06-18 07:29:40 +00:00
Elena Demikhovsky
75ede68793
AVX-512: added all forms of VPSHUFD and VPSHUFHW, VPSHUFLW
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including encodings.
llvm-svn: 238729
2015-06-01 07:17:23 +00:00
Elena Demikhovsky
3948c590e3
AVX-512: Implemented all forms of sign-extend and zero-extend instructions for KNL and SKX
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Implemented DAG lowering for all these forms.
Added tests for DAG lowering and encoding.
By Igor Breger (igor.breger@intel.com )
llvm-svn: 238301
2015-05-27 08:15:19 +00:00
Elena Demikhovsky
52266388f8
AVX-512: added integer "add" and "sub" instructions with saturation for SKX
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with intrinsics and tests
by Asaf Badouh (asaf.badouh@intel.com )
llvm-svn: 236418
2015-05-04 12:35:55 +00:00
Elena Demikhovsky
2557a22be7
AVX-512: Added VPACK* instructions forms for KNL and SKX
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and their intrinsics
by Asaf Badouh (asaf.badouh@intel.com )
llvm-svn: 236414
2015-05-04 09:14:02 +00:00
Elena Demikhovsky
0b9dbe33aa
AVX-512: Added SKX forms of shift instructions.
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Added rotation instructions, encoding only.
Added encoding tests for all these forms.
llvm-svn: 231916
2015-03-11 10:25:42 +00:00
Robert Khasanov
cbc5703aeb
[AVX512] Added VPBROADCAST{BWDQ} (Load with Broadcast Integer Data from General Purpose Register) encodings for AVX512-BW/VL subsets
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Added encoding tests.
llvm-svn: 223787
2014-12-09 16:38:41 +00:00
Robert Khasanov
545d1b7726
[AVX512] Extended avx512_binop_rm to BW/VL subsets.
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Added encoding tests.
llvm-svn: 219685
2014-10-14 14:36:19 +00:00
Robert Khasanov
29e3b96734
[SKX] Added new versions of cmp instructions in avx512_icmp_cc multiclass, added VL multiclass.
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Added encoding tests
llvm-svn: 216532
2014-08-27 09:34:37 +00:00
Robert Khasanov
2ea081d4d1
[SKX] avx512_icmp_packed multiclass extension
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Extended avx512_icmp_packed multiclass by masking versions.
Added avx512_icmp_packed_rmb multiclass for embedded broadcast versions.
Added corresponding _vl multiclasses.
Added encoding tests for CPCMP{EQ|GT}* instructions.
Add more fields for X86VectorVTInfo.
Added AVX512VLVectorVTInfo that include X86VectorVTInfo for 512/256/128-bit versions
Differential Revision: http://reviews.llvm.org/D5024
llvm-svn: 216383
2014-08-25 14:49:34 +00:00
Robert Khasanov
7ca7df0bf9
[SKX] Enabling load/store instructions: encoding
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Instructions: VMOVAPD, VMOVAPS, VMOVDQA8, VMOVDQA16, VMOVDQA32,VMOVDQA64, VMOVDQU8, VMOVDQU16, VMOVDQU32,VMOVDQU64, VMOVUPD, VMOVUPS,
Reviewed by Elena Demikhovsky <elena.demikhovsky@intel.com>
llvm-svn: 214719
2014-08-04 14:35:15 +00:00