e6fbca3a61
ARM vmul assembly parsing for the lane index operand.
...
llvm-svn: 142381
2011-10-18 18:01:52 +00:00
f416cb16c0
Tidy up.
...
llvm-svn: 142380
2011-10-18 18:01:09 +00:00
c91064551a
Add a few more testcases.
...
llvm-svn: 142379
2011-10-18 17:57:31 +00:00
2a498c1107
Add several FIXME cases for ARM encodings.
...
llvm-svn: 142377
2011-10-18 17:50:22 +00:00
8206790ab0
Tests for 142365.
...
llvm-svn: 142368
2011-10-18 17:23:34 +00:00
95135982cd
Tidy up formatting.
...
llvm-svn: 142367
2011-10-18 17:22:53 +00:00
e4454e0de2
ARM assembly parsing and encoding for VMOV.i64.
...
llvm-svn: 142356
2011-10-18 16:18:11 +00:00
8211c051ca
ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i32.
...
llvm-svn: 142321
2011-10-18 00:22:00 +00:00
26bfc9e5da
Enable a few more NEON immediate tests.
...
llvm-svn: 142313
2011-10-17 23:50:19 +00:00
cda32ae372
ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i16.
...
llvm-svn: 142303
2011-10-17 23:09:09 +00:00
40f8f2ff24
Add support for a new extension to the .file directive:
...
.file filenumber "directory" "filename"
This removes one join+split of the directory+filename in MC internals. Because
bitcode files have independent fields for directory and filenames in debug info,
this patch may change the .o files written by existing .bc files.
llvm-svn: 142300
2011-10-17 23:05:28 +00:00
741cd73aab
ARM NEON "vmov.i8" immediate assembly parsing and encoding.
...
NEON immediates are "interesting". Start of the work to handle parsing them
in an 'as' compatible manner. Getting the matcher to play nicely with
these and the floating point immediates from VFP is an extra fun wrinkle.
llvm-svn: 142293
2011-10-17 22:26:03 +00:00
96fa597828
Add X86 PEXTR and PDEP instructions.
...
llvm-svn: 142141
2011-10-16 16:50:08 +00:00
aea148c366
Add X86 BZHI instruction as well as BMI2 feature detection.
...
llvm-svn: 142122
2011-10-16 07:55:05 +00:00
0ae8d4d738
Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, VMREAD, and VMWRITE to remove hack from X86RecognizableInstr.
...
llvm-svn: 142117
2011-10-16 07:05:40 +00:00
a3a0681083
Enhance llvm::SourceMgr to support diagnostic ranges, the same way clang does. Enhance
...
the X86 asmparser to produce ranges in the one case that was annoying me, for example:
test.s:10:15: error: invalid operand for instruction
movl 0(%rax), 0(%edx)
^~~~~~~
It should be straight-forward to enhance filecheck, tblgen, and/or the .ll parser to use
ranges where appropriate if someone is interested.
llvm-svn: 142106
2011-10-16 04:47:35 +00:00
25ea4e5ad3
Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen
...
llvm-svn: 142105
2011-10-16 03:51:13 +00:00
27ad12539d
Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension.
...
llvm-svn: 142082
2011-10-15 20:46:47 +00:00
220f2643fa
Update test for disabling of code/data marker labels in ELF.
...
llvm-svn: 142003
2011-10-14 21:12:55 +00:00
965de2c197
Add X86 ANDN instruction. Including instruction selection.
...
llvm-svn: 141947
2011-10-14 07:06:56 +00:00
3657fe4b17
Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell.
...
llvm-svn: 141939
2011-10-14 03:21:46 +00:00
063f55ffdd
Revert r141854 because it was causing failures:
...
http://lab.llvm.org:8011/builders/llvm-x86_64-linux/builds/101
--- Reverse-merging r141854 into '.':
U test/MC/Disassembler/X86/x86-32.txt
U test/MC/Disassembler/X86/simple-tests.txt
D test/CodeGen/X86/bmi.ll
U lib/Target/X86/X86InstrInfo.td
U lib/Target/X86/X86ISelLowering.cpp
U lib/Target/X86/X86.td
U lib/Target/X86/X86Subtarget.h
llvm-svn: 141857
2011-10-13 07:48:07 +00:00
8cc9388073
Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell.
...
llvm-svn: 141854
2011-10-13 07:09:14 +00:00
e7c0c499b8
Finish supporting cpp #file/line comments in assembler for error messages. So
...
for cpp pre-processed assembly we give correct filename and line numbers when
reporting errors in assembly files when using clang and -integrated-as on .s
files. rdar://8998895
llvm-svn: 141814
2011-10-12 21:38:39 +00:00
54a20ed0f1
Thumb2 assembly parsing and encoding for LDC/STC.
...
llvm-svn: 141811
2011-10-12 20:54:17 +00:00
84cf2b8c98
ARM encoding tests for STC.
...
llvm-svn: 141787
2011-10-12 17:36:13 +00:00
483995875f
ARM parsing and encoding for the <option> form of LDC/STC instructions.
...
llvm-svn: 141786
2011-10-12 17:34:41 +00:00
9398141c48
ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions.
...
Fill out the rest of the encoding information, update to properly mark
the LDC/STC instructions as predicable while the LDC2/STC2 instructions are
not, and adjust the parser accordingly.
llvm-svn: 141721
2011-10-11 21:55:36 +00:00
8c799c9826
Update test for r141704.
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llvm-svn: 141705
2011-10-11 20:18:50 +00:00
3e01bd3b60
Apparently, sometimes llvm-nm doesn't put the undefined symbol at the top. Take
...
that into account and test for no U's showing up in the middle, which is what
we really wanted to test for.
llvm-svn: 141653
2011-10-11 06:58:11 +00:00
271064e873
Add X86 LZCNT instruction. Including instruction selection support.
...
llvm-svn: 141651
2011-10-11 06:44:02 +00:00
a697852386
Fix disassembling of popcntw. Also remove some code that says it accounts for 64BIT_REXW_XD not existing, but it does exist.
...
llvm-svn: 141642
2011-10-11 04:34:23 +00:00
29e7b315ac
Also create a shndx even if there are no symbols. This lets us test
...
.symtab_shndx reading and writing together, and finally we have a testcase for
r141440.
llvm-svn: 141641
2011-10-11 03:54:50 +00:00
b253f490c3
Insert dummy ED table entries for pseudo-instructions.
...
The table is indexed by opcode, so simply removing pseudo-instructions
creates a wrong mapping from opcode to table entry.
Add a test case for xorps which has a very high opcode that exposes this
problem.
llvm-svn: 141562
2011-10-10 18:30:16 +00:00
fe9179fa4f
Add Ivy Bridge 16-bit floating point conversion instructions for the X86 disassembler.
...
llvm-svn: 141505
2011-10-09 07:31:39 +00:00
c87d60a58c
Enable ARM mode VDUP(scalar) tests.
...
llvm-svn: 141447
2011-10-07 23:57:03 +00:00
d0637bfc68
ARM NEON assembly parsing and encoding for VDUP(scalar).
...
llvm-svn: 141446
2011-10-07 23:56:00 +00:00
d9cfddc5cd
Add X86 disassembler support for RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE.
...
llvm-svn: 141358
2011-10-07 07:02:24 +00:00
bf136764ae
Add X86 disassembler support for XSAVE, XRSTOR, and XSAVEOPT.
...
llvm-svn: 141354
2011-10-07 05:53:50 +00:00
5aebebe18d
Revert part of r141274. Only need to change encoding for xchg %eax, %eax in 64-bit mode. This is because in 64-bit mode xchg %eax, %eax implies zeroing the upper 32-bits of RAX which makes it not a NOP. In 32-bit mode using NOP encoding is fine.
...
llvm-svn: 141353
2011-10-07 05:35:38 +00:00
0947102623
Tidy up tests. Un-XFAIL file and mark individual tests as FIXME instead.
...
llvm-svn: 141321
2011-10-06 22:04:05 +00:00
4887469138
Fix and clean up tests. Un-XFAIL.
...
llvm-svn: 141318
2011-10-06 21:32:50 +00:00
ceb4c7523f
Fix and clean up tests. Un-XFAIL.
...
llvm-svn: 141316
2011-10-06 21:28:30 +00:00
23eb468b1f
Fix assembling of xchg %eax, %eax to not use the NOP encoding of 0x90. This was done by creating a new register group that excludes AX registers. Fixes PR10345. Also added aliases for flipping the order of the operands of xchg <reg>, %eax.
...
llvm-svn: 141274
2011-10-06 06:44:41 +00:00
10c5b12f99
Support a valid, but not very useful, encoding of CPSIE where none of the AIF bits are set.
...
llvm-svn: 141190
2011-10-05 17:16:40 +00:00
0ca562ec4c
Teach the MC to output code/data region marker labels in MachO and ELF modes. These are used by disassemblers to provide better disassembly, particularly on targets like ARM Thumb that like to intermingle data in the TEXT segment.
...
llvm-svn: 141135
2011-10-04 23:26:17 +00:00
28a0bc5562
Tidy up formatting.
...
llvm-svn: 141123
2011-10-04 21:43:51 +00:00
4879f70ab9
Un-XFAIL file. Comment out individual failing instructions.
...
llvm-svn: 141117
2011-10-04 21:16:42 +00:00
f3e1fc3f86
Tidy up formatting.
...
llvm-svn: 141115
2011-10-04 20:52:57 +00:00
8a829e8ecb
Un-XFAIL file. Fix incorrect CHECK lines. General format cleanup.
...
llvm-svn: 141114
2011-10-04 20:50:05 +00:00
8bc8bfdcad
Un-XFAIL file. Fix incorrect CHECK line. General format cleanup.
...
llvm-svn: 141113
2011-10-04 20:46:49 +00:00
610aa62edc
Tidy up formatting.
...
llvm-svn: 141111
2011-10-04 20:42:35 +00:00
388c0f61e8
Un-XFAIL file. Fix incorrect CHECK line.
...
llvm-svn: 141110
2011-10-04 20:42:09 +00:00
2644375abe
Un-XFAIL the file. Disable only the individual tests that aren't working yet.
...
llvm-svn: 141108
2011-10-04 20:34:11 +00:00
83e84faa8f
Un-XFAIL the file. Disable only the individual tests that aren't working yet.
...
llvm-svn: 141099
2011-10-04 18:43:15 +00:00
2d9eb707af
Tidy up. Formatting.
...
llvm-svn: 141096
2011-10-04 17:49:45 +00:00
f18c896337
Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676.
...
llvm-svn: 141065
2011-10-04 06:30:42 +00:00
b85400aa58
Tidy up. These tests are covered in the .s file tests now.
...
llvm-svn: 141047
2011-10-03 23:40:13 +00:00
e7fbce7acb
ARM assembly parsing and encoding for VMOV immediate.
...
llvm-svn: 141046
2011-10-03 23:38:36 +00:00
46b6646059
ARM parsing/encoding for VCMP/VCMPE.
...
llvm-svn: 141038
2011-10-03 22:30:24 +00:00
4ab23b5273
ARM assembly parsing and encoding for VMRS/FMSTAT.
...
llvm-svn: 141025
2011-10-03 21:12:43 +00:00
c3fc62b492
Update test for 141010.
...
llvm-svn: 141022
2011-10-03 20:58:08 +00:00
b817655b77
Tidy up a bit. Formatting.
...
llvm-svn: 141010
2011-10-03 17:59:31 +00:00
786bdb9e14
Add support for MOVBE and RDRAND instructions for the assembler and disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027.
...
llvm-svn: 141007
2011-10-03 17:28:23 +00:00
0d0be47d03
Treat VEX.vvvv as a 3-bit field outside of 64-bit mode. Prevents access to registers xmm8-xmm15 outside 64-bit mode.
...
llvm-svn: 140997
2011-10-03 08:14:29 +00:00
285bc34089
Test updates that were supposed to go with r140993.
...
llvm-svn: 140994
2011-10-03 07:53:59 +00:00
7aea69d949
Fix some Intel syntax disassembly issues with instructions that implicitly use AL/AX/EAX/RAX such as ADD/SUB/ADC/SUBB/XOR/OR/AND/CMP/MOV/TEST.
...
llvm-svn: 140974
2011-10-02 21:08:12 +00:00
21c33657d6
Special case disassembler handling of REX.B prefix on NOP instruction to decode as XCHG R8D, EAX instead. Fixes PR10344.
...
llvm-svn: 140971
2011-10-02 16:56:09 +00:00
d07a59f288
Fix disassembling of INVEPT and INVVPID to take operands
...
llvm-svn: 140955
2011-10-01 21:20:14 +00:00
88cb33e0d4
Fix disassembler handling of CRC32 which is an odd instruction that uses 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702.
...
llvm-svn: 140954
2011-10-01 19:54:56 +00:00
21efa7d6e1
Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit.
...
Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format.
Add decoder and disassembler tests.
Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT.
llvm-svn: 140696
2011-09-28 14:21:38 +00:00
c63af1b7b6
ARM Thumb2 asm parsing [SU]XT[BH] without rotate but with .w.
...
Add inst alias to handle these assembly forms. Add tests, too.
rdar://10178799
llvm-svn: 140647
2011-09-27 22:18:54 +00:00
287d6ef088
Fix an incorrect decoder test.
...
llvm-svn: 140579
2011-09-26 23:08:34 +00:00
d20cd25c69
Remove incorrect testcases.
...
llvm-svn: 140572
2011-09-26 22:13:55 +00:00
45faba98b4
Fix VEX decoding in i386 mode. Fixes PR11008.
...
llvm-svn: 140515
2011-09-26 05:12:43 +00:00
4916840eb8
Teach the Thumb2 AsmParser to accept pre-indexed loads/stores with an offset of #-0.
...
llvm-svn: 140426
2011-09-23 22:25:02 +00:00
b75772201f
Fix incorrect disassembly test.
...
llvm-svn: 140423
2011-09-23 22:05:54 +00:00
737beaf86d
Post-index loads/stores in still need to print the post-indexed immediate, even if it's zero, to distinguish them from non-post-indexed instructions.
...
llvm-svn: 140420
2011-09-23 21:26:40 +00:00
987a878946
Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid testcases updated.
...
llvm-svn: 140415
2011-09-23 21:07:25 +00:00
526adabe87
Don't allow 32-bit only instructions to be disassembled in 64-bit mode. Fixes part of PR10700.
...
llvm-svn: 140370
2011-09-23 06:57:25 +00:00
6d1872b77a
Fix register printing in disassembling of push/pop of segment registers and in/out in Intel syntax mode. Fixes PR10960
...
llvm-svn: 140299
2011-09-22 07:01:50 +00:00
fbe52c0192
Turns out that Thumb2 ADR doesn't need special printing like LDR does. Fix other test failures I caused.
...
llvm-svn: 140284
2011-09-21 23:53:44 +00:00
f52c68f0ca
Print out immediate offset versions of PC-relative load/store instructions as [pc, #123 ] rather than simply #123 .
...
llvm-svn: 140283
2011-09-21 23:44:46 +00:00
33e91a6cf7
The wrong relocation was being emitted for several SSSE3 instructions.
...
This fixes PR10963. Thanks to Benjamin for finding the wrong tablegen
declaration.
llvm-svn: 140184
2011-09-20 21:39:21 +00:00
2b35d7cff1
Port over more Thumb2 encoding tests to decoding tests.
...
llvm-svn: 140152
2011-09-20 17:44:48 +00:00
a316da1466
Nuke obsolete test file.
...
llvm-svn: 140127
2011-09-20 01:03:51 +00:00
c70d9dfaea
Thumb2 assembly parsing and encoding for WFE/WFI/YIELD.
...
llvm-svn: 140126
2011-09-20 00:48:56 +00:00
b35198021a
Thumb2 assembly parsing and encoding for UXTAB/UXTAB16/UXTH/UXTB/UXTB16/UXTH.
...
llvm-svn: 140125
2011-09-20 00:46:54 +00:00
5aaeb91ca6
Thumb2 assembly parsing and encoding for USUB8/USUB16.
...
llvm-svn: 140120
2011-09-20 00:31:57 +00:00
716f17399e
Thumb2 assembly parsing and encoding for USAX.
...
llvm-svn: 140119
2011-09-20 00:30:45 +00:00
42f7b647fa
Thumb2 assembly parsing and encoding for USAT16.
...
llvm-svn: 140118
2011-09-20 00:28:25 +00:00
e0493ade65
Thumb2 assembly parsing and encoding for USAT.
...
llvm-svn: 140117
2011-09-20 00:27:36 +00:00
e65c2ab453
Tidy up.
...
llvm-svn: 140114
2011-09-20 00:24:37 +00:00
db6d378f80
Thumb2 assembly parsing and encoding for UQSAD8/USADA8.
...
llvm-svn: 140113
2011-09-20 00:23:51 +00:00
6286f75161
Thumb2 assembly parsing and encoding for UQSUB16/UQSUB8.
...
llvm-svn: 140112
2011-09-20 00:20:44 +00:00
62f8eee0eb
Thumb2 assembly parsing and encoding for UQASX/UQSAX.
...
llvm-svn: 140111
2011-09-20 00:18:52 +00:00
4b0e7d9457
Thumb2 assembly parsing and encoding for UQADD16/UQADD8.
...
llvm-svn: 140110
2011-09-20 00:15:03 +00:00
c4398d2c7b
Fix PR10949. Fix the encoding of VMOVPQIto64rr.
...
llvm-svn: 140098
2011-09-19 23:36:59 +00:00
788a8cd4e6
Tidy up a bit.
...
llvm-svn: 140096
2011-09-19 23:34:18 +00:00
fc5451832a
Thumb2 assembly parsing and encoding for UMAAL/UMLAL/UMULL.
...
llvm-svn: 140095
2011-09-19 23:31:02 +00:00
Jim Grosbach