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4130 Commits

Author SHA1 Message Date
Bruno Cardoso Lopes 434248a62c Improve div/rem node handling on mips. Patch by Akira Hatanaka 
llvm-svn: 127034
 2011-03-04 21:03:24 +00:00
Bruno Cardoso Lopes d631599e38 Add testcase for r127032 
llvm-svn: 127033
 2011-03-04 20:48:39 +00:00
Dan Gohman aa036eedb8 When decling to reuse existing expressions that involve casts, ignore 
bitcasts, which are really no-ops here. This fixes slowdowns on
MultiSource/Applications/aha and others.

llvm-svn: 127031
 2011-03-04 20:46:46 +00:00
Joerg Sonnenberger 62f759791a Be nice to Xcore and the XMOS assembler and avoid quoting section names 
that contain only letters, digits and the characters "_" and ".".

llvm-svn: 127028
 2011-03-04 20:03:14 +00:00
Bruno Cardoso Lopes f8198e4311 Lowers block address. Currently asserts when relocation model is not PIC. Patch by Akira Hatanaka 
llvm-svn: 127027
 2011-03-04 20:01:52 +00:00
Devang Patel 906df92d5c XFAIL for all. These tests are darwin specific anyway. 
llvm-svn: 127022
 2011-03-04 19:38:10 +00:00
Devang Patel a0d73fd65e Disable ARMGlobalMerge on darwin. The debugger is not yet able to extract individual variable's info from merged global. 
llvm-svn: 127019
 2011-03-04 19:11:05 +00:00
Kalle Raiskila a1d947dd14 Allow vector shifts (shl,lshr,ashr) on SPU. 
There was a previous implementation with patterns that would 
have matched e.g. 
	shl <v4i32> <i32>,
but this is not valid LLVM IR so they never were selected.

llvm-svn: 126998
 2011-03-04 13:19:18 +00:00
Kalle Raiskila 3531e9b0d9 Allow load from constant on SPU. 
A 'load <4 x i32>* null' crashes llc before this fix.

llvm-svn: 126995
 2011-03-04 12:00:11 +00:00
Eli Friedman d8a555bb3b Revert r123908; the code in question is completely untested and wrong. 
llvm-svn: 126964
 2011-03-03 22:33:23 +00:00
Joerg Sonnenberger 852ab890b5 Bug#9033: For the ELF assembler output, always quote the section name. 
llvm-svn: 126963
 2011-03-03 22:31:08 +00:00
Stuart Hastings 3e7f2366fb Test case for r126864. Radar 9056407. 
llvm-svn: 126900
 2011-03-02 23:41:40 +00:00
David Greene dd567b214b [AVX] Fix mask predicates for 256-bit UNPCKLPS/D and implement 
missing patterns for them.

      Add a SIMD test subdirectory to hold tests for SIMD instruction
      selection correctness and quality.
'

llvm-svn: 126845
 2011-03-02 17:23:43 +00:00
Cameron Zwarich 5dd2aa2615 Eliminate the unused CodeGenPrepare option to split critical edges. 
llvm-svn: 126825
 2011-03-02 03:31:46 +00:00
Che-Liang Chiou 65b1476031 Extend initial support for primitive types in PTX backend 
- Allow i16, i32, i64, float, and double types, using the native .u16,
  .u32, .u64, .f32, and .f64 PTX types.
- Allow loading/storing of all primitive types.
- Allow primitive types to be passed as parameters.
- Allow selection of PTX Version and Shader Model as sub-target attributes.
- Merge integer/floating-point test cases for load/store.
- Use .u32 instead of .s32 to conform to output from NVidia nvcc compiler.

Patch by Justin Holewinski

llvm-svn: 126824
 2011-03-02 03:20:28 +00:00
Dan Gohman 7290868a1b Don't re-use existing addrec expansions if they contain casts. 
This fixes PR9259.

llvm-svn: 126812
 2011-03-02 01:34:10 +00:00
Evan Cheng 15fed7af3c Catch more cases where 2-address pass should 3-addressify instructions. rdar://9002648. 
llvm-svn: 126811
 2011-03-02 01:08:17 +00:00
Bill Wendling 3b1459b810 Narrow right shifts need to encode their immediates differently from a normal 
shift.

   16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0>
   32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0>
   64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0>

llvm-svn: 126723
 2011-03-01 01:00:59 +00:00
Jakob Stoklund Olesen 87d7408f29 Fix typo introduced by r126661: "Fix a typo which ..." 
llvm-svn: 126666
 2011-02-28 19:18:59 +00:00
Evan Cheng 6e3d443646 Fix a typo which cause dag combine crash. rdar://9059537. 
llvm-svn: 126661
 2011-02-28 18:45:27 +00:00
Duncan Sands f66e4611f9 Windows codegen also dies on this, so restrict to the platform it was 
actually tested on.

llvm-svn: 126652
 2011-02-28 14:22:08 +00:00
Duncan Sands feb9926a59 Make this test x86 specific because the ARM backend can't handle it. 
llvm-svn: 126650
 2011-02-28 12:30:47 +00:00
Che-Liang Chiou 75a800d3bf Add preliminary support for .f32 in the PTX backend. 
- Add appropriate TableGen patterns for fadd, fsub, fmul.
- Add .f32 as the PTX type for the LLVM float type.
- Allow parameters, return values, and global variable declarations
  to accept the float type.
- Add appropriate test cases.

Patch by Justin Holewinski

llvm-svn: 126636
 2011-02-28 06:34:09 +00:00
Duncan Sands f571290d1e Legalize support for fpextend of vector. PR9309. 
llvm-svn: 126574
 2011-02-27 14:41:27 +00:00
NAKAMURA Takumi d4e5003a3f Target/X86: Always emit "push/pop GPRs" in prologue/epilogue and emit "spill/reload frames" for XMMs. 
It improves Win64's prologue/epilogue but it would not affect ia32 and amd64 (lack of nonvolatile XMMs).

llvm-svn: 126568
 2011-02-27 08:47:19 +00:00
Cameron Zwarich 68f677a612 Fix PR9324 / <rdar://problem/9052489> by handling the case where a PHI has no uses. 
llvm-svn: 126567
 2011-02-27 08:06:01 +00:00
Cameron Zwarich baeb5f1431 Give a test file a more sensible name so that it can hold more test cases. 
llvm-svn: 126566
 2011-02-27 08:05:57 +00:00
Benjamin Kramer 26691d9660 Add some DAGCombines for (adde 0, 0, glue), which are useful to optimize legalized code for large integer arithmetic. 
1. Inform users of ADDEs with two 0 operands that it never sets carry
2. Fold other ADDs or ADDCs into the ADDE if possible

It would be neat if we could do the same thing for SETCC+ADD eventually, but we can't do that in target independent code.

llvm-svn: 126557
 2011-02-26 22:48:07 +00:00
Bob Wilson e3ecd5fb9b Add patterns to use post-increment addressing for Neon VST1-lane instructions. 
llvm-svn: 126477
 2011-02-25 06:42:42 +00:00
Nadav Rotem 502f1b943f Enable support for vector sext and trunc: 
Limit the folding of any_ext and sext  into the load operation to scalars.
Limit the active-bits trunc optimization to scalars.
Document vector trunc and vector sext in LangRef.

Similar to commit 126080 (for enabling zext).

llvm-svn: 126424
 2011-02-24 21:01:34 +00:00
Devang Patel b52040da17 Move arch specific tests in arch specific directories. 
llvm-svn: 126401
 2011-02-24 19:06:27 +00:00
Richard Osborne 42f52e737e Add XCore intrinsic for eeu instruction. 
llvm-svn: 126384
 2011-02-24 13:39:18 +00:00
Cameron Zwarich a62fc89a04 Merge information about the number of zero, one, and sign bits of live-out 
registers at phis. This enables us to eliminate a lot of pointless zexts during
the DAGCombine phase. This fixes <rdar://problem/8760114>.

llvm-svn: 126380
 2011-02-24 10:00:25 +00:00
Evan Cheng 3923466e82 Fix bug in X86 folding / unfolding table. Int_CMPSDrm and Int_CMPSSrm memory 
operands starts at index 2, not 1.
rdar://9045024
PR9305

llvm-svn: 126359
 2011-02-24 02:36:52 +00:00
Devang Patel 7b0f796c55 Use DW_FORM_data2 for DW_AT_language and let users use DW_LANG_lo_user=0x8000 to DW_LANG_hi_user=0xffff range. 
llvm-svn: 126339
 2011-02-23 22:37:04 +00:00
Devang Patel 37e056e455 Check only relevant strings in output to increase stability of the tests. 
llvm-svn: 126338
 2011-02-23 22:35:57 +00:00
Richard Osborne bfa5cc0e08 Add XCore intrinsic for clre instruction. 
llvm-svn: 126322
 2011-02-23 18:52:05 +00:00
Richard Osborne 4995b05f56 Add llvm.xcore.waitevent intrinsic. The effect of this intrinsic is to enable 
events on the thread and wait until a resource is ready to event. The vector
of the resource that is ready is returned.

llvm-svn: 126320
 2011-02-23 18:35:59 +00:00
Richard Osborne 2c610aa3ed Add XCore intrinsic for the setv instruction. 
llvm-svn: 126315
 2011-02-23 16:46:37 +00:00
Richard Osborne aab96995f6 Add XCore intrinsic for settw instruction. 
llvm-svn: 126313
 2011-02-23 14:45:03 +00:00
Evan Cheng d6b641e5bc More fcopysign correctness and performance fix. 
The previous codegen for the slow path (when values are in VFP / NEON
registers) was incorrect if the source is NaN.

The new codegen uses NEON vbsl instruction to copy the sign bit. e.g.
        vmov.i32        d1, #0x80000000
        vbsl    d1, d2, d0
If NEON is not available, it uses integer instructions to copy the sign bit.
rdar://9034702

llvm-svn: 126295
 2011-02-23 02:24:55 +00:00
NAKAMURA Takumi 7f5aa90d62 Revert r126195, "test/CodeGen/X86/vec_cast.ll: Mark as XFAIL: migw,win32 for workaround of PR8311." 
It seems it affected configuration --target=i686-pc-mingw32, I don't know and will investigate why.

llvm-svn: 126217
 2011-02-22 08:22:54 +00:00
NAKAMURA Takumi bced59bba7 Relax expressions and add explicit triplets -linux and -win32. 
llvm-svn: 126216
 2011-02-22 07:21:59 +00:00
NAKAMURA Takumi 384490cbe1 Relax expressions and add explicit triplets -linux and -win32. 
llvm-svn: 126215
 2011-02-22 07:21:51 +00:00
NAKAMURA Takumi 2a1ca28203 Relax expressions and add explicit triplets -linux and -win32. 
llvm-svn: 126214
 2011-02-22 07:21:42 +00:00
NAKAMURA Takumi fae5813d40 Relax expressions and add explicit triplets -linux and -win32. 
llvm-svn: 126213
 2011-02-22 07:21:33 +00:00
NAKAMURA Takumi 4d9d6ed377 Relax expressions and add explicit triplets -linux and -win32. 
llvm-svn: 126212
 2011-02-22 07:21:25 +00:00
NAKAMURA Takumi af669e5a4e Relax expressions and add explicit triplets -linux and -win32. 
On @foobar(double %d, double* %x),
AMD64: (%xmm0, %rdi)
Win64: (%xmm0, %rdx) (not %rcx!)

llvm-svn: 126211
 2011-02-22 07:21:17 +00:00
NAKAMURA Takumi a1e2ed5f1b Relax expressions and add explicit triplets -linux and -win32. 
llvm-svn: 126210
 2011-02-22 07:21:08 +00:00
NAKAMURA Takumi e38080bd8e Relax expressions and add explicit triplets -linux and -win32. 
llvm-svn: 126209
 2011-02-22 07:21:01 +00:00