Commit Graph

281272 Commits

Author SHA1 Message Date
Alexey Bataev 041ef2dd15 [SLP] Removed the warning about unused variable, NFC.
llvm-svn: 323533
2018-01-26 15:34:44 +00:00
Martin Probst f8e1f5c7d3 clang-format: [JS] Prevent ASI before [ and (.
Summary:
JavaScript automatic semicolon insertion can trigger before [ and (, so
avoid breaking before them if the previous token is likely to terminate
an expression.

Reviewers: djasper

Subscribers: cfe-commits, klimek

Differential Revision: https://reviews.llvm.org/D42570

llvm-svn: 323532
2018-01-26 15:07:49 +00:00
Simon Pilgrim 65ec923805 [X86][SSE] Add tests for vector truncation with PACKUS style signed saturation
PACKUS - truncates signed value, saturating to [0,unsigned_max_trunc]

llvm-svn: 323531
2018-01-26 14:58:50 +00:00
Alexey Bataev 167003df28 [SLP] Fix for PR32086: Count InsertElementInstr of the same elements as shuffle.
Summary:
If the same value is going to be vectorized several times in the same
tree entry, this entry is considered to be a gather entry and cost of
this gather is counter as cost of InsertElementInstrs for each gathered
value. But we can consider these elements as ShuffleInstr with
SK_PermuteSingle shuffle kind.

Reviewers: spatel, RKSimon, mkuper, hfinkel

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D38697

llvm-svn: 323530
2018-01-26 14:31:09 +00:00
Jonas Hahnfeld 723560d123 [OMPT] Use fuzzy return addresses in lock testcases
Use fuzzy return addresses in lock testcases so that these
testcases can also be run using the Intel Compiler.

Patch by Simon Convent!

Differential Revision: https://reviews.llvm.org/D41896

llvm-svn: 323529
2018-01-26 14:19:02 +00:00
Benjamin Kramer dfb730a032 [AST] Use bit packing to reduce sizeof(TypedefNameDecl) from 88 to 80.
We can stash the cached transparent tag bit in existing pointer padding.
Everything coming out of ASTContext is always aligned to a multiple of
8, so we have 8 spare bits.

llvm-svn: 323528
2018-01-26 14:14:11 +00:00
Dmitry Preobrazhensky 6cb42e7622 [AMDGPU][MC] Enabled disassembler for image atomic operations
See bug 35988: https://bugs.llvm.org/show_bug.cgi?id=35988

Differential Revision: https://reviews.llvm.org/D42186

Reviewers: vpykhtin, artem.tamazov, arsenm
llvm-svn: 323527
2018-01-26 14:07:38 +00:00
Simon Pilgrim 445d7c0e5c [X86] Cleanup SDLoc arguments as mentioned on D42544
llvm-svn: 323526
2018-01-26 14:00:01 +00:00
Clement Courbet 3c299e1b71 [TableGen][NFC]Remove dead variable.
llvm-svn: 323525
2018-01-26 13:21:43 +00:00
Sam McCall fdc3207dc1 [ASTImporter] avoid warnings: unused var, switch covered
llvm-svn: 323524
2018-01-26 12:06:44 +00:00
Alexey Bader d2c67a75b0 [OpenCL] Add "cles_khr_int64" extension.
Summary:
For OpenCL 1.1 embedded profile 64 bit integers i.e. long,
ulong including the appropriate vector data types and operations
on 64-bit integers are optional. The "cles_khr_int64" extension
string will be reported if the embedded profile implementation
supports 64-bit integers.

Reviewers: Anastasia, bader

Reviewed By: Anastasia, bader

Subscribers: bader, yaxunl, Anastasia, cfe-commits

Differential Revision: https://reviews.llvm.org/D42532

llvm-svn: 323522
2018-01-26 11:48:46 +00:00
Francis Visoiu Mistrih e4718e84e8 [MIR] Add support for addrspace in MIR
Add support for printing / parsing the addrspace of a MachineMemOperand.

Fixes PR35970.

Differential Revision: https://reviews.llvm.org/D42502

llvm-svn: 323521
2018-01-26 11:47:28 +00:00
Pavel Labath e8524e0ca2 Fix linux fallout from c++ gmodules enable
TestLibcxxListLoop - fails because the evil "define private public"
  trick does not work with gmodules. The purpose of the test is not to
  test debug info parsing so I just mark it as no_debug_info_testcase.
  In the long term it may be interesting to write a mock std::list which
  will allow us to test bad inputs to data formatters more easily.
TestGModules - seems to be a genuine bug. Filed pr36107 and xfailed.

llvm-svn: 323520
2018-01-26 11:40:59 +00:00
Aleksei Sidorin 8fc8510cb8 [ASTImporter] Support LambdaExprs and improve template support
Also, a number of style and bug fixes was done:

 *  ASTImporterTest: added sanity check for source node
 *  ExternalASTMerger: better lookup for template specializations
 *  ASTImporter: don't add templated declarations into DeclContext
 *  ASTImporter: introduce a helper, ImportTemplateArgumentListInfo getting SourceLocations
 *  ASTImporter: proper set ParmVarDecls for imported FunctionProtoTypeLoc

Differential Revision: https://reviews.llvm.org/D42301

llvm-svn: 323519
2018-01-26 11:36:54 +00:00
Sam McCall 24f0fa34c2 [clangd] Fix GCC build break 'declaration changes meaning'
llvm-svn: 323518
2018-01-26 11:23:33 +00:00
Eric Liu 2a27ebe670 [Tooling] Test more APIs of ToolExecutor. NFC.
llvm-svn: 323517
2018-01-26 11:10:32 +00:00
Daniil Fukalov 6e1dc68117 [AMDGPU] fix LDS f32 intrinsics
- using qualified pointer addrspace in intrinsics class to avoid .f32 mangling
- changed too common atomic mangling to ds
- added missing intrinsics to AMDGPUTTIImpl::getTgtMemIntrinsic

Reviewed by: b-sumner

Differential Revision: https://reviews.llvm.org/D42383

llvm-svn: 323516
2018-01-26 11:09:38 +00:00
Florian Hahn 212afb9fd9 [CallSiteSplitting] Fix infinite loop when recording conditions.
Fix infinite loop when recording conditions by correctly marking basic
blocks as visited.

Fixes https://bugs.llvm.org/show_bug.cgi?id=36105

llvm-svn: 323515
2018-01-26 10:36:50 +00:00
Momchil Velikov d2cc6fd90b [ARM] Accept a subset of Thumb GPR register class when emitting an SP-relative
load instruction

The function `Thumb1InstrInfo::loadRegFromStackSlot` accepts only the `tGPR`
register class. The function serves to emit a `tLDRspi` instruction and
certainly any subset of the `tGPR` register class is a valid destination of the
load.

Differential revision: https://reviews.llvm.org/D42535

llvm-svn: 323514
2018-01-26 10:20:58 +00:00
Andrei Elovikov cbc5a688f3 [X86FixupBWInsts] Prefer positive checks in the test. NFC
Reviewers: andrew.w.kaylor, craig.topper, MatzeB

Reviewed By: andrew.w.kaylor

Subscribers: aivchenk, llvm-commits

Differential Revision: https://reviews.llvm.org/D42531

llvm-svn: 323513
2018-01-26 09:50:32 +00:00
Sjoerd Meijer 011de9c0ca [ARM] Armv8.2-A FP16 code generation (part 1/3)
This is the groundwork for Armv8.2-A FP16 code generation .

Clang passes and returns _Float16 values as floats, together with the required
bitconverts and truncs etc. to implement correct AAPCS behaviour, see D42318.
We will implement half-precision argument passing/returning lowering in the ARM
backend soon, but for now this means that this:

_Float16 sub(_Float16 a, _Float16 b) {
  return a + b;
}

gets lowered to this:

define float @sub(float %a.coerce, float %b.coerce) {
entry:
  %0 = bitcast float %a.coerce to i32
  %tmp.0.extract.trunc = trunc i32 %0 to i16
  %1 = bitcast i16 %tmp.0.extract.trunc to half
  <SNIP>
  %add = fadd half %1, %3
  <SNIP>
}

When FullFP16 is *not* supported, we don't make f16 a legal type, and we get
legalization for "free", i.e. nothing changes and everything works as before.
And also f16 argument passing/returning is handled.

When FullFP16 is supported, we do make f16 a legal type, and have 2 places that
we need to patch up: f16 argument passing and returning, which involves minor
tweaks to avoid unnecessary code generation for some bitcasts.

As a "demonstrator" that this works for the different FP16, FullFP16, softfp
modes, etc., I've added match rules to the VSUB instruction description showing
that we can codegen this instruction from IR, but more importantly, also to
some conversion instructions. These conversions were causing issue before in
the FP16 and FullFP16 cases.

I've also added match rules to the VLDRH and VSTRH desriptions, so that we can
actually compile the entire half-precision sub code example above. This showed
that these loads and stores had the wrong addressing mode specified: AddrMode5
instead of AddrMode5FP16, which turned out not be implemented at all, so that
has also been added.

This is the minimal patch that shows all the different moving parts. In patch
2/3 I will add some efficient lowering of bitcasts, and in 2/3 I will add the
remaining Armv8.2-A FP16 instruction descriptions.


Thanks to Sam Parker and Oliver Stannard for their help and reviews!


Differential Revision: https://reviews.llvm.org/D38315

llvm-svn: 323512
2018-01-26 09:26:40 +00:00
Sam McCall 1b475a1ad0 [clangd] Modify the Span API so that Spans propagate with contexts.
Summary:
This is probably the right behavior for distributed tracers, and makes unpaired
begin-end events impossible without requiring Spans to be bound to a thread.

The API is conceptually clean but syntactically awkward. As discussed offline,
this is basically a naming problem and will go away if (when) we use TLS to
store the current context.

The apparently-unrelated change to onScopeExit are because its move semantics
broken if Func is POD-like since r322838. This is true of function pointers,
and the lambda I use here that captures two pointers only.
I've raised this issue on llvm-dev and will revert this part if we fix it in
some other way.

Reviewers: ilya-biryukov

Subscribers: klimek, jkorous-apple, ioeric, cfe-commits

Differential Revision: https://reviews.llvm.org/D42499

llvm-svn: 323511
2018-01-26 09:00:30 +00:00
Hiroshi Inoue d1a6646e59 [NFC] fix trivial typos in comments and documents
"in in" -> "in", "on on" -> "on" etc.

llvm-svn: 323510
2018-01-26 08:16:08 +00:00
Hiroshi Inoue ef04f64069 [NFC] fix trivial typos in comments and documents
"in in" -> "in", "on on" -> "on" etc.

llvm-svn: 323509
2018-01-26 08:15:52 +00:00
Hiroshi Inoue 0909ca132f [NFC] fix trivial typos in comments and documents
"in in" -> "in", "on on" -> "on" etc.

llvm-svn: 323508
2018-01-26 08:15:29 +00:00
Shiva Chen 056d835fa4 [RISCV] Encode RISCV specific ELF e_flags to RISCV Binary by RISCVTargetStreamer
llvm-svn: 323507
2018-01-26 07:53:07 +00:00
Craig Topper 882f0d7955 [X86] Remove dead code from LowerBUILD_VECTOR that tried to handle i64 element type in 32-bit mode.
Type legalization would prevent any i64 operands to the build_vector from existing before we get here. The coverage bots show this code as uncovered.

llvm-svn: 323506
2018-01-26 07:30:44 +00:00
Craig Topper b5c45e0509 [SelectionDAG] Replace a std::vector<SDValue> with a SmallVector.
It likely the number of elements in the type we're legalizing here is reasonably small.

llvm-svn: 323505
2018-01-26 07:15:22 +00:00
Craig Topper 77c5077585 [X86] Remove code from combineBitcastvxi1 that was needed to support the previous native IR for kunpck intrinsics.
The original autoupgrade for kunpck intrinsics used a bitcasted scalar shift, or, and. This combine would turn this into a concat_vectors. Now the kunpck intrinsics are autoupgraded to a vector shuffle that will become a concat_vectors.

llvm-svn: 323504
2018-01-26 07:15:21 +00:00
Craig Topper 95e8c9143e [X86] Remove unused intrinsic type handling. NFC
llvm-svn: 323503
2018-01-26 07:15:20 +00:00
Craig Topper ccb35dfda6 [X86] Simplify condition in VSETCC. NFC
This listed all legal 128-bit integer types individually, but since we already know we have a legal type and its integer, we can just check is128BitVector.

llvm-svn: 323502
2018-01-26 07:15:18 +00:00
Craig Topper faa56f7b08 [X86] Remove LowerVSETCC code for handling vXi1 setcc with vXi8/vXi16 input type. NFC
These kinds of setccs are promoted by a DAG combine before they ever get to legalization.

llvm-svn: 323501
2018-01-26 07:15:17 +00:00
Craig Topper ad8ce0b800 [X86] Remove some dead code from LowerVSETCC. NFC
This code was added in r321967, but ultimately I fixed the issue in the legalizer and this code was no longer required.

llvm-svn: 323500
2018-01-26 07:15:16 +00:00
Martin Storsjo 25a37a894e Don't enable _LIBUNWIND_BUILD_ZERO_COST_APIS if building the SJLJ APIs
Otherwise, a shared library build with SJLJ APIs enabled would
end up with duplicate symbols.

This didn't occur for the apple && arm case due to specifically
checking for that in the surrounding ifdef.

Differential Revision: https://reviews.llvm.org/D42555

llvm-svn: 323499
2018-01-26 06:50:07 +00:00
Serguei Katkov 9fe0524ee6 [CGP] Re-enable Select in complex addressing mode.
Switch Select handling on after fixing two bugs: rL323192 and rL323497.

llvm-svn: 323498
2018-01-26 06:26:56 +00:00
Serguei Katkov 1ce7137c99 [X86] Fix killed flag handling in X86FixupLea pass
When pass creates a MOV instruction for 
lea (%base,%index,1), %dst => mov %base,%dst; add %index,%dst
modification it should clean the killed flag for base
if base is equal to index.

Otherwise verifier complains about usage of killed register in add instruction.

Reviewers: lsaba, zvi, zansari, aaboud
Reviewed By: lsaba
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D42522

llvm-svn: 323497
2018-01-26 04:49:26 +00:00
Don Hinton 3a667b9bd8 [cmake] [libunwind] Call llvm_setup_rpath() when adding shared libraries.
Clang and llvm already use llvm_setup_rpath(), so this change will
help standarize rpath usage across all projects.

Differential Revision: https://reviews.llvm.org/D42461

llvm-svn: 323496
2018-01-26 04:01:50 +00:00
Don Hinton e3b3b8094d Reland:
[cmake] [libcxxabi] Call llvm_setup_rpath() when adding shared libraries.

Clang and llvm already use llvm_setup_rpath(), so this change will
help standarize rpath usage across all projects.

Differential Revision: https://reviews.llvm.org/D42460

llvm-svn: 323495
2018-01-26 03:41:58 +00:00
Jake Ehrlich 9634e18ffe Reland "[llvm-objcopy] Refactor llvm-objcopy to use reader and writer objects"
Somehow I reverted changes I made in a previous Reland. This change re-relands
unconfusing a varible name with a type name.

llvm-svn: 323494
2018-01-26 02:01:37 +00:00
Jake Ehrlich 41d9d7b16f Reland "[llvm-objcopy] Refactor llvm-objcopy to use reader and writer objects"
I had more unused varibles. This change removes those to get rid of warnings.

llvm-svn: 323493
2018-01-26 01:48:12 +00:00
Don Hinton d21aeffc86 Reland: [cmake] [libcxx] Call llvm_setup_rpath() when adding shared libraries.
Clang and llvm already use llvm_setup_rpath(), so this change will
help standarize rpath usage across all projects.

Differential Revision: https://reviews.llvm.org/D42459

llvm-svn: 323492
2018-01-26 01:34:51 +00:00
Peter Collingbourne 1634c15e3c libcxx: Use vcruntime declarations for typeinfo on Windows.
We need to use the vcruntime declarations on Windows to avoid an
ODR violation involving rtti.obj, which provides the definition of
the runtime function implementing dynamic_cast and depends on the
vcruntime implementations of bad_cast and bad_typeid.

Differential Revision: https://reviews.llvm.org/D42220

llvm-svn: 323491
2018-01-26 01:22:17 +00:00
Peter Collingbourne 0aa71a4f86 libcxx: Move #include_next <math.h> out of header guard in wrapper header.
Code on Windows expects to be able to do:

 #define _USE_MATH_DEFINES
 #include <math.h>

and receive the definitions of mathematical constants, even if <math.h>
has previously been included. To support this scenario, re-include
<math.h> every time the wrapper header is included.

Differential Revision: https://reviews.llvm.org/D42403

llvm-svn: 323490
2018-01-26 01:19:23 +00:00
Jake Ehrlich c0e9bee781 Reland "[llvm-objcopy] Refactor llvm-objcopy to use reader and writer objects"
Added line to output the proper files in the output to binary case.

llvm-svn: 323489
2018-01-26 01:17:35 +00:00
Rui Ueyama e1c19c4c6e Rename a test file.
A test for option /foo is usually named foo.test, but this test
file is not for the /order option, so rename it to avoid confusion.

llvm-svn: 323488
2018-01-26 01:01:21 +00:00
Aditya Nandakumar db8d709c5a Fix buildfailure by making some MIPatternMatchers inline
llvm-svn: 323487
2018-01-26 00:50:56 +00:00
Jake Ehrlich 82d61211b2 Revert "Reland "[llvm-objcopy] Refactor llvm-objcopy to use reader and writer objects""
Tests were working on my system because the old correct files were left over
and the new bug was that the output files were not being output at all.
Consequently the test work on my system but fail on any other system.

This reverts commit r323484.

llvm-svn: 323486
2018-01-26 00:38:30 +00:00
Amara Emerson 4ee9f82a95 [Driver] Add an -fexperimental-isel driver option to enable/disable GlobalISel.
Differential Revision: https://reviews.llvm.org/D42276

llvm-svn: 323485
2018-01-26 00:27:22 +00:00
Jake Ehrlich 6d88ffd256 Reland "[llvm-objcopy] Refactor llvm-objcopy to use reader and writer objects"
I named a varible the same as a type which caused a warning. I also had unamed varibles.

llvm-svn: 323484
2018-01-26 00:19:30 +00:00
Shoaib Meenai d8fd16b08f [CodeGen] Ignore private symbols in llvm.used for COFF
Similar to the existing handling for internal symbols, private symbols
are also not visible to the linker and should be ignored.

llvm-svn: 323483
2018-01-26 00:15:25 +00:00