Commit Graph

357031 Commits

Author SHA1 Message Date
Sanjay Patel 039ff29ef6 [VectorCombine] remove unused parameters; NFC 2020-06-11 19:15:03 -04:00
Vitaly Buka a10fc165f5 [StackSafety,NFC] Fix use of CallBase API
Code does not need iterate arguments and can get ArgNo from
CallBase::getArgOperandNo.
2020-06-11 16:11:30 -07:00
Matt Arsenault 27f8bd94cb AMDGPU/GlobalISel: Fix select of <8 x s64> scalar load 2020-06-11 19:09:43 -04:00
Akira Hatanaka c9a52de002 [CodeGen] Simplify the way lifetime of block captures is extended
Rather than pushing inactive cleanups for the block captures at the
entry of a full expression and activating them during the creation of
the block literal, just call pushLifetimeExtendedDestroy to ensure the
cleanups are popped at the end of the scope enclosing the block
expression.

rdar://problem/63996471

Differential Revision: https://reviews.llvm.org/D81624
2020-06-11 16:06:22 -07:00
Jonas Devlieghere 8d8ec55035 [lldb/Test] Unify DYLD_INSERT_LIBRARIES solution for ASan and TSan
Add the same fix for loading the sanitizer runtime for TSan as we
currently have for ASan and unify the code with a helper function.
2020-06-11 16:04:46 -07:00
Matt Arsenault 2247072b65 AMDGPU/GlobalISel: Set insert point when emitting control flow pseudos
This was implicitly assuming the branch instruction was the next after
the pseudo. It's possible for another non-terminator instruction to be
inserted between the intrinsic and the branch, so adjust the insertion
point. Fixes a non-terminator after terminator verifier error (which
without the verifier, manifested itself as an infinite loop in
analyzeBranch much later on).
2020-06-11 18:53:26 -04:00
George Mitenkov fc148a4c88 [MLIR][SPIRVToLLVM] Added conversion for SPIR-V comparison ops
Implemented `FComparePattern` and `IComparePattern` classes
that provide conversion of SPIR-V comparison ops (such as
`spv.FOrdGreaterThanEqual` and others) to LLVM dialect.
Also added tests in `comparison-ops-to-llvm.mlir`.

Differential Revision: https://reviews.llvm.org/D81487
2020-06-11 18:46:17 -04:00
Kirill Naumov 1022b5eb5b [InlineCost] Preparational patch for creation of Printer pass.
- Renaming the printer class, flag
- Refactoring
- Changing some tests

This patch is a preparational stage for introducing a new printing pass and new
functionality to the existing Annotation Writer. I plan to extend
this functionality for this tool to be more useful when looking at the inline
process.
2020-06-11 22:29:03 +00:00
Fangrui Song 030897523d [Support] Don't tie errs() to outs() by default
This reverts part of D81156.

Accessing errs() concurrently was safe before and racy after D81156.
(`errs() << 'a'` is always racy)

Accessing outs() and errs() concurrently was safe before and racy after D81156.

Don't tie errs() to outs() by default to fix the fallout.
llvm-dwarfdump is single-threaded and opting in the tie behavior is safe.
2020-06-11 15:19:56 -07:00
John McCall 7fac1acc61 Set the LLVM FP optimization flags conservatively.
Functions can have local pragmas that override the global settings.
We set the flags eagerly based on global settings, but if we emit
an expression under the influence of a pragma, we clear the
appropriate flags from the function.

In order to avoid doing a ton of redundant work whenever we emit
an FP expression, configure the IRBuilder to default to global
settings, and only reconfigure it when we see an FP expression
that's not using the global settings.

Patch by Michele Scandale!

https://reviews.llvm.org/D80462
2020-06-11 18:16:41 -04:00
Stanislav Mekhanoshin a98d618f6e Fixed assertion in SROA if block has ho successors
BasicBlock::isLegalToHoistInto() asserts if block does not
have successors. The case is degenarate but assertion still
needs to be avoided.

https://bugs.llvm.org/show_bug.cgi?id=46280

Differential Revision: https://reviews.llvm.org/D81674
2020-06-11 15:15:19 -07:00
Craig Topper c525168190 [X86] Remove unnecessary #if around call to isCpuIdSupported in getHostCPUName.
The exact same #if is already inside isCpuIdSupported and causes
it to return true. The definition of isCpuIdSupported isn't
conditional so we should be able just rely on its body doing
the right thing.
2020-06-11 15:13:28 -07:00
Thomas Lively c5d012341e [WebAssembly] Make BR_TABLE non-duplicable
Summary:
After their range checks were removed in 7f50c15be5, br_tables
started being duplicated into their predecessors by tail
folding. Unfortunately, when the br_tables were in loops this
transformation introduced bad irreducible control flow which was later
expanded into even more br_tables. This commit abuses the
`isNotDuplicable` property to prevent this irreducible control flow
from being introduced. This change saves a few dozen bytes of code
size and has a negligible affect on performance for most of the large
Emscripten benchmarks, but can improve performance significantly on
microbenchmarks of switches in loops.

Reviewers: aheejin, dschuff

Subscribers: sbc100, jgravelle-google, hiraditya, sunfish, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D81628
2020-06-11 15:11:45 -07:00
Ilya Bukonkin 3b43f00629 [lldb] Check if thread was suspended during previous stop added.
Encountered the following situation: Let we started thread T1 and it hit
breakpoint on B1 location. We suspended T1 and continued the process.
Then we started thread T2 which hit for example the same location B1.
This time in a breakpoint callback we decided not to stop returning
false.

Expected result: process continues (as if T2 did not hit breakpoint) its
workflow with T1 still suspended. Actual result: process do stops (as if
T2 callback returned true).

Solution: We need invalidate StopInfo for threads that was previously
suspended just because something that is already inactive can not be the
reason of stop. Thread::GetPrivateStopInfo() may be appropriate place to
do it, because it gets called (through Thread::GetStopInfo()) every time
before process reports stop and user gets chance to change
m_resume_state again i.e if we see m_resume_state == eStateSuspended
it definitely means it was set during previous stop and it also means
this thread can not be stopped again (cos' it was frozen during
previous stop).

Differential revision: https://reviews.llvm.org/D80112
2020-06-11 15:02:46 -07:00
Diego Caballero 2e7a084591 [mlir][Affine] Revisit fusion candidates after successful fusion
This patch changes the fusion algorithm so that after fusing two loop nests
we revisit previously visited nodes so that they are considered again for
fusion in the context of the new fused loop nest.

Reviewed By: bondhugula

Differential Revision: https://reviews.llvm.org/D81609
2020-06-11 14:53:08 -07:00
Reid Kleckner 1c03389c29 Re-land "Migrate the rest of COFFObjectFile to Error"
This reverts commit 101fbc0138.

Remove leftover debugging attribute.

Update LLDB as well, which was missed before.
2020-06-11 14:46:16 -07:00
Kadir Cetinkaya f44d2424f8
[clangd] Set CWD in semaCodeComplete
Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, usaxena95, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D81691
2020-06-11 23:35:47 +02:00
Alex Richardson 385e5f7e14 Fix incorrect call to ExprResult::get()
Res is already a ExprResult, so if we call .get(), we will convert an
ExprError() result into an unset result. I discovered this in our downstream
CHERI target where this resulted in a crash due to a NULL-dereference.
It appears that this was introduced in SVN revision 201788 (8690a6860a)

Reviewed By: Anastasia
Differential Revision: https://reviews.llvm.org/D81608
2020-06-11 22:23:33 +01:00
Fangrui Song 432f20bc18 [GlobalISel][test] Add REQUIRES: asserts after D76934 2020-06-11 13:50:56 -07:00
Jacques Pienaar 7f13d51ee3 [mlir] Remove Broadcastable ODS trait
Alias to ResultsBroadcastableShape ODS trait which matches C++ class.
2020-06-11 13:45:09 -07:00
Louis Dionne 96e6cbbf94 [libc++] Allow specifying arbitrary custom executors with the new format
The integration between CMake and executor selection in the new format
wasn't very flexible -- only the default executor and SSH executors were
supported.

This patch makes it possible to specify arbitrary executors with the new
format. With the new testing format, a custom executor is just a script
that gets called with a command-line to execute, and some arguments like
--env, --codesign_identity and --execdir. As such, the default executor
is just run.py.

Remote execution with the SSH executor can be achived by specifying
LIBCXX_EXECUTOR="<path-to-ssh.py> --host <host>". Similarly, arbitrary
scripts can be provided.
2020-06-11 16:24:29 -04:00
Alexander Belyaev e9ac792748 [mlir] Fix some of the warnings in MLIR code.
Summary:
* extra ';' in the following files:
    mlir/lib/Dialect/Linalg/Transforms/Transforms.cpp
    mlir/lib/Dialect/Shape/IR/Shape.cpp

* base class ‘mlir::ConvertVectorToSCFBase<ConvertVectorToSCFPass>’
  should be explicitly initialized in the copy constructor [-Wextra] in
    mlir/lib/Conversion/VectorToSCF/VectorToSCF.cpp

* warning: ‘bool Expression::operator==(const Expression&) const’
  defined but not used [-Wunused-function] in
    mlir/tools/mlir-linalg-ods-gen/mlir-linalg-ods-gen.cpp

Differential Revision: https://reviews.llvm.org/D81673
2020-06-11 22:18:32 +02:00
Craig Topper 8fa3e8fa14 [X86] Force VIA PadLock crypto instructions to emit a 0xF3 prefix when they encode to match what GNU as does.
The spec for these says they need 0xf3 but also mentions REP
before the mnemonic. But I don't think its fair to users to make
them write REP first. And gas doesn't make them. objdump seems to
disassemble with or without the prefix and just prints any 0xf3
as REP.
2020-06-11 12:59:21 -07:00
Aditya Nandakumar 6239d67001 [GISel][NFC]: Add unit test for clarifying CSE behavior
Add a unit test that shows how CSE works if we install an observer
at the machine function level and not use the CSEMIRBuilder to build
instructions.

https://reviews.llvm.org/D81625
2020-06-11 12:49:41 -07:00
Erich Keane c08ea07716 Add to the Coding Standard our that single-line bodies omit braces
This is a rule that seems to have been enforced for the better part of
the decade, so we should document it for new contributors.

Differential Revision: https://reviews.llvm.org/D80947
2020-06-11 12:46:15 -07:00
Bruno Ricci a9250c281a
[clang] TextNodeDumper: Dump the trait spelling of {Type,ArrayType,Expression}TraitExpr
nodes using the new helper functions introduced
in 78e636b3f2.
2020-06-11 20:27:40 +01:00
Bruno Ricci efb0413a5c
[clang][NFC] Assert that the enumerator value of {Type,ArrayType,UnaryExprOrType,Expression}Traits
is valid and does not overflow in the bit-field for its storage in more places.
This is a follow-up to 78e636b3f2. NFC.
2020-06-11 20:27:40 +01:00
Bruno Ricci a06f000326
[clang][NFC] Remove two hard-coded lists of ArrayTypeTrait and ExpressionTrait
These two were missed in 78e636b3f2.
2020-06-11 20:27:40 +01:00
Siva Chandra Reddy 118c13c691 [libc] Add implementation of few floating point manipulation functions.
Implementations of copysign[f], frexp[f], logb[f], and modf[f] are added.

Reviewers: asteinhauser

Differential Revision: https://reviews.llvm.org/D81134
2020-06-11 12:23:11 -07:00
Craig Topper 269d843720 [X86] Replace TB with PS on instructions that are documented in the SDM with 'NP'
'NP' means that the instruction is not recognized with a 66, F2 or F3
prefix. It will either #UD or decode to a different instruction.

All of the cases are here should fall into the #UD variety since
we should be detecting the collision with other instructions when
we build the disassembler tables.
2020-06-11 12:20:29 -07:00
Eli Friedman 12459ec926 [AArch64] Regenerate SVE test llvm-ir-to-intrinsic.ll. 2020-06-11 12:14:24 -07:00
Louis Dionne e619e9d5f5 [libc++abi] Simplify the logic for finding libc++ from libc++abi
Since we have the monorepo, libc++abi's build requires a sibling checkout
of the libc++ sources. Hence, the logic for finding libc++ can be greatly
simplified.
2020-06-11 15:08:01 -04:00
Alexey Bataev 43101d10db [OPENMP50]Codegen for scan directive in simd loops.
Added codegen for scan directives in simd loop. The codegen transforms
original code:
```
int x = 0;
 #pragma omp simd reduction(inscan, +: x)
for (..) {
  <first part>
  #pragma omp scan inclusive(x)
  <second part>
}
```
into
```
int x = 0;
for (..) {
  int x_priv = 0;
  <first part>
  x = x_priv + x;
  x_priv = x;
  <second part>
}
```
and
```
int x = 0;
 #pragma omp simd reduction(inscan, +: x)
for (..) {
  <first part>
  #pragma omp scan exclusive(x)
  <second part>
}
```
into
```
int x = 0;
for (..) {
  int x_priv = 0;
  <second part>
  int temp = x;
  x = x_priv + x;
  x_priv = temp;
  <first part>
}
```

Differential revision: https://reviews.llvm.org/D78232
2020-06-11 14:48:43 -04:00
sameeran joshi 70ad73b6b7 [flang] Semantics for SELECT TYPE
Summary:
    Added support for all semantic checks except C1157
    was previously implemented.

    Address review comments.

    Reviewers: PeteSteinfeld, tskeith, klausler, DavidTruby, kiranktp, anchu-rajendran, sscalpone

    Subscribers: kiranchandramohan, llvm-commits, flang-commits

    Tags: #llvm, #flang

    Differential Revision: https://reviews.llvm.org/D79851
2020-06-12 00:12:24 +05:30
Leonard Chan 71568a9e28 [clang] Frontend components for the relative vtables ABI (round 2)
This patch contains all of the clang changes from D72959.

- Generalize the relative vtables ABI such that it can be used by other targets.
- Add an enum VTableComponentLayout which controls whether components in the
  vtable should be pointers to other structs or relative offsets to those structs.
  Other ABIs can change this enum to restructure how components in the vtable
  are laid out/accessed.
- Add methods to ConstantInitBuilder for inserting relative offsets to a
  specified position in the aggregate being constructed.
- Fix failing tests under new PM and ASan and MSan issues.

See D72959 for background info.

Differential Revision: https://reviews.llvm.org/D77592
2020-06-11 11:17:08 -07:00
Stanislav Mekhanoshin 59491b208f Regenerated SROA phi-gep.ll test. NFC. 2020-06-11 10:51:06 -07:00
hyd-dev 95d7ccb70b [PCH] Support writing BuiltinBitCastExprs to PCHs
eee944e7f adds the new BuiltinBitCastExpr, but does not set the Code member of
ASTStmtWriter. This is not correct and causes an assertion failue in
ASTStmtWriter::emit() when building PCHs that contain __builtin_bit_cast.  This
commit adds serialization::EXPR_BUILTIN_BIT_CAST and handles
ASTStmtWriter::Code properly.

Differential revision: https://reviews.llvm.org/D80360
2020-06-11 13:37:01 -04:00
jerryyin eedd8fe62e [mlir][rocdl] Fixing breakage of dim operator from 904f91db
Summary:
* Update the unit test dimOp index to be an operand
* Refactored the constant naming

Subscribers: mehdi_amini, rriddle, jpienaar, shauheen, antiagainst, nicolasvasilache, csigg, arpith-jacob, mgester, lucyrfox, liufengdb, stephenneuendorffer, Joonsoo, grosul1, frgossen, Kayjukh, jurahul, msifontes

Tags: #mlir

Differential Revision: https://reviews.llvm.org/D81663
2020-06-11 17:35:22 +00:00
diggerlin c6be3ea524 [NFC] clean up the AsmPrinter::emitLinkage for AIX part
SUMMARY:

Since we deal with aix emitLinkage in the PPCAIXAsmPrinter::emitLinkage() in the patch https://reviews.llvm.org/D75866. It do not go to AsmPrinter::emitLinkage() any more, we clean up some aix related code in the AsmPrinter::emitLinkage()

Reviewers:  Jason liu

Differential Revision: https://reviews.llvm.org/D81613
2020-06-11 13:33:51 -04:00
Jonas Devlieghere 5a33ba52b6 [lldb/Test] Ensure inline tests have a unique build directory
Inline tests have one method named 'test' which means that multiple
inline tests in the same file end up sharing the same build directory
per variant.

This patch overrides the getBuildDirBasename method for the InlineTest
class to include the test name.

Differential revision: https://reviews.llvm.org/D81516
2020-06-11 09:36:54 -07:00
Alexander Belyaev 4e19ba4159 [mlir][shape] Add assemblyFormat for `shape.add`.
Differential Revision: https://reviews.llvm.org/D81644
2020-06-11 18:35:05 +02:00
Sanjay Patel d386297c67 [VectorCombine] add tests for compare scalarization; NFC 2020-06-11 12:29:00 -04:00
Petar Avramovic bd3d951b8b AMDGPU/GlobalISel: Fix lower for f64->f16 G_FPTRUNC
Put AND before ADD in LegalizerHelper::lowerFPTRUNC_F64_TO_F16
in order to match algorithm from AMDGPUTargetLowering::LowerFP_TO_FP16.

Differential Revision: https://reviews.llvm.org/D81666
2020-06-11 18:19:27 +02:00
Fangrui Song 5ee571735d [llvm-objdump] Decrease instruction indentation for non-x86
Place the instruction at the 24th column (0-based indexing), matching
GNU objdump ARM/AArch64/powerpc/etc when the address is low.

This is beneficial for non-x86 targets which have short instruction
lengths.

```
// GNU objdump AArch64
   0:   91001062        add     x2, x3, #0x4
  400078:       91001062        add     x2, x3, #0x4
// llvm-objdump, with this patch
       0: 62 10 00 91   add     x2, x3, #4
  400078: 62 10 00 91   add     x2, x3, #4
// llvm-objdump, if we change to print a word instead of bytes in the future
       0: 91001062      add     x2, x3, #4
  400078: 91001062      add     x2, x3, #4

// GNU objdump Thumb
   0:   bf00            nop

// GNU objdump Power ISA 3.1 64-bit instruction
// 0:   00 00 10 04     plwa    r3,0
// 4:   00 00 60 a4
```

Reviewed By: jhenderson

Differential Revision: https://reviews.llvm.org/D81590
2020-06-11 09:10:50 -07:00
Alexey Bataev fac7259c81 Revert "[OPENMP50]Codegen for scan directive in simd loops."
This reverts commit fb80e67f10 to resolve
the issue with asan buildbots.
2020-06-11 11:22:51 -04:00
Mircea Trofin e82eff7a03 [llvm][NFC] Factor some common data in InlineAdvice
Summary:
Other derivations will all want to emit optimization remarks and, as
part of that, use debug info.

Additionally, drive-by const-ing.

Reviewers: davidxl, dblaikie

Subscribers: aprantl, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D81507
2020-06-11 08:01:00 -07:00
Simon Pilgrim 7706c7af74 [X86] Fold vXi1 OR(KSHIFTL(X,NumElts/2),Y) -> KUNPCK
Convert shift+or bool vector patterns into CONCAT_VECTORS if we know this will be lowered to KUNPCK (which requires 16+ vector elements).

Fixes PR32547
2020-06-11 15:47:20 +01:00
jerryyin 2abad3433f [mlir][rocdl] Adding vector to ROCDL dialect lowering
* Created the vector to ROCDL lowering pass
  * The lowering pass lowers vector transferOps to rocdl mubufOps
* Added unit test and functional test
2020-06-11 14:28:13 +00:00
serge-sans-paille bff09876d7 Fix return status of DataFlowSanitizer pass
Take into account added functions, global values and attribute change.

Differential Revision: https://reviews.llvm.org/D81239
2020-06-11 16:05:17 +02:00
Alexey Bataev 90b54fa045 [OPENMP50]Codegen for use_device_addr clauses.
Summary:
Added codegen for use_device_addr clause. The components of the list
items are mapped as a kind of RETURN components and then the returned
base address is used instead of the real address of the base declaration
used in the use_device_addr expressions.

Reviewers: jdoerfert

Subscribers: yaxunl, guansong, sstefan1, cfe-commits, caomhin

Tags: #clang

Differential Revision: https://reviews.llvm.org/D80730
2020-06-11 09:54:51 -04:00