Commit Graph

364077 Commits

Author SHA1 Message Date
Matt Arsenault ff5758fec8 AMDGPU/GlobalISel: Add some bitcast tests 2020-08-19 10:38:39 -04:00
madhur13490 0313c540c2 [NFC] Fix typo in AMDGPU doc
Reviewed By: t-tye, arsenm

Differential Revision: https://reviews.llvm.org/D86206
2020-08-19 14:33:26 +00:00
Matt Arsenault 386a5ea2b7 AMDGPU/GlobalISel: Add selection tests for pointer constants 2020-08-19 10:23:56 -04:00
Benjamin Kramer b98e25b6d7 Make helpers static. NFC. 2020-08-19 16:00:03 +02:00
Roman Lebedev 3d76a133c7
Revert "[InstCombine] Lower infinite combine loop detection thresholds"
And as being reported by Florian Hahn, there's a hit
in MultiSource/Benchmarks/mafft from the test-suite on X86 with -O3 -flto,
so reverting until addressed.

This reverts commit 71e0b82c9f.
2020-08-19 16:53:30 +03:00
Simon Pilgrim 90a1e6509f Fix MSVC implicit truncation narrowing conversion warning. 2020-08-19 14:41:40 +01:00
Simon Pilgrim 057bdd63a4 [X86][AVX] lowerShuffleWithVPMOV - minor refactor to more closely match lowerShuffleAsVTRUNC
Replace isBuildVectorAllZeros check by using the Zeroable bitmask instead.
2020-08-19 14:34:32 +01:00
Simon Pilgrim 1014a93a4e Fix unused variable warnings. NFCI. 2020-08-19 14:34:32 +01:00
Aaron Puchert 916b750a8d [CodeGen] Use existing EmitLambdaVLACapture (NFC) 2020-08-19 15:20:05 +02:00
Xing GUO 419326a445 [obj2yaml] Refactor the .debug_pub* sections dumper.
It's good to reuse the DWARF parser in lib/DebugInfo so that we don't
need to maintain a separate parser in client side (obj2yaml). Besides,
A test case is added whose length field is a very huge value which makes
obj2yaml stuck when parsing the section.

Reviewed By: jhenderson

Differential Revision: https://reviews.llvm.org/D86192
2020-08-19 21:13:52 +08:00
Pavel Labath 9cc2f13dee [lldb] Clean up DW_AT_declaration-with-children.s test
Address some post-commit feedback on D85968.
2020-08-19 14:58:50 +02:00
Pavel Labath d7363397c6 [lldb] Add typedefs to the DeclContext they are created in
TypeSystemClang::CreateTypedef was creating a typedef in the right
DeclContext, but it was not actually adding it as a child of the
context. The resulting inconsistent state meant that we would be unable
to reference the typedef from an expression directly, but we could use
them if they end up being pulled in by some previous subexpression
(because the ASTImporter will set up the correct links in the expression
ast).

This patch adds the typedef to the decl context it is created in.

Differential Revision: https://reviews.llvm.org/D86140
2020-08-19 14:57:43 +02:00
Simon Pilgrim 9fee2bad6d [X86] lowerShuffleWithVPMOV - remove unnecessary shuffle commutation. NFCI.
canonicalizeShuffleMaskWithCommute should have already ensured the lower elements are from V1, we do have test coverage for this already.
2020-08-19 13:28:59 +01:00
Simon Pilgrim b61cef3a92 [X86][AVX] getAVX512TruncNode - don't truncate from illegal vector widths.
Thanks to @fhahn for the test case.
2020-08-19 13:00:26 +01:00
Sanjay Patel 92bcd240f2 [InstCombine] update stale comments in test files; NFC
I missed updating these with:
rG23bd33c6acc4
2020-08-19 07:42:06 -04:00
Roman Lebedev 71e0b82c9f
[InstCombine] Lower infinite combine loop detection thresholds
It's been a month since 2f3862eb9f,
and no new bug reports about the threshold were filled,
so let's bump it again and wait again.
2020-08-19 14:37:57 +03:00
Raphael Isemann c1b1868f35 [lldb] Make error messages in TestQueues more helpfull 2020-08-19 13:30:31 +02:00
David Green 41495dd57a [ARM] Change target triple to arm-none-none-eabi. NFC 2020-08-19 11:58:50 +01:00
Muhammad Omair Javaid bd791e97f8 [LLDB] Minor fix in TestSVERegisters.py for AArch64/Linux buildbot
This adds a minor test case fix to previously submitted AArch64 SVE
ptrace support. This was failing on LLDB/AArch64 Linux buildbot.

Differential Revision: https://reviews.llvm.org/D79699
2020-08-19 15:47:59 +05:00
Simon Pilgrim 80a0dc59b7 [X86][AVX] computeKnownBitsForTargetNode - add VTRUNC/VTRUNCS/VTRUNCUS known zero upper elements handling.
Like many of the AVX512 conversion ops, the VTRUNC ops guarantee the upper destination elements are zero.
2020-08-19 11:39:27 +01:00
Paul Walker 08ba4f112d [SVE] Add tests for fixed length vector integer operations with immediate operands. 2020-08-19 11:12:03 +01:00
Muhammad Omair Javaid 567ba6c468 [LLDB] Add ptrace register access for AArch64 SVE registers
This patch adds NativeRegisterContext_arm64 ptrace routines to access
AArch64 SVE register set. This patch also adds a test-case to test
AArch64 SVE register access and dynamic size configuration capability.

Reviewed By: labath

Differential Revision: https://reviews.llvm.org/D79699
2020-08-19 15:11:01 +05:00
Simon Pilgrim 46fc9a0dfc [X86][AVX] Fold store(extract_element(vtrunc)) to truncated store
Add handling for storing the extracted lower (truncated bits) element from a X86ISD::VTRUNC node - this can be lowered to a generic truncated store directly.

Differential Revision: https://reviews.llvm.org/D86158
2020-08-19 11:10:20 +01:00
Sander de Smalen 0353848cc9 [Clang][SVE] NFC: Move info about ACLE types into separate function.
This function returns a struct `BuiltinVectorTypeInfo` that contains
the builtin vector's element type, element count and number of vectors
(used for vector tuples).

Reviewed By: c-rhodes

Differential Revision: https://reviews.llvm.org/D86100
2020-08-19 11:04:20 +01:00
Bjorn Pettersson 54105d635d [GlobalISel] Untabify InstructionSelectorImpl.h. NFC 2020-08-19 12:00:00 +02:00
sstefan1 b0b32e6490 [OpenMPOpt] ICV tracking for calls
Introduce two new AAs. AAICVTrackerFunctionReturned which checks if a
function can have a unique ICV value after it is finished, and
AAICVCallSiteReturned which checks AAICVTrackerFunctionReturned for a
call site. This enables us to check the value of a call and if it
changes the ICV. This also changes the approach in
`getReplacementValues()` to a worklist-based approach so we can explore
all relevant BBs.

Differential Revision: https://reviews.llvm.org/D85544
2020-08-19 11:43:12 +02:00
sstefan1 eedf18fc1f [IR] Intrinsics default attributes and opt-out flag
Intrinsic properties can now be set to default and applied to all
intrinsics. If the attributes are not needed, the user can opt-out by
setting the DisableDefaultAttributes flag to true.

Differential Revision: https://reviews.llvm.org/D70365
2020-08-19 10:50:46 +02:00
Meera Nakrani 545de56f87 [ARM] Enabled VMLAV and Add instructions to use VMLAVA
Used InstCombine to enable VMLAV and Add instructions to generate VMLAVA instead with tests.
2020-08-19 08:36:49 +00:00
luxufan 6c5039a10f [RISCV] add the assemble and disassemble support of Zvlsseg instructions
This implements the assemble and disassemble support of RISCV Vector
extension Zvlsseg instructions, base on the 0.9 spec version.

Reviewed  by HsiangKai

Differential Revision: https://reviews.llvm.org/D84416
2020-08-19 16:22:25 +08:00
Mauri Mustonen c78993955e [utils] Fix regexp in llvm/utils/extract_vplan.py to extract VPlans.
Regarding this bug in Bugzilla: https://bugs.llvm.org/show_bug.cgi?id=46451

I went ahead and fixed the regexp pattern and now Python script is able
to extract vplan graphs from the log files. Additionally some test for
this would be nice to have but I'm not sure are Python scripts tested
in LLVM and if so where they live.

Reviewed By: fhahn

Differential Revision: https://reviews.llvm.org/D86068
2020-08-19 08:57:12 +01:00
madhur13490 8351e80cd1 [GlobalISel] Don't skip adding predicate matcher
This patch fixes a bug which skipped
adding predicate matcher for a pattern in many cases.
For example, if predicate is Load and
its memoryVT is non-null then the loop
continues and never reaches to the end which
adds the predicate matcher. This patch moves the
matcher addition to the top of the loop
so that it gets added regardless of contextual checks
later in the loop.
Other way to fix this issue is to remove all "continue" statements
in checks and let the loop continue till end.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D83034
2020-08-19 07:54:14 +00:00
Florian Hahn 1a55fbceaa [DSE,MemorySSA] Use NumRedundantStores instead of NumNoopStores.
Legacy DSE uses NumRedundantStores, while MemorySSA DSE uses
NumNoopStores. We should just use the same counter.
2020-08-19 08:50:33 +01:00
Ronak Chauhan fdf71d486c Revert "[AMDGPU] Support disassembly for AMDGPU kernel descriptors"
This reverts commit cacfb02d28.

Reverting due to buildbot failures.
2020-08-19 13:12:29 +05:30
Martin Storsjö cb6cf18ff5 [clang] Remove stray semicolons, fixing GCC warnings. NFC. 2020-08-19 10:41:03 +03:00
Muhammad Omair Javaid af4f40c376 [LLDB] NativeThreadLinux invalidate register cache on stop
In our discussion D79699 SVE ptrace register access support we decide to
invalidate register context cached data on every stop instead of doing
at before Step/Resume.

InvalidateAllRegisters was added to facilitate flushing of SVE register
context configuration and cached register values. It now makes more
sense to move invalidation after every stop where we initiate SVE
configuration update if needed by calling ConfigureRegisterContext.

Reviewed By: labath

Differential Revision: https://reviews.llvm.org/D84501
2020-08-19 12:30:38 +05:00
Muhammad Omair Javaid 090306fc80 Convert SVE macros into c++ constants and inlines
This patch updates LLDB's in house version of SVE ptrace/sig macros by
converting them into constants and inlines. They are housed under sve
namespace and are used by process elf-core for reading SVE register data.

Reviewed By: labath

Differential Revision: https://reviews.llvm.org/D85641
2020-08-19 12:28:16 +05:00
Haojian Wu 5b797eb5b4 [AST] Fix a crash on mangling a binding decl from a DeclRefExpr.
Differential Revision: https://reviews.llvm.org/D86130
2020-08-19 09:05:12 +02:00
David Sherwood 3f36561f69 [SVE][CodeGen] Fix scalable vector issues in DAGTypeLegalizer::GenWidenVectorLoads
In DAGTypeLegalizer::GenWidenVectorLoads the algorithm assumes it only
ever deals with fixed width types, hence the offsets for each individual
store never take 'vscale' into account. I've changed the code in that
function to use TypeSize instead of unsigned for tracking the remaining
load amount. In addition, I've changed the load loop to use the new
IncrementPointer helper function for updating the addresses in each
iteration, since this handles scalable vector types.

Also, I've added report_fatal_errors in GenWidenVectorExtLoads,
TargetLowering::scalarizeVectorLoad and TargetLowering::scalarizeVectorStores,
since these functions currently use a sequence of element-by-element
scalar loads/stores. In a similar vein, I've also added a fatal error
report in FindMemType for the case when we decide to return the element
type for a scalable vector type.

I've added new tests in

  CodeGen/AArch64/sve-split-load.ll
  CodeGen/AArch64/sve-ld-addressing-mode-reg-imm.ll

for the changes in GenWidenVectorLoads.

Differential Revision: https://reviews.llvm.org/D85909
2020-08-19 07:54:32 +01:00
Craig Topper b32f203edc [X86][Driver] Remove code that forced a core2 mtune from MachO::TranslateArgs.
mtune was previously ignored by the compiler so I'm not sure this
did anything. But after D85384 we're starting to support mtune
and this code is now causing a couple test failures on MacOS.
2020-08-18 23:44:36 -07:00
Shinji Okumura 21e4b9b204 [Attributor][NFC] Add tests to range.ll
Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D86128
2020-08-19 15:01:14 +09:00
Yaxun (Sam) Liu a11ab6e04c Fix test hip-target-id.hip
Some build bot has lld in the directory name, which caused pattern match
issue in the list test.
2020-08-19 00:41:14 -04:00
LLVM GN Syncbot 9896546e8b [gn build] Port 7546b29e76 2020-08-19 03:44:19 +00:00
Yaxun (Sam) Liu 7546b29e76 [HIP] Support target id by --offload-arch
This patch introduces support of target id by
-offload-arch.

Differential Revision: https://reviews.llvm.org/D60620
2020-08-18 23:43:53 -04:00
Ronak Chauhan cacfb02d28 [AMDGPU] Support disassembly for AMDGPU kernel descriptors
Decode AMDGPU Kernel descriptors as assembler directives.

Reviewed By: scott.linder

Differential Revision: https://reviews.llvm.org/D80713
2020-08-19 08:49:07 +05:30
aartbik 451dcfae31 [mlir] [VectorOps] Cleanup mask 1-d test on constants
I forgot to address this in previous CL. Sorry about that.

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D86188
2020-08-18 19:39:17 -07:00
Julian Lettner 40ae296bc3 [TSan][libdispatch] Guard test execution on old platforms
`dispatch_async_and_wait()` was introduced in macOS 10.14.  Let's
forward declare it to ensure we can compile the test with older SDKs and
guard execution by checking if the symbol is available.  (We can't use
`__builtin_available()`, because that itself requires a higher minimum
deployment target.)  We also need to specify the `-undefined
dynamic_lookup` compiler flag.

Differential Revision: https://reviews.llvm.org/D85995
2020-08-18 18:34:14 -07:00
Julian Lettner 686fe293e6 [TSan][libdispatch] Ensure TSan dylib works on old systems
`dispatch_async_and_wait()` was introduced in macOS 10.14, which is
greater than our minimal deployment target.  We need to forward declare
it as a "weak import" to ensure we generate a weak reference so the TSan
dylib continues to work on older systems.  We cannot simply `#include
<dispatch.h>` or use the Darwin availability macros since this file is
multi-platform.

In addition, we want to prevent building these interceptors at all when
building with older SDKs because linking always fails.

Before:
```
➤ dyldinfo -bind ./lib/clang/12.0.0/lib/darwin/libclang_rt.tsan_osx_dynamic.dylib | grep dispatch_async_and_wait
__DATA  __interpose      0x000F5E68    pointer      0 libSystem        _dispatch_async_and_wait_f
```

After:
```
➤ dyldinfo -bind ./lib/clang/12.0.0/lib/darwin/libclang_rt.tsan_osx_dynamic.dylib | grep dispatch_async_and_wait
__DATA  __got            0x000EC0A8    pointer      0 libSystem        _dispatch_async_and_wait (weak import)
__DATA  __interpose      0x000F5E78    pointer      0 libSystem        _dispatch_async_and_wait (weak import)
```

This is a follow-up to D85854 and should fix:
https://reviews.llvm.org/D85854#2221529

Reviewed By: kubamracek

Differential Revision: https://reviews.llvm.org/D86103
2020-08-18 18:34:14 -07:00
Julian Lettner 0c4863a253 Reland "[TSan][libdispatch] Add interceptors for dispatch_async_and_wait()"
The linker errors caused by this revision have been addressed.

Add interceptors for `dispatch_async_and_wait[_f]()` which was added in
macOS 10.14.  This pair of functions is similar to `dispatch_sync()`,
but does not force a context switch of the queue onto the caller thread
when the queue is active (and hence is more efficient).  For TSan, we
can apply the same semantics as for `dispatch_sync()`.

From the header docs:
> Differences with dispatch_sync()
>
> When the runtime has brought up a thread to invoke the asynchronous
> workitems already submitted to the specified queue, that servicing
> thread will also be used to execute synchronous work submitted to the
> queue with dispatch_async_and_wait().
>
> However, if the runtime has not brought up a thread to service the
> specified queue (because it has no workitems enqueued, or only
> synchronous workitems), then dispatch_async_and_wait() will invoke the
> workitem on the calling thread, similar to the behaviour of functions
> in the dispatch_sync family.

Additional context:
> The guidance is to use `dispatch_async_and_wait()` instead of
> `dispatch_sync()` when it is necessary to mix async and sync calls on
> the same queue. `dispatch_async_and_wait()` does not guarantee
> execution on the caller thread which allows to reduce context switches
> when the target queue is active.
> https://gist.github.com/tclementdev/6af616354912b0347cdf6db159c37057

rdar://35757961

Reviewed By: kubamracek

Differential Revision: https://reviews.llvm.org/D85854
2020-08-18 18:34:14 -07:00
Mehdi Amini f9dc2b7079 Separate the Registration from Loading dialects in the Context
This changes the behavior of constructing MLIRContext to no longer load globally
registered dialects on construction. Instead Dialects are only loaded explicitly
on demand:
- the Parser is lazily loading Dialects in the context as it encounters them
during parsing. This is the only purpose for registering dialects and not load
them in the context.
- Passes are expected to declare the dialects they will create entity from
(Operations, Attributes, or Types), and the PassManager is loading Dialects into
the Context when starting a pipeline.

This changes simplifies the configuration of the registration: a compiler only
need to load the dialect for the IR it will emit, and the optimizer is
self-contained and load the required Dialects. For example in the Toy tutorial,
the compiler only needs to load the Toy dialect in the Context, all the others
(linalg, affine, std, LLVM, ...) are automatically loaded depending on the
optimization pipeline enabled.

To adjust to this change, stop using the existing dialect registration: the
global registry will be removed soon.

1) For passes, you need to override the method:

virtual void getDependentDialects(DialectRegistry &registry) const {}

and registery on the provided registry any dialect that this pass can produce.
Passes defined in TableGen can provide this list in the dependentDialects list
field.

2) For dialects, on construction you can register dependent dialects using the
provided MLIRContext: `context.getOrLoadDialect<DialectName>()`
This is useful if a dialect may canonicalize or have interfaces involving
another dialect.

3) For loading IR, dialect that can be in the input file must be explicitly
registered with the context. `MlirOptMain()` is taking an explicit registry for
this purpose. See how the standalone-opt.cpp example is setup:

  mlir::DialectRegistry registry;
  registry.insert<mlir::standalone::StandaloneDialect>();
  registry.insert<mlir::StandardOpsDialect>();

Only operations from these two dialects can be in the input file. To include all
of the dialects in MLIR Core, you can populate the registry this way:

  mlir::registerAllDialects(registry);

4) For `mlir-translate` callback, as well as frontend, Dialects can be loaded in
the context before emitting the IR: context.getOrLoadDialect<ToyDialect>()

Differential Revision: https://reviews.llvm.org/D85622
2020-08-19 01:19:03 +00:00
Mehdi Amini e75bc5c791 Revert "Separate the Registration from Loading dialects in the Context"
This reverts commit d14cf45735.
The build is broken with GCC-5.
2020-08-19 01:19:03 +00:00