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72 Commits

Author SHA1 Message Date
Dave Zarzycki 656e8515fc x86 -- add the XTEST instruction 
llvm-svn: 177888
 2013-03-25 18:59:43 +00:00
Hans Wennborg 5deecd9043 Fix typo in X86BaseInfo.h that I introduced in r157818. 
llvm-svn: 173798
 2013-01-29 14:05:57 +00:00
Michael Liao 73cffddb95 Add support of RTM from TSX extension 
- Add RTM code generation support throught 3 X86 intrinsics:
  xbegin()/xend() to start/end a transaction region, and xabort() to abort a
  tranaction region

llvm-svn: 167573
 2012-11-08 07:28:54 +00:00
Chandler Carruth 5c0997f066 Remove 'static' from inline functions defined in header files. 
There is a pretty staggering amount of this in LLVM's header files, this
is not all of the instances I'm afraid. These include all of the
functions that (in my build) are used by a non-static inline (or
external) function. Specifically, these issues were caught by the new
'-Winternal-linkage-in-inline' warning.

I'll try to just clean up the remainder of the clearly redundant "static
inline" cases on functions (not methods!) defined within headers if
I can do so in a reliable way.

There were even several cases of a missing 'inline' altogether, or my
personal favorite "static bool inline". Go figure. ;]

llvm-svn: 158800
 2012-06-20 08:39:33 +00:00
Hans Wennborg 09610f3e09 Better comments for TLS-related X86 MachineOperand flags. 
llvm-svn: 157920
 2012-06-04 09:55:36 +00:00
Hans Wennborg 789acfb63d Implement the local-dynamic TLS model for x86 (PR3985) 
This implements codegen support for accesses to thread-local variables
using the local-dynamic model, and adds a clean-up pass so that the base
address for the TLS block can be re-used between local-dynamic access on
an execution path.

llvm-svn: 157818
 2012-06-01 16:27:21 +00:00
Hans Wennborg f9d0e44b82 Implement initial-exec TLS model for 32-bit PIC x86 
This fixes a TODO from 2007 :) Previously, LLVM would emit the wrong
code here (see the update to test/CodeGen/X86/tls-pie.ll).

llvm-svn: 156611
 2012-05-11 10:11:01 +00:00
Pete Cooper f76b5fe5ab Copied all the VEX prefix encoding code from X86MCCodeEmitter to the x86 JIT emitter. Needs some major refactoring as these two code emitters are almost identical 
llvm-svn: 155810
 2012-04-30 03:56:44 +00:00
Craig Topper 66a3597a4a Add vmfunc instruction to X86 assembler and disassembler. 
llvm-svn: 150899
 2012-02-19 01:39:49 +00:00
Craig Topper ed7aa46366 Add X86 assembler and disassembler support for AMD SVM instructions. Original patch by Kay Tiong Khoo. Few tweaks by me for code density and to reduce replication. 
llvm-svn: 150873
 2012-02-18 08:19:49 +00:00
Anton Korobeynikov c6b4017ce2 Add support for implicit TLS model used with MS VC runtime. 
Patch by Kai Nacke!

llvm-svn: 150307
 2012-02-11 17:26:53 +00:00
Craig Topper 4ed7278ff4 Convert assert(0) to llvm_unreachable in X86 Target directory. 
llvm-svn: 149809
 2012-02-05 05:38:58 +00:00
Craig Topper cd93de93fa Separate the concept of having memory access in operand 4 from the concept of having the W bit set for XOP instructons. Removes ORing W-bits in the encoder and will similarly simplify the disassembler implementation. 
llvm-svn: 147366
 2011-12-30 04:48:54 +00:00
Jan Sjödin 6dd2488383 XOP encoding bits and logic. 
llvm-svn: 146397
 2011-12-12 19:12:26 +00:00
Bruno Cardoso Lopes 0f9a1f5e6c This patch contains support for encoding FMA4 instructions and 
tablegen patterns for scalar FMA4 operations and intrinsic. Also
add tests for vfmaddsd.

Patch by Jan Sjodin

llvm-svn: 145133
 2011-11-25 19:33:42 +00:00
Craig Topper 980d59832a Add X86 RORX instruction 
llvm-svn: 142741
 2011-10-23 07:34:00 +00:00
Craig Topper 96fa597828 Add X86 PEXTR and PDEP instructions. 
llvm-svn: 142141
 2011-10-16 16:50:08 +00:00
Craig Topper aea148c366 Add X86 BZHI instruction as well as BMI2 feature detection. 
llvm-svn: 142122
 2011-10-16 07:55:05 +00:00
Craig Topper 25ea4e5ad3 Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen 
llvm-svn: 142105
 2011-10-16 03:51:13 +00:00
Craig Topper 27ad12539d Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension. 
llvm-svn: 142082
 2011-10-15 20:46:47 +00:00
Craig Topper f18c896337 Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676. 
llvm-svn: 141065
 2011-10-04 06:30:42 +00:00
Evan Cheng 7e763d86ba Refactor X86 target to separate MC code from Target code. 
llvm-svn: 135930
 2011-07-25 18:43:53 +00:00