Summary: The changes introduced in the above two commits are giving
a rough time to one of the build bots. Reverting the changes for the
moment so that the bot can go green again.
Change-Id: Id19f6cb2a8bc292631fac2262268927563d820c2
llvm-svn: 218970
The Cortex-M7 has 3 options for its FPU: none, FPv5-SP-D16 and
FPv5-DP-D16. FPv5 has the same instructions as FP-ARMv8, so it can be
modeled using the same target feature, and all double-precision
operations are already disabled by the fp-only-sp target features.
llvm-svn: 218748
Added two new options for -mfpu when targetting ARM:
* fpv4-sp-d16
* fp4-sp-d16
The first is the same spelling as gcc.
The lack of a leading `v' is correct, this is consistent with ARM's
documentation and gcc's spelling of the option.
llvm-svn: 201846
Although we wire up a bit for v8fp for macro setting
purposes, we don't set a macro yet. Need to ask list
about that.
Change-Id: Ic9819593ce00882fbec72757ffccc6f0b18160a0
llvm-svn: 193367
- Support gcc-compatible vfpv3 name in addition to vfp3.
- Support vfpv3-d16.
- Disable neon feature for -mfpu=vfp* (yes, we were emitting Neon instructions
for those!).
llvm-svn: 147943
Asiri Rathnayake