dc49a8d3f1
Add Thumb2 lsr hooks.
...
llvm-svn: 79032
2009-08-14 20:09:37 +00:00
09c070f4ce
80 col violation.
...
llvm-svn: 79026
2009-08-14 19:11:20 +00:00
9a58aff837
Indentation.
...
llvm-svn: 79022
2009-08-14 19:01:37 +00:00
e41903b10d
Also shrink immediate branches; also more assembler workarounds.
...
llvm-svn: 79014
2009-08-14 18:31:44 +00:00
6f34e278c7
Now that all the legal Neon shuffles (or at least the ones that have been
...
implemented so far) are recognized during legalization, it is easy to fall
back to the default expansion for other shuffles.
llvm-svn: 78995
2009-08-14 05:16:33 +00:00
eb54d51759
Create a new ARM-specific DAG node, VDUP, to represent a splat from a
...
scalar_to_vector. Generate these VDUP nodes during legalization instead
of trying to recognize the pattern during selection.
llvm-svn: 78994
2009-08-14 05:13:08 +00:00
cce31f6831
During legalization, change Neon vdup_lane operations from shuffles to
...
target-specific VDUPLANE nodes. This allows the subreg handling for the
quad-register version to be done easily with Pats in the .td file, instead
of with custom code in ARMISelDAGToDAG.cpp.
llvm-svn: 78993
2009-08-14 05:08:32 +00:00
db73d68cbe
Shrink ADR and LDR from constantpool late during constantpool island pass.
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llvm-svn: 78970
2009-08-14 00:32:16 +00:00
76fa6e6a8f
New entry.
...
llvm-svn: 78968
2009-08-14 00:16:47 +00:00
55f1c09e31
Push LLVMContexts through the IntegerType APIs.
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llvm-svn: 78948
2009-08-13 21:58:54 +00:00
86c065dd68
Revert 78892 and 78895, these break generating working executables on
...
x86_64-apple-darwin10.
--- Reverse-merging r78895 into '.':
U test/CodeGen/PowerPC/2008-12-12-EH.ll
U lib/Target/DarwinTargetAsmInfo.cpp
--- Reverse-merging r78892 into '.':
U include/llvm/Target/DarwinTargetAsmInfo.h
U lib/Target/X86/X86TargetAsmInfo.cpp
U lib/Target/X86/X86TargetAsmInfo.h
U lib/Target/ARM/ARMTargetAsmInfo.h
U lib/Target/ARM/ARMTargetMachine.cpp
U lib/Target/ARM/ARMTargetAsmInfo.cpp
U lib/Target/PowerPC/PPCTargetAsmInfo.cpp
U lib/Target/PowerPC/PPCTargetAsmInfo.h
U lib/Target/PowerPC/PPCTargetMachine.cpp
G lib/Target/DarwinTargetAsmInfo.cpp
llvm-svn: 78919
2009-08-13 17:03:38 +00:00
eba70d85cf
Add missing defs of R2 and D1.
...
llvm-svn: 78918
2009-08-13 16:59:44 +00:00
a9c2aad939
Finalize itineraries for cortex-a8 integer multiply
...
llvm-svn: 78908
2009-08-13 15:51:13 +00:00
695e1c6087
Remove unnecessary newline
...
llvm-svn: 78905
2009-08-13 15:12:16 +00:00
c96e88f8a5
Correct comment wording
...
llvm-svn: 78904
2009-08-13 15:11:43 +00:00
f59e9f4288
tPOP_RET now has predicate operands.
...
llvm-svn: 78898
2009-08-13 06:05:07 +00:00
3e4c012d54
Add a fixme message about canonicalizing floating-point vector types.
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llvm-svn: 78897
2009-08-13 06:01:30 +00:00
ef6e602bf4
Revert r78852 for now. I want to do this differently, but I don't have time
...
to fix it tonight.
llvm-svn: 78896
2009-08-13 05:58:56 +00:00
e5801bd220
It's ok to spill a tGPR register as long as it's still allocated a low register.
...
llvm-svn: 78893
2009-08-13 05:40:51 +00:00
eb68198145
fix a minor fixme. When building with SL and later tools, the ".eh" symbols
...
don't need to be exported from the .o files.
llvm-svn: 78892
2009-08-13 05:30:22 +00:00
607cd3b63a
Change MCSectionELF to represent a section semantically instead of
...
syntactically as a string, very similiar to what Chris did with MachO.
The parsing support and validation is not introduced yet.
llvm-svn: 78890
2009-08-13 05:07:35 +00:00
c6800b55e6
Add a comment to describe why vector shuffles are legalized to custom DAG nodes.
...
llvm-svn: 78884
2009-08-13 02:13:04 +00:00
fcd6361ad1
Use cast<> instead of dyn_cast<> in places where the type is known.
...
llvm-svn: 78881
2009-08-13 01:57:47 +00:00
ef3d457126
Various AsmWriter output cleanups. Use WriteAsOperand instead of
...
PrintUnmangledNameSafely.
llvm-svn: 78878
2009-08-13 01:36:44 +00:00
ff2db10211
Recognize Neon VDUP shuffles during legalization instead of selection.
...
llvm-svn: 78852
2009-08-12 22:54:19 +00:00
ea3a402ae7
Recognize Neon VREV shuffles during legalization instead of selection.
...
llvm-svn: 78850
2009-08-12 22:31:50 +00:00
1432ef864e
This void is implicit in C++.
...
llvm-svn: 78848
2009-08-12 22:10:57 +00:00
4b35448360
Generate Neon VTBL and VTBX instructions from the corresponding intrinsics.
...
llvm-svn: 78835
2009-08-12 20:51:55 +00:00
aee7e49c50
PredCC is meant to be 2 bits wide, like PredCC1.
...
llvm-svn: 78829
2009-08-12 18:35:50 +00:00
b369ee4c48
Enhance the InstrStage object to enable the specification of an Itinerary with overlapping stages. The default is to maintain the current behavior that the "next" stage immediately follows the previous one.
...
llvm-svn: 78827
2009-08-12 18:31:53 +00:00
3cfc6463c9
Add catch block handling to SjLj exception handling.
...
llvm-svn: 78817
2009-08-12 17:38:44 +00:00
25cae66713
Fix TableGen warnings. This partly reverts my previous change to this file,
...
leaving the mayLoad and mayStore settings around only the load/store
instructions where those can't be inferred from the patterns.
llvm-svn: 78815
2009-08-12 17:04:56 +00:00
a5fdfac6ca
register naming cleanup (s/ip/r12/)
...
llvm-svn: 78806
2009-08-12 15:21:13 +00:00
9a6cf91261
Change TargetAsmInfo to be constructed via TargetRegistry from a Target+Triple
...
pair instead of from a virtual method on TargetMachine. This cuts the final
ties of TargetAsmInfo to TargetMachine, meaning that MC can now use
TargetAsmInfo.
llvm-svn: 78802
2009-08-12 07:22:17 +00:00
bb2af3555c
Shrink Thumb2 movcc instructions.
...
llvm-svn: 78790
2009-08-12 05:17:19 +00:00
81348021b1
Remove another Darwin assembler workaround.
...
llvm-svn: 78779
2009-08-12 02:07:19 +00:00
fd10869d4b
80 col violation.
...
llvm-svn: 78778
2009-08-12 02:03:03 +00:00
608d92c943
Remove an Darwin assembler workaround.
...
llvm-svn: 78777
2009-08-12 01:56:42 +00:00
1e6c2a1c17
Shrink ADDS, ADC, RSB, and SUBS.
...
llvm-svn: 78776
2009-08-12 01:49:45 +00:00
f042eadd1e
Add missing chain operands for VLD* and VST* instructions.
...
Set "mayLoad" and "mayStore" on the load/store instructions.
llvm-svn: 78761
2009-08-12 00:49:01 +00:00
f6a9d06241
Shrinkify Thumb2 r = add sp, imm.
...
llvm-svn: 78745
2009-08-11 23:00:31 +00:00
abdcbc7ef2
Change the asmprinter to print the comment character before the
...
"inlineasmstart/end" strings so that the contents of the directive
are separate from the comment character. This lets elf targets
get #APP/#NOAPP for free even if they don't use "#" as the comment
character. This also allows hoisting the darwin stuff up to the
shared TAI class.
llvm-svn: 78737
2009-08-11 22:39:40 +00:00
fd5defed1d
Allow a zero cycle stage to reserve/require a FU without advancing the cycle counter.
...
llvm-svn: 78736
2009-08-11 22:38:43 +00:00
54075a78b4
factorize more darwin TAI stuff. Note that this gives
...
darwin/arm support for .no_dead_strip
llvm-svn: 78734
2009-08-11 22:31:42 +00:00
6747b39ca5
factorize darwin ProtectedDirective and SetDirective.
...
llvm-svn: 78732
2009-08-11 22:22:44 +00:00
d832c8e87c
all darwin targets have .space and .zerofill, pull up.
...
llvm-svn: 78730
2009-08-11 22:17:31 +00:00
f710f71839
eliminate template from arm TAI
...
llvm-svn: 78729
2009-08-11 22:14:59 +00:00
7faf1fd9a0
move LCOMMDirective = "\t.lcomm\t" up to DarwinTAI, eliminate
...
template in PPC backend for TAI.
llvm-svn: 78727
2009-08-11 22:06:07 +00:00
cc9ca3500d
Shrinkify Thumb2 load / store multiple instructions.
...
llvm-svn: 78717
2009-08-11 21:11:32 +00:00
9f94459d24
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while
...
the latter is capable of representing either a primitive or an extended type.
llvm-svn: 78713
2009-08-11 20:47:22 +00:00
2c30970b22
pass the TargetTriple down from each target ctor to the
...
LLVMTargetMachine ctor. It is currently unused.
llvm-svn: 78711
2009-08-11 20:42:37 +00:00
fe27130454
split "JumpTableDirective" (an existing hack) into a PIC and nonPIC
...
version. This allows TAI implementations to specify the directive to use
based on the mode being codegen'd for.
The real fix for this is to remove JumpTableDirective, but I don't feel
like diving into the jumptable snarl just now.
llvm-svn: 78709
2009-08-11 20:30:58 +00:00
841850ed26
Add Thumb2 eh_sjlj_setjmp implementation
...
llvm-svn: 78701
2009-08-11 19:42:21 +00:00
1d5350c08f
fix GetInstSizeInBytes for eh_sjlj_setjmp
...
llvm-svn: 78683
2009-08-11 17:08:15 +00:00
eda08015ee
This void is implicit in C++.
...
llvm-svn: 78678
2009-08-11 16:03:08 +00:00
f24f9d9cb6
Whitespace cleanup. Remove trailing whitespace.
...
llvm-svn: 78666
2009-08-11 15:33:49 +00:00
74eb9e7bfd
Move ~ARMConstantPoolValue() to the .cpp file to avoid needing to include <cstdlib> in the header.
...
llvm-svn: 78665
2009-08-11 15:26:27 +00:00
806845daec
Fix the previous accidental commit. Now shrinking common Thumb2 load / store instructions.
...
llvm-svn: 78659
2009-08-11 09:37:40 +00:00
3606467709
Fix Thumb2 load / store addressing mode matching code. Do not use so_reg form to
...
match base only address, i.e. [r] since Thumb2 requires a offset register field.
For those, use [r + imm12] where the immediate is zero.
Note the generated assembly code does not look any different after the patch.
But the bug would have broken the JIT (if there is Thumb2 support) and it can
break later passes which expect the address mode to be well-formed.
llvm-svn: 78658
2009-08-11 08:52:18 +00:00
d4d352c663
80 column violation.
...
llvm-svn: 78657
2009-08-11 08:47:46 +00:00
192d7c0752
Cosmetic changes.
...
llvm-svn: 78655
2009-08-11 07:36:14 +00:00
6e62e93a8d
Adding a blank line back.
...
llvm-svn: 78654
2009-08-11 07:32:58 +00:00
12842f9865
Use vAny type to get rid of Neon intrinsics that differed only in whether
...
the overloaded vector types allowed floating-point or integer vector elements.
Most of these operations actually depend on the element type, so bitcasting
was not an option.
If you include the vpadd intrinsics that I updated earlier, this gets rid
of 20 intrinsics.
llvm-svn: 78646
2009-08-11 05:39:44 +00:00
741a9c7bf6
Use new EVT::vAny type to combine Neon intrinsics for VPADD.
...
llvm-svn: 78632
2009-08-11 01:15:26 +00:00
b80734bb15
Fix bug in NEON convert for single-precision FP. This also fixes the tblgen warnings.
...
llvm-svn: 78629
2009-08-11 01:07:38 +00:00
9382d5ac05
Add stdlib.h
...
llvm-svn: 78627
2009-08-11 00:20:00 +00:00
693e36a3e8
SjLj based exception handling unwinding support. This patch is nasty, brutish
...
and short. Well, it's kinda short. Definitely nasty and brutish.
The front-end generates the register/unregister calls into the SjLj runtime,
call-site indices and landing pad dispatch. The back end fills in the LSDA
with the call-site information provided by the front end. Catch blocks are
not yet implemented.
Built on Darwin and verified no llvm-core "make check" regressions.
llvm-svn: 78625
2009-08-11 00:09:57 +00:00
475f8a4fa2
Enable Thumb2 instruction shrinking (32-bit to 16-bit) pass. Convert a bunch of thumb2 tests to FileCheck.
...
llvm-svn: 78622
2009-08-10 23:56:04 +00:00
733a64db57
Fix a bug where DAGCombine was producing an illegal ConstantFP
...
node after legalize, and remove the workaround code from the
ARM backend.
llvm-svn: 78615
2009-08-10 23:15:10 +00:00
53aa7a960c
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.
...
llvm-svn: 78610
2009-08-10 22:56:29 +00:00
85b5b027f7
Use NEON for single-precision int<->FP conversions.
...
llvm-svn: 78604
2009-08-10 22:17:39 +00:00
3e77df2bcd
SimpleValueType-ify a few more methods on TargetLowering.
...
llvm-svn: 78595
2009-08-10 20:46:15 +00:00
f72c13bdf5
Handle the constantfp created during post-legalization dag combiner phase.
...
llvm-svn: 78594
2009-08-10 20:25:59 +00:00
246617857f
Continue the SimpleValueType-ification.
...
llvm-svn: 78593
2009-08-10 20:18:46 +00:00
6c20391d38
split MachO section handling stuff out to its out .h/.cpp file.
...
llvm-svn: 78576
2009-08-10 18:15:01 +00:00
fbcafd4c6c
arm only needs to emit one .align directive for hidden nlp's, not one
...
per pointer.
llvm-svn: 78574
2009-08-10 18:02:16 +00:00
292472d3d3
make sure that arm nonlazypointers are aligned properly
...
llvm-svn: 78573
2009-08-10 18:01:34 +00:00
62e053b790
Checkpoint scheduling itinerary changes.
...
llvm-svn: 78564
2009-08-10 15:56:13 +00:00
5bb93ce769
Watch out for empty BB.
...
llvm-svn: 78562
2009-08-10 08:10:13 +00:00
8a640ae504
rev, rev16, and revsh do not set CPSR.
...
llvm-svn: 78561
2009-08-10 07:58:45 +00:00
f16a1d5b79
Duh. Most 16-bit Thumb rr instructions are two-address. Fix table.
...
llvm-svn: 78560
2009-08-10 07:20:37 +00:00
1f5bee14a1
CPSR can be livein; transfer predicate operands correctly; tMUL is two-address.
...
llvm-svn: 78559
2009-08-10 06:57:42 +00:00
092b701a2c
Add support for folding loads / stores into 16-bit moves used by Thumb2.
...
llvm-svn: 78558
2009-08-10 06:32:05 +00:00
55c014a9f3
80 col violation.
...
llvm-svn: 78557
2009-08-10 05:51:48 +00:00
f5b73869f2
Use tMOVgpr2gpr instead of t2MOVr.
...
llvm-svn: 78556
2009-08-10 05:49:43 +00:00
51cbd2d6c4
Add support to reduce most of 32-bit Thumb2 arithmetic instructions.
...
llvm-svn: 78550
2009-08-10 02:37:24 +00:00
5b4c308f0c
Always use the 16-bit tMOVgpr2gpr instead of the 32-bit t2MOVr.
...
llvm-svn: 78549
2009-08-10 02:06:53 +00:00
cb307a27bf
Make the big switch: Change MCSectionMachO to represent a section *semantically*
...
instead of syntactically as a string. This means that it keeps track of the
segment, section, flags, etc directly and asmprints them in the right format.
This also includes parsing and validation support for llvm-mc and
"attribute(section)", so we should now start getting errors about invalid
section attributes from the compiler instead of the assembler on darwin.
Still todo:
1) Uniquing of darwin mcsections
2) Move all the Darwin stuff out to MCSectionMachO.[cpp|h]
3) there are a few FIXMEs, for example what is the syntax to get the
S_GB_ZEROFILL segment type?
llvm-svn: 78547
2009-08-10 01:39:42 +00:00
d461c1c559
Add support to convert 32-bit instructions to 16-bit non-two-address ones.
...
llvm-svn: 78540
2009-08-09 19:17:19 +00:00
cfed3005e5
Use subclassing to print lane-like immediates (w/o hash) eliminating
...
'no_hash' modifier. Hopefully this will make Daniel happy :)
llvm-svn: 78514
2009-08-08 23:10:41 +00:00
1cb9396f4f
1. Make MCSection an abstract class.
...
2. Move section switch printing to MCSection virtual method which takes a
TAI. This eliminates textual formatting stuff from TLOF.
3. Eliminate SwitchToSectionDirective, getSectionFlagsAsString, and
TLOFELF::AtIsCommentChar.
llvm-svn: 78510
2009-08-08 22:41:53 +00:00
ce7d14032b
now that getOrCreateSection is all object-file specific,
...
give the impls an object-file-specific name. In the future
they can take different arguments etc.
llvm-svn: 78495
2009-08-08 20:22:20 +00:00
028f6dc4c2
Update CMake
...
llvm-svn: 78475
2009-08-08 17:03:13 +00:00
7167f33872
Add insert_elt / extract_elt patterns for v4f32 stuff.
...
Did anyone tests v4f32 ever?
llvm-svn: 78470
2009-08-08 14:06:07 +00:00
4218516f5d
Lane number should be printed w/o hash
...
llvm-svn: 78469
2009-08-08 14:05:53 +00:00
887d05ce9b
Use VLDM / VSTM to spill/reload 128-bit Neon registers
...
llvm-svn: 78468
2009-08-08 13:35:48 +00:00
e2231070ff
Implement Neon VZIP and VUZP instructions. These are very similar to VTRN,
...
so I generalized the class for VTRN in the .td file to handle all 3 of them.
llvm-svn: 78460
2009-08-08 06:13:25 +00:00
db46af0461
Implement Neon VTRN instructions. For now, anyway, these are selected
...
directly from the intrinsics produced by the frontend. If it is more
convenient to have a custom DAG node for using these to implement shuffles,
we can add that later.
llvm-svn: 78459
2009-08-08 05:53:00 +00:00
1be453b462
Add a skeleton Thumb2 instruction size reduction pass.
...
llvm-svn: 78456
2009-08-08 03:21:23 +00:00
2aa91cc2be
Code refactoring. No functionality change.
...
llvm-svn: 78455
2009-08-08 03:20:32 +00:00
Evan Cheng