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484 Commits

Author SHA1 Message Date
Jim Grosbach 15c6884a4b ARM assembly aliases for two-operand V[R]SHR instructions. 
rdar://11189467

llvm-svn: 154087
 2012-04-05 07:23:53 +00:00
Jim Grosbach daa04130ed ARM encoding for VSWP got the second operand incorrect. 
Make the non-tied register operand names line up with what the base
class encoding handler expects.

rdar://11157236

llvm-svn: 153766
 2012-03-30 18:53:01 +00:00
Jakob Stoklund Olesen 9e512120b7 Spill DPair registers, not just QPR. 
The arm_neon intrinsics can create virtual registers from the DPair
register class which allows both even-odd and odd-even D-register pairs.

This fixes PR12389.

llvm-svn: 153603
 2012-03-28 21:20:32 +00:00
Richard Barton 7ce39497b4 Fixup VST1.32 with writeback instruction. Also re-factor non-writeback version. 
llvm-svn: 153573
 2012-03-28 10:18:11 +00:00
Jim Grosbach ed428bc1ce ARM more NEON VLD/VST composite physical register refactoring. 
Register pair, all lanes subscripting.

llvm-svn: 152157
 2012-03-06 23:10:38 +00:00
Jim Grosbach 13a292cc74 ARM refactor more NEON VLD/VST instructions to use composite physregs 
Register pair VLD1/VLD2 all-lanes instructions. Kill off more of the
pseudos as a result.

llvm-svn: 152150
 2012-03-06 22:01:44 +00:00
Jim Grosbach e5307f9019 ARM Refactor VLD/VST spaced pair instructions. 
Use the new composite physical registers.

llvm-svn: 152063
 2012-03-05 21:43:40 +00:00
Jim Grosbach c71bf4739a ARM Remove a bit of dead code. 
llvm-svn: 152061
 2012-03-05 21:09:58 +00:00
Jim Grosbach c988e0c521 ARM refactor away a bunch of VLD/VST pseudo instructions. 
With the new composite physical registers to represent arbitrary pairs
of DPR registers, we don't need the pseudo-registers anymore. Get rid of
a bunch of them that use DPR register pairs and just use the real
instructions directly instead.

llvm-svn: 152045
 2012-03-05 19:33:30 +00:00
Sebastian Pop 957a6583f1 updated patch for the ARM fused multiply add/sub 
In this update:
- I assumed neon2 does not imply vfpv4, but neon and vfpv4 imply neon2.
- I kept setting .fpu=neon-vfpv4 code attribute because that is what the
assembler understands.

Patch by Ana Pazos <apazos@codeaurora.org>

llvm-svn: 152036
 2012-03-05 17:39:52 +00:00
Jim Grosbach a0ec8896ac ARM vbit/vbif/vbsl assembly optional size suffix. 
These instructions accept but do not require a size suffix.

rdar://10947225

llvm-svn: 151646
 2012-02-28 19:11:07 +00:00
James Molloy 547d4c0662 Improve generated code for extending loads and some trunc stores on ARM. 
Teach TargetSelectionDAG about lengthening loads for vector types and set v4i8 as legal. Allow FP_TO_UINT for v4i16 from v4i32.

llvm-svn: 150956
 2012-02-20 09:24:05 +00:00
Jia Liu b22310fda6 Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 
llvm-svn: 150878
 2012-02-18 12:03:15 +00:00
Lang Hames 876f24f706 Third time's the charm...? 
llvm-svn: 150447
 2012-02-14 00:34:30 +00:00
Lang Hames 185455df7e Unswap swap operands, partially reducing confusion. 
llvm-svn: 150444
 2012-02-14 00:17:12 +00:00
Lang Hames aef4ca78c5 Make operands for VSWP read-modify-write. 
llvm-svn: 150433
 2012-02-13 23:37:19 +00:00
Jim Grosbach 086cbfac7d NEON VLD4(all lanes) assembly parsing and encoding. 
llvm-svn: 148884
 2012-01-25 00:01:08 +00:00
Jim Grosbach ccb6d55dae Tidy up. Rename VLD4DUP patterns for consistency. 
llvm-svn: 148883
 2012-01-24 23:47:07 +00:00
Jim Grosbach b78403ce48 NEON VLD3(all lanes) assembly parsing and encoding. 
llvm-svn: 148882
 2012-01-24 23:47:04 +00:00
Jim Grosbach 8e2722cdb0 NEON VST4(one lane) assembly parsing and encoding. 
llvm-svn: 148836
 2012-01-24 18:53:13 +00:00
Jim Grosbach 14952a0e32 NEON VLD4(one lane) assembly parsing and encoding. 
llvm-svn: 148832
 2012-01-24 18:37:25 +00:00
Jim Grosbach 3cfef8d467 NEON Two-operand assembly aliases for VSRA. 
llvm-svn: 148821
 2012-01-24 17:55:36 +00:00
Jim Grosbach 7ae12cc546 NEON Two-operand assembly aliases for VSLI. 
llvm-svn: 148819
 2012-01-24 17:49:15 +00:00
Jim Grosbach 7b6f0f67aa NEON Two-operand assembly aliases for VSRI. 
llvm-svn: 148818
 2012-01-24 17:46:58 +00:00
Jim Grosbach 681db34eae NEON add correct predicates for some asm aliases. 
llvm-svn: 148815
 2012-01-24 17:23:29 +00:00
Jim Grosbach da70eac268 NEON VST4(multiple 4 element structures) assembly parsing. 
llvm-svn: 148764
 2012-01-24 00:58:13 +00:00
Jim Grosbach ed561fc850 NEON VLD4(multiple 4 element structures) assembly parsing. 
llvm-svn: 148762
 2012-01-24 00:43:17 +00:00
Jim Grosbach 17bacab475 Fix typo. 
llvm-svn: 148757
 2012-01-24 00:12:39 +00:00
Jim Grosbach d3d36d9315 NEON VST3(single element from one lane) assembly parsing. 
llvm-svn: 148755
 2012-01-24 00:07:41 +00:00
Jim Grosbach 1a74724fc9 NEON VST3(multiple 3-element structures) assembly parsing. 
llvm-svn: 148748
 2012-01-23 23:45:44 +00:00
Jim Grosbach ac2af3ffab NEON VLD3(multiple 3-element structures) assembly parsing. 
llvm-svn: 148745
 2012-01-23 23:20:46 +00:00
Jim Grosbach a8b444b08b NEON VLD3 lane-indexed assembly parsing and encoding. 
llvm-svn: 148734
 2012-01-23 21:53:26 +00:00
Jim Grosbach d28ef9ac46 Simplify some NEON assembly pseudo definitions. 
Let the generic token alias definitions handle the data subtype
suffices. We don't need explicit versions for each.

llvm-svn: 148718
 2012-01-23 19:39:08 +00:00
Anton Korobeynikov 5482b9f535 Add fused multiple+add instructions from VFPv4. 
Patch by Ana Pazos!

llvm-svn: 148658
 2012-01-22 12:07:33 +00:00
Bob Wilson 6c7aaec077 ARM vector any_extends need to be selected to vmovl. <rdar://problem/10723651> 
We have patterns for vector sext and zext operations but were missing
anyext.  Without those patterns, codegen will fail when the selection DAG
has any_extend nodes.

llvm-svn: 148568
 2012-01-20 20:59:56 +00:00
Jim Grosbach 90f5780fc1 VST2 four-register w/ update pseudos for fixed/register update. 
rdar://10724489

llvm-svn: 148560
 2012-01-20 19:16:00 +00:00
Jim Grosbach a9d36fbca7 NEON use vmov.i32 to splat some f32 values into vectors. 
For bit patterns that aren't representable using the 8-bit floating point
representation for vmov.f32, but are representable via vmov.i32, treat
the .f32 syntax as an alias. Most importantly, this covers the case
'vmov.f32 Vd, #0.0'.

rdar://10616677

llvm-svn: 148556
 2012-01-20 18:09:51 +00:00
Jim Grosbach 74ac7d50a1 ARM updating VST2 pseudo-lowering fixed vs. register update. 
rdar://10663487

llvm-svn: 147876
 2012-01-10 21:11:12 +00:00
Jim Grosbach 2b80dad572 ARM NEON mnemonic aliase for vrecpeq. 
llvm-svn: 147109
 2011-12-21 23:52:37 +00:00
Jim Grosbach 260b4b336a ARM NEON optional data type on VSWP instructions. 
llvm-svn: 147103
 2011-12-21 23:09:28 +00:00
Jim Grosbach a50e24fcb3 ARM NEON mnemonic aliases for vzipq and vswpq. 
llvm-svn: 147102
 2011-12-21 23:04:33 +00:00
Jim Grosbach c80a264386 ARM NEON assmebly parsing for VLD2 to all lanes instructions. 
llvm-svn: 147069
 2011-12-21 19:40:55 +00:00
Jim Grosbach c5af54ec89 ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback. 
llvm-svn: 147025
 2011-12-21 00:38:54 +00:00
Jim Grosbach 2c59052984 ARM assembly parsing and encoding for VST2 single-element, double spaced. 
llvm-svn: 146990
 2011-12-20 20:46:29 +00:00
Jim Grosbach 75e2ab5db2 ARM assembly parsing and encoding for VLD2 single-element, double spaced. 
llvm-svn: 146983
 2011-12-20 19:21:26 +00:00
Jim Grosbach 045b6c71a6 ARM NEON assembly aliases for VMOV<-->VMVN for i32 immediates. 
e.g., "vmov.i32 d4, #-118" can be assembled as "vmvn.i32 d4, #117"

rdar://10603913

llvm-svn: 146925
 2011-12-19 23:51:07 +00:00
Jim Grosbach 64f4de29e0 ARM NEON two-operand aliases for VPADD. 
rdar://10602276

llvm-svn: 146895
 2011-12-19 19:51:03 +00:00
Jim Grosbach 9ae4fc035b ARM NEON implied destination aliases for VMAX/VMIN. 
llvm-svn: 146885
 2011-12-19 18:57:38 +00:00
Jim Grosbach cef98cddbe ARM NEON relax parse time diagnostics for alignment specifiers. 
There's more variation that we need to handle. Error checking will need
to be on operand predicates.

llvm-svn: 146884
 2011-12-19 18:31:43 +00:00
Jim Grosbach a7d2421603 Tidy up. 
llvm-svn: 146882
 2011-12-19 18:11:17 +00:00