3b5791f982
I've lost my mind. PR4572 has not been fixed.
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llvm-svn: 77031
2009-07-25 01:11:46 +00:00
f3a1fce8ae
Change Thumb2 jumptable codegen to one that uses two level jumps:
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Before:
adr r12, #LJTI3_0_0
ldr pc, [r12, +r0, lsl #2 ]
LJTI3_0_0:
.long LBB3_24
.long LBB3_30
.long LBB3_31
.long LBB3_32
After:
adr r12, #LJTI3_0_0
add pc, r12, +r0, lsl #2
LJTI3_0_0:
b.w LBB3_24
b.w LBB3_30
b.w LBB3_31
b.w LBB3_32
This has several advantages.
1. This will make it easier to optimize this to a TBB / TBH instruction +
(smaller) table.
2. This eliminate the need for ugly asm printer hack to force the address
into thumb addresses (bit 0 is one).
3. Same codegen for pic and non-pic.
4. This eliminate the need to align the table so constantpool island pass
won't have to over-estimate the size.
Based on my calculation, the later is probably slightly faster as well since
ldr pc with shifter address is very slow. That is, it should be a win as long
as the HW implementation can do a reasonable job of branch predict the second
branch.
llvm-svn: 77024
2009-07-25 00:33:29 +00:00
8c8e88bd39
Remove a duplicated test.
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llvm-svn: 77020
2009-07-25 00:24:40 +00:00
01740ab57b
Forgot this test earlier.
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llvm-svn: 77007
2009-07-24 22:42:45 +00:00
aee0e1f48c
Fix these tests.
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llvm-svn: 77006
2009-07-24 22:42:22 +00:00
fae639c9ad
Move insertps tests to sse41 combo test file, convert to filecheck
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format and add an extract/insert test.
llvm-svn: 76994
2009-07-24 19:24:26 +00:00
3990850a7d
Convert a test to FileCheck.
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llvm-svn: 76954
2009-07-24 06:01:46 +00:00
26aff56462
Remove SectionKind::Small*. This was only used on mips, and is apparently
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a sad mistake that is regretted. :)
llvm-svn: 76935
2009-07-24 03:11:51 +00:00
fc39e417a8
Add tests for handling of globals and tls on the XCore. These currently fail
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but pass when run against r76652.
llvm-svn: 76923
2009-07-24 00:38:20 +00:00
17151155ed
Remove the IA-64 backend.
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llvm-svn: 76920
2009-07-24 00:30:09 +00:00
dc99f07113
Thumb2 does not allow the use of "pc" register as part of the load / store address.
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llvm-svn: 76909
2009-07-23 23:09:51 +00:00
d2919a1773
Fix up ARM constant island pass for Thumb2.
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Also fixed up code to fully use the SoImm field for ADR on ARM mode.
llvm-svn: 76890
2009-07-23 18:27:47 +00:00
dc13b7c637
merge one more sse41 test into sse41.ll
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llvm-svn: 76853
2009-07-23 04:49:39 +00:00
70d5783535
merge another sse41 test into sse41.ll
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llvm-svn: 76852
2009-07-23 04:43:48 +00:00
08fc6e6e40
merge sse41-pmovx.ll into sse41.ll
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llvm-svn: 76850
2009-07-23 04:39:09 +00:00
b9cdd3153c
change a test to run in filecheck style. Rename it to be a general
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dumping ground of various SSE4.1 tests, since filecheck can reasonably
handle them all in one file. Generalize it to check x86-64 stuff as
well since it has a different ABI (a convenient way to test both the
reg and mem forms of these instructions).
llvm-svn: 76848
2009-07-23 04:33:02 +00:00
b1b77ca862
Support insertps via the intrinsic and add a couple of simple
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testcases to make sure it's being generated.
llvm-svn: 76843
2009-07-23 02:22:41 +00:00
327cb795a1
Add test for pinsrd and pinsrb instructions.
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llvm-svn: 76840
2009-07-23 01:58:04 +00:00
b215100c7c
Revert r75663 (and r76805), as it is causing regressions on powerpc.
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llvm-svn: 76823
2009-07-23 00:09:46 +00:00
824ab40381
x86 isel tweak: use lea (%reg,%reg) instead of lea (,%reg,2).
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llvm-svn: 76817
2009-07-22 23:26:55 +00:00
cdbef5f2c0
Add -march=ppc32 lines so that this test doesn't ever default to ppc64.
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llvm-svn: 76805
2009-07-22 22:08:31 +00:00
e270d4a4dd
Use getTargetConstant instead of getConstant since it's meant as an constant operand.
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llvm-svn: 76803
2009-07-22 22:03:29 +00:00
c510293251
Make the grep line in this test more specific, to avoid
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unintended matches.
llvm-svn: 76802
2009-07-22 22:02:42 +00:00
d2d52d1906
Ignore undef uses.
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llvm-svn: 76799
2009-07-22 21:51:42 +00:00
0cf7f5d6d2
Revert commit 76707, it was breaking the llvm-gcc build
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on linux platforms. The binutils assembler does not
recognize the "s" flag, see for example
http://sourceware.org/binutils/docs/as/Section.html
llvm-svn: 76733
2009-07-22 10:35:05 +00:00
8ebaec6b27
set the ELF "small" flag on objects that end up in .rodata.cst4 consistently,
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updating a mips testcase to expect it.
llvm-svn: 76707
2009-07-22 00:41:56 +00:00
332a6590ae
Remove a big test case.
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llvm-svn: 76669
2009-07-21 22:52:04 +00:00
38e88cb53f
Do not select tSXTB / tSXTH in thumb2 mode.
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llvm-svn: 76600
2009-07-21 18:15:26 +00:00
8e55200089
convert this test to filecheck format, which is faster and avoids false matches of "st" -> "stdin"
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llvm-svn: 76591
2009-07-21 17:36:24 +00:00
b61f9c8c8d
add a testcase for the pic16 section handling stuff.
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llvm-svn: 76579
2009-07-21 16:48:20 +00:00
07a6ac6b29
Another rewriter bug exposed by recent coalescer changes. ReuseInfo::GetRegForReload() should make sure the "switched" register is in the desired register class. I'm surprised this hasn't caused more failures in the past.
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llvm-svn: 76558
2009-07-21 09:15:00 +00:00
83423aa276
remove a very large testcase for now.
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llvm-svn: 76537
2009-07-21 06:28:36 +00:00
a7bb55ebb6
Fix a dagga combiner bug: avoid creating illegal constant.
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Is this really a winning transformation?
fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or
(srl (and x, (shl -1, c1)), (sub c1, c2))
llvm-svn: 76535
2009-07-21 05:40:15 +00:00
0d8b0cf3b8
Fix ARM isle code that optimize multiply by constants which are power-of-2 +/- 1.
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llvm-svn: 76520
2009-07-21 00:31:12 +00:00
9a47392f2e
Cross RC coalescing is now on by default.
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llvm-svn: 76519
2009-07-21 00:22:59 +00:00
40c68ad3bb
Re-apply 75490, 75806 and 76177 with fixes and tests. Efficiency comes
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next.
llvm-svn: 76486
2009-07-20 22:02:59 +00:00
a2b8c3f98f
Forgot this test earlier.
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llvm-svn: 76485
2009-07-20 21:46:42 +00:00
57106d6dc0
Use TII->findCommutedOpIndices to find the commute operands (rather than guessing).
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llvm-svn: 76472
2009-07-20 21:16:08 +00:00
027d9f93ea
Fix some sub-reg coalescing bugs where the coalescer wasn't updating the resulting interval's register class.
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llvm-svn: 76458
2009-07-20 19:47:55 +00:00
33a3fd0b9c
Revert the addition of hasNoPointerOverflow to GEPOperator.
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Getelementptrs that are defined to wrap are virtually useless to
optimization, and getelementptrs that are undefined on any kind
of overflow are too restrictive -- it's difficult to ensure that
all intermediate addresses are within bounds. I'm going to take
a different approach.
Remove a few optimizations that depended on this flag.
llvm-svn: 76437
2009-07-20 17:43:30 +00:00
58f9bb2ccd
implement a new magic global "llvm.compiler.used" which is like llvm.used, but
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doesn't cause ".no_dead_strip" to be emitted on darwin.
llvm-svn: 76399
2009-07-20 06:14:25 +00:00
4e4eb0b00c
Restore AsmWriterEmitter.cpp back to 74742. The recent changes broke Thumb.
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llvm-svn: 76398
2009-07-20 06:10:07 +00:00
aba695c7d0
Fix http://llvm.org/bugs/show_bug.cgi?id=4583
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Inline asm instructions may have additional <imp-def,kill> register operands.
These operands are not marked with a flag like the normal asm operands, so we
must not assert that there is a flag.
llvm-svn: 76373
2009-07-19 19:09:59 +00:00
090db9b7a9
Catch more coalescing opportunities.
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llvm-svn: 76282
2009-07-18 04:52:23 +00:00
e20cbf3068
Enable cross register class coalescing.
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llvm-svn: 76281
2009-07-18 02:10:10 +00:00
a776067d3f
Fix pr4552. Stack slot coloring with register must take care not to generate illegal ams.
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llvm-svn: 76258
2009-07-17 22:42:51 +00:00
18fe458103
Fix x86 inline ams 'q' constraint support. In 32-bit mode, it's just like 'Q', i.e. EAX, EDX, ECX, EBX. In 64-bit mode, it just means all the i64r registers. Yeah, that makes sense.
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llvm-svn: 76248
2009-07-17 22:13:25 +00:00
52d436e98b
rename test.
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llvm-svn: 76197
2009-07-17 18:05:55 +00:00
97f3f965eb
Make promotion in operation legalization for SETCC work correctly.
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llvm-svn: 76153
2009-07-17 05:16:04 +00:00
c5df7e2dc1
Emit cross regclass register moves for thumb2.
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Minor code duplication cleanup.
llvm-svn: 76124
2009-07-16 23:26:06 +00:00
Evan Cheng