f6af822c76
First draft of stack slot loads / stores lowering
...
llvm-svn: 70735
2009-05-03 13:09:57 +00:00
ed65671768
Reverse order of memory arguments
...
llvm-svn: 70734
2009-05-03 13:09:40 +00:00
04888305f6
Remove bogus pattern
...
llvm-svn: 70733
2009-05-03 13:09:24 +00:00
6399a3d628
Correct asmprinting of memory operands
...
llvm-svn: 70732
2009-05-03 13:09:10 +00:00
a3bce28ae0
Match wrapper node for address
...
llvm-svn: 70731
2009-05-03 13:08:51 +00:00
cfc97056e7
Add lowering for global address nodes. Not pretty efficient though.
...
llvm-svn: 70730
2009-05-03 13:08:33 +00:00
b5613928f5
Some early full call lowering draft for direct calls
...
llvm-svn: 70729
2009-05-03 13:08:13 +00:00
ec3f0b3f9d
Add call frame setup instruction elimination and lowerid for bunch of call-related stuff.
...
llvm-svn: 70728
2009-05-03 13:07:54 +00:00
5613510c81
Add CALL lowering.
...
llvm-svn: 70727
2009-05-03 13:07:31 +00:00
c995ddd017
Add bunch of mem-whatever patterns
...
llvm-svn: 70726
2009-05-03 13:07:10 +00:00
f702a0085c
Add bunch of reg-mem inst patterns
...
llvm-svn: 70725
2009-05-03 13:06:46 +00:00
ed1c3dfa0f
Add normal and trunc stores
...
llvm-svn: 70724
2009-05-03 13:06:26 +00:00
31ecd23a9e
Basic support for mem=>reg moves
...
llvm-svn: 70723
2009-05-03 13:06:03 +00:00
80a73e7d8b
Add 8-bit insts. zext behaviour is not modelled yet
...
llvm-svn: 70722
2009-05-03 13:05:42 +00:00
b900245e13
Add 8-bit regclass and pattern for sext_inreg
...
llvm-svn: 70721
2009-05-03 13:05:22 +00:00
b638fb10f5
Add pattern for OR
...
llvm-svn: 70720
2009-05-03 13:05:00 +00:00
654cb0a761
Add reg-imm variants
...
llvm-svn: 70719
2009-05-03 13:04:41 +00:00
37709c3584
Add hint to nop
...
llvm-svn: 70718
2009-05-03 13:04:23 +00:00
6339db830e
Add more instructions
...
llvm-svn: 70717
2009-05-03 13:04:06 +00:00
e32c817d2c
Cleanup
...
llvm-svn: 70716
2009-05-03 13:03:50 +00:00
15a515b1af
Add dummy lowering for shifts
...
llvm-svn: 70715
2009-05-03 13:03:33 +00:00
55a085b539
We don't have any div at all - thus mark it as expensive
...
llvm-svn: 70714
2009-05-03 13:03:14 +00:00
abb51755c8
We're not going to spend 100% of time in interrupts, do we? :)
...
llvm-svn: 70713
2009-05-03 13:02:57 +00:00
8a17dff7d0
Add simple reg-reg add.
...
llvm-svn: 70712
2009-05-03 13:02:39 +00:00
6ff6fc95a0
gas uses lower letter for register names
...
llvm-svn: 70711
2009-05-03 13:02:22 +00:00
d7afd69e3b
Add code enough for emission of reg-reg and reg-imm moves. This allows us to compile "ret i16 0" properly!
...
llvm-svn: 70710
2009-05-03 13:02:04 +00:00
c942782b3b
Add function body printing routine
...
llvm-svn: 70709
2009-05-03 13:01:41 +00:00
ef811d8e05
Add 'msp430' target triple recognizer
...
llvm-svn: 70708
2009-05-03 13:01:23 +00:00
a9b7df98e6
Make emit{Prologue,Epilogue}() noop for now
...
llvm-svn: 70707
2009-05-03 13:01:04 +00:00
69f51f0b41
Add callee-saved regs & reg classes getter hooks
...
llvm-svn: 70706
2009-05-03 13:00:46 +00:00
efcd5aa381
Add simple FP indicator for given function hook
...
llvm-svn: 70705
2009-05-03 13:00:28 +00:00
c10f98ace3
Provide set of reserved registers
...
llvm-svn: 70704
2009-05-03 13:00:11 +00:00
7bfc3ea2ee
Add proper ISD::RET lowering
...
llvm-svn: 70703
2009-05-03 12:59:50 +00:00
3849be6ca1
Add first draft of MSP430 calling convention stuff and draft of ISD::FORMAL_ARGUMENTS node lowering.
...
llvm-svn: 70702
2009-05-03 12:59:33 +00:00
77e5a11ec2
Fix register names, fix register allocation order, handle frame pointer.
...
llvm-svn: 70701
2009-05-03 12:59:16 +00:00
64717bbc14
Clearify the usage and add some debug stuff
...
llvm-svn: 70700
2009-05-03 12:58:58 +00:00
e10f69a8a7
Cleanup
...
llvm-svn: 70699
2009-05-03 12:58:40 +00:00
128e8a188f
Add cmake script. No idea whether it works or not :)
...
llvm-svn: 70698
2009-05-03 12:58:22 +00:00
4130a7c1e7
Add a note
...
llvm-svn: 70697
2009-05-03 12:58:05 +00:00
7c4db99df3
Typo
...
llvm-svn: 70695
2009-05-03 12:57:47 +00:00
101380015c
Dummy MSP430 backend
...
llvm-svn: 70694
2009-05-03 12:57:15 +00:00
e01821edbd
'The attached patch fixes an issue where llc -march=cpp fails with
...
"Invalid primitive type" on input containing the x86_fp80 type.'
Patch by Collin Winter!
llvm-svn: 70610
2009-05-01 23:54:26 +00:00
31af617924
Fix compilation for some targets other than x86.
...
llvm-svn: 70522
2009-04-30 23:50:26 +00:00
a5037484a4
Make DebugLoc independent of DwarfWriter.
...
-Replace DebugLocTuple's Source ID with CompileUnit's GlobalVariable*
-Remove DwarfWriter::getOrCreateSourceID
-Make necessary changes for the above (fix callsites, etc.)
llvm-svn: 70520
2009-04-30 23:22:31 +00:00
e651f25a7b
getCommonSubClass() - Calculate the largest common sub-class of two register
...
classes.
This is implemented as a function rather than a method on TargetRegisterClass
because it is symmetric in its arguments.
llvm-svn: 70512
2009-04-30 21:23:32 +00:00
db3a57ec5c
Set mayLoad on MOVZX32_NOREXrm8 too.
...
llvm-svn: 70466
2009-04-30 03:11:48 +00:00
99578674fd
Mark MOV8mr_NOREX and MOV8rm_NOREX as mayStore / mayLoad respectively.
...
llvm-svn: 70461
2009-04-30 00:58:57 +00:00
1fba01bbcd
remove progname which is never set. PR4085
...
llvm-svn: 70453
2009-04-30 00:24:33 +00:00
026e5d7667
Instead of passing in an unsigned value for the optimization level, use an enum,
...
which better identifies what the optimization is doing. And is more flexible for
future uses.
llvm-svn: 70440
2009-04-29 23:29:43 +00:00
7e6e352735
Fix infinite recursion in the C++ code which handles movddup by making it unnecessary.
...
llvm-svn: 70425
2009-04-29 22:47:44 +00:00
5f829d896d
Implement review feedback for vector shuffle work.
...
llvm-svn: 70372
2009-04-29 05:20:52 +00:00
ccd30945f9
Add a public method called getAddressSpace() to the GlobalAddressSDNode.
...
llvm-svn: 70366
2009-04-29 04:43:24 +00:00
084669a1c9
Second attempt:
...
Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to
use the old behavior, the flag is -O0. This change allows for finer-grained
control over which optimizations are run at different -O levels.
Most of this work was pretty mechanical. The majority of the fixes came from
verifying that a "fast" variable wasn't used anymore. The JIT still uses a
"Fast" flag. I'll change the JIT with a follow-up patch.
llvm-svn: 70343
2009-04-29 00:15:41 +00:00
dac88bae4f
Properly print 'P' modifier on inline asm memory operands.
...
This should fix PR3379 and PR4064.
Patch inspired by Edwin Török!
llvm-svn: 70328
2009-04-28 21:49:33 +00:00
7bfed8a9f4
GlobalValue is always pointer type, so an assert isn't required.
...
llvm-svn: 70300
2009-04-28 16:39:45 +00:00
56f2987a87
r70270 isn't ready yet. Back this out. Sorry for the noise.
...
llvm-svn: 70275
2009-04-28 01:04:53 +00:00
d0ae15946c
Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to
...
use the old behavior, the flag is -O0. This change allows for finer-grained
control over which optimizations are run at different -O levels.
Most of this work was pretty mechanical. The majority of the fixes came from
verifying that a "fast" variable wasn't used anymore. The JIT still uses a
"Fast" flag. I'm not 100% sure if it's necessary to change it there...
llvm-svn: 70270
2009-04-28 00:21:31 +00:00
8d6d4b9289
2nd attempt, fixing SSE4.1 issues and implementing feedback from duncan.
...
PR2957
ISD::VECTOR_SHUFFLE now stores an array of integers representing the shuffle
mask internal to the node, rather than taking a BUILD_VECTOR of ConstantSDNodes
as the shuffle mask. A value of -1 represents UNDEF.
In addition to eliminating the creation of illegal BUILD_VECTORS just to
represent shuffle masks, we are better about canonicalizing the shuffle mask,
resulting in substantially better code for some classes of shuffles.
llvm-svn: 70225
2009-04-27 18:41:29 +00:00
2986972118
Rename GR8_ABCD to GR8_ABCD_L and create GR8_ABCD_H, and use these
...
to precisely describe the h-register subreg register classes.
Thanks to Jakob Stoklund Olesen for spotting this and for the
initial patch!
Also, make getStoreRegOpcode and getLoadRegOpcode aware of the
needs of h registers.
llvm-svn: 70211
2009-04-27 16:41:36 +00:00
ec542ca65e
Rename GR8_, GR16_, GR32_, and GR64_ to GR8_ABCD, GR16_ABCD,
...
GR32_ABCD, and GR64_ABCD, respectively, to help describe them.
llvm-svn: 70210
2009-04-27 16:33:14 +00:00
ba99bddf1f
Break up long multi-mnemonic strings into separate lines for readability.
...
llvm-svn: 70209
2009-04-27 15:13:28 +00:00
e15bf109be
Revised 68749 to allow matching of load/stores for address spaces < 256.
...
llvm-svn: 70197
2009-04-27 07:22:10 +00:00
3ad60b18cb
add support for detecting process features on win64, patch by
...
Nicolas Capens!
llvm-svn: 70057
2009-04-25 18:27:23 +00:00
0041bd3523
Change LowerCallResult method so that CCValAssign::BCvt can be used with
...
f64 types. This is not used for anything yet.
llvm-svn: 70006
2009-04-25 00:33:20 +00:00
40e784ce69
Adjust a comment to reflect what the code does. Splitting a 64-bit argument
...
between registers and the stack may be required with the APCS ABI, but it
isn't tied to using a particular version of the ARM architecture.
llvm-svn: 69978
2009-04-24 17:05:01 +00:00
f134b2d212
Fix up some problems with getCopyToReg and getCopyFromReg nodes being
...
chained and "flagged" together. I also made a few changes to handle the
chain and flag values more consistently. I found these problems by
inspection so I'm not aware of anything that breaks because of them
(thus no testcase).
llvm-svn: 69977
2009-04-24 17:00:36 +00:00
62d47d2361
Remove unnecessary references to f32 types. After specifying that f32
...
should be bit-converted to i32, it is sufficient to list only i32 in
subsequent definitions.
llvm-svn: 69973
2009-04-24 16:55:25 +00:00
c1396a2313
Fix PR 4004 by including the call to __tls_get_addr in X86tlsaddr. This is not
...
very elegant, but neither is the tls specification :-(
llvm-svn: 69968
2009-04-24 12:59:40 +00:00
b93db668b3
Revert 69952. Causes testsuite failures on linux x86-64.
...
llvm-svn: 69967
2009-04-24 12:40:33 +00:00
bb881d66f4
PR2957
...
ISD::VECTOR_SHUFFLE now stores an array of integers representing the shuffle
mask internal to the node, rather than taking a BUILD_VECTOR of ConstantSDNodes
as the shuffle mask. A value of -1 represents UNDEF.
In addition to eliminating the creation of illegal BUILD_VECTORS just to
represent shuffle masks, we are better about canonicalizing the shuffle mask,
resulting in substantially better code for some classes of shuffles.
A clean up of x86 shuffle code, and some canonicalizing in DAGCombiner is next.
llvm-svn: 69952
2009-04-24 03:42:54 +00:00
870c33f14b
Fix spurious indentation in a comment.
...
llvm-svn: 69934
2009-04-23 22:41:05 +00:00
5058f240d9
Banksel immediate constant will always immediately follow the GA/ES, so scan an insn from beginnin to find out the banksel operand.
...
llvm-svn: 69883
2009-04-23 10:34:58 +00:00
14efb90fcf
Add support for printing MO_ExternalSymbol operands in
...
memory operand tuples. This doesn't ever come up in normal
code however.
llvm-svn: 69848
2009-04-23 00:57:37 +00:00
107b2818ce
Make the function begin label start after ther data pointer.
...
The address of data frame for function can be obtained by subtracting 2 from the function begin label.
llvm-svn: 69801
2009-04-22 12:02:36 +00:00
7ce5cc6bd1
Get rid of what looks like a copy-and-pasted typo.
...
Spotted by gcc-4.5.
llvm-svn: 69673
2009-04-21 09:44:39 +00:00
47ed1f5293
TLS_addr64 and TLS_addr32 define RDI and EAX. They don't use them.
...
This fixes PR4002.
llvm-svn: 69672
2009-04-21 08:22:09 +00:00
3e3ef7c4d9
Handle direct aggregate type arguments.
...
llvm-svn: 69665
2009-04-21 05:54:51 +00:00
1addf64735
Make X86's copyRegToReg able to handle copies to and from subclasses.
...
This makes the extra copyRegToReg calls in ScheduleDAGSDNodesEmit.cpp
unnecessary. Derived from a patch by Jakob Stoklund Olesen.
llvm-svn: 69635
2009-04-20 22:54:34 +00:00
2c441c6afe
Remove unused variable.
...
llvm-svn: 69624
2009-04-20 20:34:38 +00:00
f8b85477ae
Move duplicated AddLiveIn function from X86 and ARM backends to be a method
...
in the MachineFunction class, renaming it to addLiveIn for consistency with
the same method in MachineBasicBlock. Thanks for Anton for suggesting this.
llvm-svn: 69615
2009-04-20 18:36:57 +00:00
958d5eb032
Match C backend only if it explicitly requested.
...
llvm-svn: 69613
2009-04-20 18:07:22 +00:00
0fcc019d36
Emit the auto variables of a function into a different section than parameters.
...
llvm-svn: 69605
2009-04-20 16:59:35 +00:00
6c8bcf9da1
Fixed a few 64 bit cases in X86InstrInfo::commuteInstruction
...
llvm-svn: 69417
2009-04-18 05:16:01 +00:00
06684350c4
Recommit r69335 and r69336. These were not causing problems.
...
llvm-svn: 69394
2009-04-17 22:40:38 +00:00
b0b10f8bf6
Move the AddLiveIn function definition closer to its uses.
...
llvm-svn: 69382
2009-04-17 20:42:34 +00:00
deeaf70dad
Rearrange code to reduce indentation.
...
llvm-svn: 69381
2009-04-17 20:40:45 +00:00
ea09d4aca8
Clean up formatting, remove trailing whitespace, fix comment typos and
...
punctuation. No functional changes.
llvm-svn: 69378
2009-04-17 20:35:10 +00:00
a4c2290e5f
Use CallConvLower.h and TableGen descriptions of the calling conventions
...
for ARM. Patch by Sandeep Patel.
llvm-svn: 69371
2009-04-17 19:07:39 +00:00
355fe12c82
For general dynamic TLS access we must use
...
leaq foo@TLSGD(%rip), %rdi
as part of the instruction sequence. Using a register other than %rdi and then
copying it to %rdi is not valid.
llvm-svn: 69350
2009-04-17 14:35:58 +00:00
30527b1114
Revert r69335 and r69336. They were causing build failures.
...
llvm-svn: 69347
2009-04-17 04:19:22 +00:00
09dbb0b5e0
MOV8rr_NOREX is a "Move" instruction. This doesn't currently
...
matter, because this instruction isn't generated until after
things that care.
llvm-svn: 69336
2009-04-17 00:45:17 +00:00
74835ce1cb
Don't use MOV8rr_NOREX on x86-32. It doesn't actually hurt anything at
...
present, but it's inconsistent.
llvm-svn: 69335
2009-04-17 00:43:09 +00:00
a8919d0a35
Fix some failures in targets on available_externally functions,
...
this fixes a crash on CodeGen/Generic/externally_available.ll
on ppc hosts. Thanks to Nicholas L for pointing this out.
llvm-svn: 69333
2009-04-17 00:26:12 +00:00
5e42177a0f
fix PR3995. A scale must be 1, 2, 4 or 8.
...
llvm-svn: 69284
2009-04-16 12:34:53 +00:00
de7b3e74be
Fix 80-column violations.
...
llvm-svn: 69204
2009-04-15 19:48:57 +00:00
6711216e84
Add a folding table entry for MOV8rr_NOREX.
...
llvm-svn: 69203
2009-04-15 19:48:28 +00:00
6f873b446a
Fix X86MachineFunctionInfo's doxygen comment.
...
llvm-svn: 69127
2009-04-15 01:20:18 +00:00
dd07f638f5
Do for GR16_NOREX what r69049 did for GR8_NOREX, to avoid trouble with
...
the local register allocator.
llvm-svn: 69115
2009-04-15 00:10:16 +00:00
7913ea5e4a
Add a new MOV8rr_NOREX, and make X86's copyRegToReg use it when
...
either the source or destination is a physical h register.
This fixes sqlite3 with the post-RA scheduler enabled.
llvm-svn: 69111
2009-04-15 00:04:23 +00:00
821e13a8f4
GR8_NOREX can contain the H registers, since they don't require
...
REX prefixes.
llvm-svn: 69108
2009-04-15 00:00:48 +00:00
62f4498646
For the h-register addressing-mode trick, use the correct value for
...
any non-address uses of the address value. This fixes 186.crafty.
llvm-svn: 69094
2009-04-14 22:45:05 +00:00
dfbbf5c043
Some of GR8_NOREX registers are only available in 64-bit mode.
...
llvm-svn: 69049
2009-04-14 16:57:43 +00:00
92bb846e2b
Handle aggregate type arguments to direct and indirect calls.
...
llvm-svn: 69022
2009-04-14 02:49:52 +00:00
6c1426308c
Rename COPY_TO_SUBCLASS to COPY_TO_REGCLASS, and generalize
...
it accordingly. Thanks to Jakob Stoklund Olesen for pointing
out how this might be useful.
llvm-svn: 68986
2009-04-13 21:06:25 +00:00
80be3511ed
Reapply 68847.
...
Now debug_inlined section is covered by TAI->doesDwarfUsesInlineInfoSection(), which is false by default.
llvm-svn: 68964
2009-04-13 17:02:03 +00:00
57d6bd36b2
Implement x86 h-register extract support.
...
- Add patterns for h-register extract, which avoids a shift and mask,
and in some cases a temporary register.
- Add address-mode matching for turning (X>>(8-n))&(255<<n), where
n is a valid address-mode scale value, into an h-register extract
and a scaled-offset address.
- Replace X86's MOV32to32_ and related instructions with the new
target-independent COPY_TO_SUBREG instruction.
On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.
These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.
llvm-svn: 68962
2009-04-13 16:09:41 +00:00
f20462c217
Remove x86's special-case handling for ISD::TRUNCATE and
...
ISD::SIGN_EXTEND_INREG. Tablegen-generated code can handle
these cases, and the scheduling issues observed earlier
appear to be resolved now.
llvm-svn: 68959
2009-04-13 15:29:31 +00:00
e9432dcc0d
Fix copy+pastos in comments.
...
llvm-svn: 68958
2009-04-13 15:28:29 +00:00
9e3eb7bcd9
List the l registers before h registers, for consistency.
...
llvm-svn: 68954
2009-04-13 15:18:42 +00:00
092b8b6fdb
Use X86::SUBREG_8BIT instead of hard-coding the equivalent constant.
...
llvm-svn: 68951
2009-04-13 15:14:03 +00:00
c5c2fc45ae
Add a comment about MOVSX64rr8.
...
llvm-svn: 68950
2009-04-13 15:13:28 +00:00
39aa13a401
Fix another hard-coded constant to use X86AddrNumOperands.
...
This unbreaks the JIT on x86-64.
llvm-svn: 68948
2009-04-13 15:04:25 +00:00
6d6c6043ea
X86-64 TLS support for local exec and initial exec.
...
llvm-svn: 68947
2009-04-13 13:02:49 +00:00
0368bc4703
While passing arg of types larger than char only one byte at lower end was getting passed. We couldn't catch this as we did not have tests that were passing an int value larger than 256.
...
llvm-svn: 68946
2009-04-13 09:38:38 +00:00
184f1be4a8
Add a new "available_externally" linkage type. This is intended
...
to support C99 inline, GNU extern inline, etc. Related bugzilla's
include PR3517, PR3100, & PR2933. Nothing uses this yet, but it
appears to work.
llvm-svn: 68940
2009-04-13 05:44:34 +00:00
7186f20a1b
In X86DAGToDAGISel::MatchWrapper, if base or index are set, avoid matching
...
only if symbolic addresses are RIP relatives.
llvm-svn: 68924
2009-04-12 23:00:38 +00:00
6688b0a5da
refactor some code into X86DAGToDAGISel::MatchWrapper
...
llvm-svn: 68915
2009-04-12 21:55:03 +00:00
ce6bcf0847
fix a cross-block fastisel crash handling overflow intrinsics.
...
See comment for details. This fixes rdar://6772169
llvm-svn: 68890
2009-04-12 07:51:14 +00:00
99a8cb627d
simplify code by using IntrinsicInst.
...
llvm-svn: 68887
2009-04-12 07:36:01 +00:00
24ac95abc1
Add new TargetInstrDesc::hasImplicitUseOfPhysReg and
...
hasImplicitDefOfPhysReg methods. Use them to remove a
look in X86 fast isel.
llvm-svn: 68886
2009-04-12 07:26:51 +00:00
825236b116
Revert r68847. It breaks the build on non-Darwin targets, with this message
...
from the assembler:
Error: unknown pseudo-op: `.debug_inlined'
llvm-svn: 68863
2009-04-11 15:57:04 +00:00
790e60999e
Keep track of inlined functions and their locations. This information is collected when nested llvm.dbg.func.start intrinsics are seen. (Right now, inliner removes nested llvm.dbg.func.start intrinisics during inlining.)
...
Create debug_inlined dwarf section using these information. This info is used by gdb, at least on Darwin, to enable better experience debugging inlined functions. See DwarfWriter.cpp for more information on structure of debug_inlined section.
llvm-svn: 68847
2009-04-11 00:16:47 +00:00
638f400a3c
Added code to handle spilling and reloading of FSRs.
...
llvm-svn: 68783
2009-04-10 15:10:14 +00:00
bb834f0929
Don't fold a load if the other operand is a TLS address.
...
With this we generate
movl %gs:0, %eax
leal i@NTPOFF(%eax), %eax
instead of
movl $i@NTPOFF, %eax
addl %gs:0, %eax
llvm-svn: 68778
2009-04-10 10:09:34 +00:00
428f71623b
a few fixes to "addrspace(256) is reference offset of GS segment register".
...
It turns out that there are still several problems with this, will file a bugzilla.
llvm-svn: 68749
2009-04-10 00:16:23 +00:00
992f846dc7
Pass in the std::string parameter instead of returning it by value.
...
llvm-svn: 68747
2009-04-10 00:12:49 +00:00
de912e2475
Remove the obsolete SelectionDAG::getNodeValueTypes and simplify
...
code that uses it by using SelectionDAG::getVTList instead.
llvm-svn: 68744
2009-04-09 23:54:40 +00:00
5eb8d26f19
Give register alias checking the hash table treatment too.
...
llvm-svn: 68730
2009-04-09 22:19:30 +00:00
51856173c8
Fix pr3954. The register scavenger asserts for inline assembly with
...
register destinations that are tied to source operands. The
TargetInstrDescr::findTiedToSrcOperand method silently fails for inline
assembly. The existing MachineInstr::isRegReDefinedByTwoAddr was very
close to doing what is needed, so this revision makes a few changes to
that method and also renames it to isRegTiedToUseOperand (for consistency
with the very similar isRegTiedToDefOperand and because it handles both
two-address instructions and inline assembly with tied registers).
llvm-svn: 68714
2009-04-09 17:16:43 +00:00
38533d48dd
The way we are trying to figure out banksel immediate operand may yield different results for different type of insns. This will eventually need to be changed but currently let us prevent the crash in cases of incorrect detection of banksel operand.
...
llvm-svn: 68713
2009-04-09 17:06:24 +00:00
60fd2cd503
Arguments to indirect calls were being passed incorrectly. They are not fixed to start after return value.
...
llvm-svn: 68705
2009-04-09 10:29:32 +00:00
bcd2632638
Fix code size computation on x86-64, patch by Zoltan Varga!
...
llvm-svn: 68690
2009-04-09 06:10:51 +00:00
cdfdc79b70
r68576 unconverd a bug in PIC16 port (Thanks to Dan Gohman) where we were custom lowering an ADD to ADDC.
...
llvm-svn: 68671
2009-04-09 04:03:43 +00:00
3a888f639e
Convert TargetRegisterInfo's super-register checking to use a pre-computed hash table just like subregister checking does.
...
llvm-svn: 68669
2009-04-09 03:50:16 +00:00
f15454866c
Fix grammaros in comments.
...
llvm-svn: 68666
2009-04-09 02:06:09 +00:00
3b2df10c9e
Re-apply 68552.
...
Tested by bootstrapping llvm-gcc and using that to build llvm.
llvm-svn: 68645
2009-04-08 21:14:34 +00:00
866c174f79
Fix PR3795: Apply Dan's suggested fix for
...
ARMTargetLowering::isLegalAddressingMode.
llvm-svn: 68619
2009-04-08 17:55:28 +00:00
d173f4237d
Avoid a hard coded constant.
...
llvm-svn: 68603
2009-04-08 08:09:33 +00:00
44ea053a49
Emit .line debug directives for stoppoints. The debug location is retrieved by the MachineInstr itself, rather than by custom handling the DBG_STOPPOINT nodes.
...
llvm-svn: 68602
2009-04-08 06:24:04 +00:00
4b489c75c2
Handle indirect function calls.
...
Every function has the address of its frame in the beginning of code section.
The frame address is retrieved and used to pass arguments.
llvm-svn: 68597
2009-04-08 05:38:48 +00:00
ad3e549a53
Implement support for using modeling implicit-zero-extension on x86-64
...
with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce
SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG
instructions), and teach the DAGCombiner to take advantage of this on
targets which support it. This eliminates many redundant
zero-extension operations on x86-64.
This adds a new TargetLowering hook, isZExtFree. It's similar to
isTruncateFree, except it only applies to actual definitions, and not
no-op truncates which may not zero the high bits.
Also, this adds a new optimization to SimplifyDemandedBits: transform
operations like x+y into (zext (add (trunc x), (trunc y))) on targets
where all the casts are no-ops. In contexts where the high part of the
add is explicitly masked off, this allows the mask operation to be
eliminated. Fix the DAGCombiner to avoid undoing these transformations
to eliminate casts on targets where the casts are no-ops.
Also, this adds a new two-address lowering heuristic. Since
two-address lowering runs before coalescing, it helps to be able to
look through copies when deciding whether commuting and/or
three-address conversion are profitable.
Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle
the case that a clobber range extended both before and beyond an
existing live range. In that case, multiple live ranges need to be
added. This was exposed by the new subreg coalescing code.
Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the
spiller behavior it was looking for no longer occurrs with the new
instruction selection.
llvm-svn: 68576
2009-04-08 00:15:30 +00:00
4aa25b79f9
Temporarily revert r68552. This was causing a failure in the self-hosting LLVM
...
builds.
--- Reverse-merging (from foreign repository) r68552 into '.':
U test/CodeGen/X86/tls8.ll
U test/CodeGen/X86/tls10.ll
U test/CodeGen/X86/tls2.ll
U test/CodeGen/X86/tls6.ll
U lib/Target/X86/X86Instr64bit.td
U lib/Target/X86/X86InstrSSE.td
U lib/Target/X86/X86InstrInfo.td
U lib/Target/X86/X86RegisterInfo.cpp
U lib/Target/X86/X86ISelLowering.cpp
U lib/Target/X86/X86CodeEmitter.cpp
U lib/Target/X86/X86FastISel.cpp
U lib/Target/X86/X86InstrInfo.h
U lib/Target/X86/X86ISelDAGToDAG.cpp
U lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
U lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp
U lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
U lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
U lib/Target/X86/X86ISelLowering.h
U lib/Target/X86/X86InstrInfo.cpp
U lib/Target/X86/X86InstrBuilder.h
U lib/Target/X86/X86RegisterInfo.td
llvm-svn: 68560
2009-04-07 22:35:25 +00:00
1edda06792
Reduce code duplication on the TLS implementation.
...
This introduces a small regression on the generated code
quality in the case we are just computing addresses, not
loading values.
Will work on it and on X86-64 support.
llvm-svn: 68552
2009-04-07 21:37:46 +00:00
fde2110aa9
PR2985 / <rdar://problem/6584986>
...
When compiling in Thumb mode, only the low (R0-R7) registers are available
for most instructions. Breaking the low registers into a new register class
handles this. Uses of R12, SP, etc, are handled explicitly where needed
with copies inserted to move results into low registers where the rest of
the code generator can deal with them.
llvm-svn: 68545
2009-04-07 20:34:09 +00:00
0669f6d295
Handle 'a' modifier in ARM inline assembly.
...
Patch by Richard Pennington.
llvm-svn: 68464
2009-04-06 21:46:51 +00:00
0b08df8c09
Map stack based frameindices for spills to zero based indices that can be accessed based on an external symbol defining the location of temporary data for a function. For example: we have spill slots addressed as foo.tmp + 0, foo.tmp + 1 etc.
...
llvm-svn: 68442
2009-04-06 10:54:50 +00:00
6bedd59894
Wrap some lines to fix indentation problems.
...
llvm-svn: 68405
2009-04-03 21:08:42 +00:00
d24b794f31
Fix some comments.
...
llvm-svn: 68404
2009-04-03 20:53:25 +00:00
f4de47b91e
CMake: removed IA64AsmPrinter.cpp from lib/Target/IA64/CMakeLists.txt
...
llvm-svn: 68384
2009-04-03 12:11:43 +00:00
06d2d8ba72
Separate MIPS asmprinter
...
llvm-svn: 68383
2009-04-03 10:41:41 +00:00
354171f060
Fix target library name
...
llvm-svn: 68382
2009-04-03 10:41:17 +00:00
b1cce77929
Fix comment
...
llvm-svn: 68381
2009-04-03 10:41:00 +00:00
547b43a809
Move IA64 asmprinter to separate library
...
llvm-svn: 68380
2009-04-03 10:38:51 +00:00
9c186c5d27
Added a x86 dag combine to increase the chances to use a
...
movq for v2i64 on x86-32.
llvm-svn: 68368
2009-04-03 02:43:30 +00:00
e9cff3328f
Fixed build warnings.
...
llvm-svn: 68333
2009-04-02 18:33:12 +00:00
cc841a3810
To convert the StopPoint insn into an assembler directive by ISel, we need to have access to the line number field. So we convert that info as an operand by custom handling DBG_STOPPOINT in legalize.
...
llvm-svn: 68329
2009-04-02 18:03:10 +00:00
1e8860a8f5
Params are not being generated as static globals now. The caller passes them onto the callee's stack directly and the callee loads the argvals from its own stack. Clang generated frameindexes validatd by recalculating the stack as if all frameindexes represent 1-byte slots.
...
llvm-svn: 68327
2009-04-02 17:42:00 +00:00
d2eb0a63a1
silence warning in release-asserts build.
...
llvm-svn: 68253
2009-04-01 22:14:45 +00:00
cff6953c45
Use CHAR_BIT instead of hard-coding 8 in several places where it
...
is appropriate. This helps visually differentiate host-oriented
calculations from target-oriented calculations.
llvm-svn: 68227
2009-04-01 18:45:54 +00:00
0170402fe8
Use LLVM type names instead of C type names in comments, to be
...
less ambiguous and less C-specific.
llvm-svn: 68219
2009-04-01 18:10:16 +00:00
cf1ec2cc68
Fix PR3862: Recognize some ARM-specific constraints for immediates in inline
...
assembly.
llvm-svn: 68218
2009-04-01 17:58:54 +00:00
d9d6e427d6
i128 shift libcalls are not available on x86.
...
llvm-svn: 68133
2009-03-31 19:38:51 +00:00
6b42dfddf4
Reapply 68073, with fixes. EH Landing-pad basic blocks are not
...
entered via fall-through. Don't miss fallthroughs from blocks
terminated by conditional branches. Also, move
isOnlyReachableByFallthrough out of line.
llvm-svn: 68129
2009-03-31 18:39:13 +00:00
9277379fc0
remove unused arguments.
...
llvm-svn: 68109
2009-03-31 16:16:57 +00:00
6afae239c2
Really temporarily revert r68073.
...
llvm-svn: 68100
2009-03-31 08:42:40 +00:00
b8017e02ca
Oy! When reverting r68073, I added in experimental code. Sorry...
...
llvm-svn: 68099
2009-03-31 08:41:31 +00:00
c4b08e5eb0
Revert r68073. It's causing a failure in the Apple-style builds.
...
llvm-svn: 68092
2009-03-31 08:26:26 +00:00
885bc6de52
X86 address mode isel tweak. If the base of the address is also used by a CopyToReg (i.e. it's likely live-out), do not fold the sub-expressions into the addressing mode to avoid computing the address twice. The CopyToReg use will be isel'ed to a LEA, re-use it for address instead.
...
This is not yet enabled.
llvm-svn: 68082
2009-03-31 01:13:53 +00:00
adccd30533
Except in asm-verbose mode, avoid printing labels for blocks that are
...
only reachable via fall-through edges. This dramatically reduces the
number of labels printed, and thus also the number of labels the
assembler must parse and remember.
llvm-svn: 68073
2009-03-30 22:55:17 +00:00
a84a318873
When optimzing a mul by immediate into two, the resulting mul's should get a x86 specific node to avoid dag combiner from hacking on them further.
...
llvm-svn: 68066
2009-03-30 21:36:47 +00:00
57178e8822
Fix comment to match function name.
...
llvm-svn: 68050
2009-03-30 18:49:37 +00:00
56709fdffe
Fix thinko: put stuff with both global and local relocations into data.rel{.ro}, not .local
...
llvm-svn: 68036
2009-03-30 17:37:43 +00:00
7c5f3c40ca
Do not propagate ELF-specific stuff (data.rel) into other targets. This simplifies code and also ensures correctness.
...
llvm-svn: 68032
2009-03-30 15:27:43 +00:00
c247fd396c
Add data.rel stuff
...
llvm-svn: 68031
2009-03-30 15:27:03 +00:00
bea241a5f5
IA64 is as weird as Alpha wrt r/o relocs :)
...
llvm-svn: 68007
2009-03-29 17:14:35 +00:00
014a86f216
Alpha always requires global relocations to be r/w regardless of PIC.
...
llvm-svn: 68006
2009-03-29 17:14:14 +00:00
088ebede53
Honour relocation behaviour stuff for ro objects
...
llvm-svn: 68005
2009-03-29 17:13:49 +00:00
356d974a93
add a note
...
llvm-svn: 67953
2009-03-28 19:26:55 +00:00
1f11c3c36f
Use array_lengthof
...
llvm-svn: 67950
2009-03-28 19:02:18 +00:00
6ff3dabbb4
Have only one definition of X86AddrNumOperands.
...
llvm-svn: 67949
2009-03-28 18:55:31 +00:00
c2a17d3022
Make code a bit less brittle by no hardcoding the number
...
of operands in an address in so many places.
llvm-svn: 67945
2009-03-28 17:03:24 +00:00
fd81c73cde
Optimize some 64-bit multiplication by constants into two lea's or one lea + shl since imulq is slow (latency 5). e.g.
...
x * 40
=>
shlq $3, %rdi
leaq (%rdi,%rdi,4), %rax
This has the added benefit of allowing more multiply to be folded into addressing mode. e.g.
a * 24 + b
=>
leaq (%rdi,%rdi,2), %rax
leaq (%rsi,%rax,8), %rax
llvm-svn: 67917
2009-03-28 05:57:29 +00:00
669f1d0b0b
remove trailing whitespace
...
llvm-svn: 67874
2009-03-27 23:06:27 +00:00
705f2a6cd2
Avoid hardcoding that X86 addresses have 4 operands.
...
llvm-svn: 67848
2009-03-27 15:57:50 +00:00
227815437a
Use less hard coded constants to make the code less brittle.
...
llvm-svn: 67846
2009-03-27 15:45:05 +00:00
e728019392
I am trying to add a segment to the X86 addresses matching to
...
improve TLS support (see http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20090309/075220.html ), but that code is VERY brittle.
This patch just makes it a bit more resistant.
llvm-svn: 67843
2009-03-27 15:26:30 +00:00
d88ebc352c
-no-implicit-float means explicit fp operations are legal.
...
llvm-svn: 67784
2009-03-26 23:06:32 +00:00
904f14663d
tADDhirr is a thumb instruction. Do not allow this code to be reached in non-thumb mode.
...
llvm-svn: 67765
2009-03-26 19:09:01 +00:00
aa28be652c
Pull transform from target-dependent code into target-independent code.
...
llvm-svn: 67742
2009-03-26 06:14:09 +00:00
78b7cbe668
fix warning in -asserts mode.
...
llvm-svn: 67739
2009-03-26 05:29:34 +00:00
f38fd11a26
fix some warnings in release-asserts mode.
...
llvm-svn: 67738
2009-03-26 05:28:26 +00:00
3c04970f31
fix an apparently real bug exposed by a warning in -asserts mode.
...
llvm-svn: 67737
2009-03-26 05:28:14 +00:00
3871781c7b
fix warning in -asserts build.
...
llvm-svn: 67736
2009-03-26 05:25:59 +00:00
94f299f2c5
Match this pattern so that we can generate simpler code:
...
%a = ...
%b = and i32 %a, 2
%c = srl i32 %b, 1
%d = br i32 %c,
into
%a = ...
%b = and %a, 2
%c = X86ISD::CMP %b, 0
%d = X86ISD::BRCOND %c ...
This applies only when the AND constant value has one bit set and the SRL
constant is equal to the log2 of the AND constant. The back-end is smart enough
to convert the result into a TEST/JMP sequence.
llvm-svn: 67728
2009-03-26 01:47:50 +00:00
189d67181c
Doxygen-ify comments.
...
llvm-svn: 67727
2009-03-26 01:46:56 +00:00
2755edf4c4
do not rely on callee being operand 0
...
llvm-svn: 67681
2009-03-25 06:32:59 +00:00
5e5a63cf8f
CodeGen still defaults to non-verbose asm, but llc now overrides it and default to verbose.
...
llvm-svn: 67668
2009-03-25 01:47:28 +00:00
9966403e90
Don't print global names twice with -asm-verbose.
...
llvm-svn: 67667
2009-03-25 01:08:42 +00:00
efd2d44aa5
I was convinced that it's ok to allow a second i8 return value
...
to be returned in DL. LLVM's multiple-return-value support is
not ABI-conforming; front-ends that wish to have code emitted
that conforms to an ABI are currently expected to make
arrangements for this on their own rather than assuming that
multiple-return-values will automatically do the right thing.
This commit doesn't fundamentally change this situation.
llvm-svn: 67588
2009-03-24 01:04:34 +00:00
a774a99245
Do not emit comments unless -asm-verbose.
...
llvm-svn: 67580
2009-03-24 00:17:40 +00:00
Anton Korobeynikov