Commit Graph

429234 Commits

Author SHA1 Message Date
Matt Arsenault 02769f2b3f AArch64/GlobalISel: Stop using legal s1 values
As far as I can tell treating s1 values as legal makes no sense. There
are no allocatable 1-bit registers. SelectionDAG legalizes the usual
set of boolean operations to 32-bits, and this should do the
same. This avoids some special case handling in the selector of s1
values, and some extra code to look through truncates.

This makes some code worse at -O0, since nothing cleans up the and 1
the artifact combiner inserts. We could probably add some
non-essential combines or teach the artifact combiner to elide
intermediates betweeen boolean uses and defs.
2022-07-08 11:55:08 -04:00
Matt Arsenault 13ac4c3de9 GlobalISel: Add buildBoolExtInReg helper 2022-07-08 11:55:08 -04:00
Matt Arsenault e9a45d45d0 GlobalISel: Allow forming atomic/volatile G_SEXTLOAD
Mirror the change to G_ZEXTLOAD.
2022-07-08 11:55:08 -04:00
Matt Arsenault 1ee6ce9bad GlobalISel: Allow forming atomic/volatile G_ZEXTLOAD
SelectionDAG has a target hook, getExtendForAtomicOps, which it uses
in the computeKnownBits implementation for ATOMIC_LOAD. This is pretty
ugly (as is having a separate load opcode for atomics), so instead
allow making use of atomic zextload. Enable this for AArch64 since the
DAG path defaults in to the zext behavior.

The tablegen changes are pretty ugly, but partially helps migrate
SelectionDAG from using ISD::ATOMIC_LOAD to regular ISD::LOAD with
atomic memory operands. For now the DAG emitter will emit matchers for
patterns which the DAG will not produce.

I'm still a bit confused by the intent of the isLoad/isStore/isAtomic
bits. The DAG implementation rejects trying to use any of these in
combination. For now I've opted to make the isLoad checks also check
isAtomic, although I think having isLoad and isAtomic set on these
makes most sense.
2022-07-08 11:55:08 -04:00
Joseph Huber 0d7161af89 [Clang] Fix test failing due to renamed arg 2022-07-08 11:50:56 -04:00
Nikita Popov d686ea32b1 [ConstantFolding] Guard against unfolded FP binop
Check that the operation actually folded before trying to flush
denormals. A minor variation of the pr33453 test exposed this
with the FP binops marked as undesirable.
2022-07-08 17:45:33 +02:00
Joseph Huber 74a8fce6e8 [LinkerWrapper] Fix save-temps and argument name
Summary:
The previous path reworked some handling of temporary files which
exposed some bugs related to capturing local state by reference in the
callback labmda. Squashing this by copying in everything instead. There
was also a problem where the argument name was changed for
`--bitcode-library=` but clang still used `--target-library=`.
2022-07-08 11:38:33 -04:00
Nikita Popov d287051404 [InstCombine] Avoid ConstantExpr::get() in vector binop fold (NFCI)
Use the ConstantFoldBinaryOpOperands() API instead. This case
would bail out on a non-folded result anyway.
2022-07-08 17:20:14 +02:00
Joseph Huber e0de264f63 [LinkerWrapper][NFC] Move error handling to a common function
Summary:
This patch merges all the error handling functions to a single function
call so we don't define the same lambda many times.
2022-07-08 11:18:38 -04:00
Joseph Huber d2ead9e324 [LinkerWrapper][NFC] Rework command line argument handling in the linker wrapper
Summary:
This patch reworks the command line argument handling in the linker
wrapper from using the LLVM `cl` interface to using the `Option`
interface with TableGen. This has several benefits compared to the old
method.

We use arguments from the linker arguments in the linker
wrapper, such as the libraries and input files, this allows us to
properly parse these. Additionally we can now easily set up aliases to
the linker wrapper arguments and pass them in the linker input directly.
That is, pass an option like `cuda-path=` as `--offload-arg=cuda-path=`
in the linker's inputs. This will allow us to handle offloading
compilation in the linker itself some day. Finally, this is also a much
cleaner interface for passing arguments to the individual device linking
jobs.
2022-07-08 11:18:38 -04:00
Nikita Popov 29c6bf45c3 [InstCombine] Avoid ConstantExpr::get() call
Avoid calling ConstantExpr::get() for associative/commutative
binops, call ConstantFoldBinaryOpOperands() instead. We only
want to perform the reassociation of the constants actually fold.
2022-07-08 17:13:06 +02:00
Simon Pilgrim b53046122f [DAG] SimplifyDemandedBits - fold AND(INSERT_SUBVECTOR(C,X,I),M) -> INSERT_SUBVECTOR(AND(C,M),X,I)
If all the demanded bits of the AND mask covering the inserted subvector 'X' are known to be one, then the mask isn't affecting the subvector at all.

In which case, if the base vector 'C' is undef/constant, then move the AND mask up to just (constant) fold it directly.

Addresses some of the regressions from D129150, particularly the cases where we're attempting to zero the upper elements of a widened vector.

Differential Revision: https://reviews.llvm.org/D129290
2022-07-08 16:08:31 +01:00
Ye Luo fca79b78c4 [libomptarget] compile DeviceRTL bc files with -O3
bc files of DeviceRTL are compiled with -O3, the same as the static library.

Differential Revision: https://reviews.llvm.org/D129344
2022-07-08 10:00:26 -05:00
Nikita Popov 8edb9c3c56 [ConstantExpr] Don't create float binop expressions
Mark the fadd, fsub, fmul, fdiv, and frem expressions as
undesirable, so they are not created automatically. This is in
preparation for their removal.
2022-07-08 16:53:46 +02:00
Nikita Popov fc18a88231 [InstCombine] Avoid creating float binop ConstantExprs
Replace ConstantExpr:getFAdd etc with call to
ConstantFoldBinaryOpOperands(). I'm using the constant folding API
rather than IRBuilder here to ensure that this does actually
constant fold. These transforms don't use m_ImmConstant(), so this
would not otherwise be guaranteed (and apparently, they can't use
m_ImmConstant because they want to handle scalable vector splats).

There is an opportunity here to further migrate these to the
ConstantFoldFPInstOperands() API, which would respect the denormal
mode. I've held off on doing so here, because some of this code
explicitly checks for denormal results, and I don't want to touch
it in a mostly NFC change.
2022-07-08 16:36:04 +02:00
Sanjay Patel 79bb915fb6 [InstCombine] enhance fold for subtract-from-constant -> xor
A low-bit mask is not required:
https://alive2.llvm.org/ce/z/yPShss

This matches the SDAG implementation that was updated at:
8b75671314
2022-07-08 10:02:19 -04:00
Sanjay Patel 0cf5d40d4c [InstCombine] add tests for masked sub; NFC 2022-07-08 10:02:19 -04:00
Valentin Clement 015834e455
[flang][openacc][NFC] Extract device_type parser to its own
Move the device_type parser to a separate parser AccDeviceTypeExprList. Preparatory work for D106968.

Reviewed By: kiranchandramohan

Differential Revision: https://reviews.llvm.org/D106967
2022-07-08 16:02:04 +02:00
Valentin Clement 36e24da8eb
[flang][openacc][NFC] Make self clause value optional in ACC.td and extract the parser
Set the isOptional flag for the self clause. Move the optional and parenthesis part of the parser. Update the rest of the code to deal with the optional value.

Preparatory work for D106968.

Reviewed By: kiranchandramohan

Differential Revision: https://reviews.llvm.org/D106965
2022-07-08 15:45:12 +02:00
Cullen Rhodes d1c51d45f0 [AArch64] Use Neoverse N2 sched model as default for:
- Cortex-A710
  - Cortex-X2
  - Neoverse-V1
  - Neoverse-512tvb

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D129203
2022-07-08 13:34:13 +00:00
Daniil Fukalov 6858a17f66 [LiveIntervals] Fix incorrect range (re)construction from subranges.
After D82916 `updateAllRanges()` started to fix holes in main range with
subranges but it fails on instructions with two subregs def which are parts of
one reg. The main range constructed with //all// subranges of subregs just after
processing the first operand. So the main range gets intervals from subranges
those are not updated yet.

The patch takes into account lane mask to update the main range.

Reviewed By: rampitec, arsenm

Differential Revision: https://reviews.llvm.org/D128553
2022-07-08 16:07:19 +03:00
LLVM GN Syncbot fad7d53a5f [gn build] Port 1cdec6c96e 2022-07-08 12:39:02 +00:00
Louis Dionne d2e86866be [libc++] Re-apply the use of ABI tags to provide per-TU insulation
This commit re-applies 9ee97ce3b8, which was reverted by 61d417ce
because it broke the LLDB data formatter tests. It also re-applies
6148c79a (the manual GN change associated to it).

Differential Revision: https://reviews.llvm.org/D127444
2022-07-08 08:38:36 -04:00
Phoebe Wang 8fb083d33e [X86][FP16] Add constrained FP support for scalar emulation
This is a follow up patch to support constrained FP in FP16 emulation.

Reviewed By: skan

Differential Revision: https://reviews.llvm.org/D128114
2022-07-08 20:33:42 +08:00
Hui Xie 1cdec6c96e [libcxx][ranges] implement `std::ranges::set_difference`
implement `std::ranges::set_difference`
reused classic std::set_difference
added unit tests

Differential Revision: https://reviews.llvm.org/D128983
2022-07-08 13:26:23 +01:00
Sanjay Patel 8b75671314 [SDAG] try to replace subtract-from-constant with xor
This is almost the same as the abandoned D48529, but it
allows splat vector constants too.

This replaces the x86-specific code that was added with
the alternate patch D48557 with the original generic
combine.

This transform is a less restricted form of an existing
InstCombine and the proposed SDAG equivalent for that
in D128080:
https://alive2.llvm.org/ce/z/OUm6N_

Differential Revision: https://reviews.llvm.org/D128123
2022-07-08 08:14:24 -04:00
Aaron Ballman fee77a2073 Disable clang-format entirely for test directories
See discussion here:

https://github.com/llvm/llvm-project/issues/55982

And the RFC here:
https://discourse.llvm.org/t/rfc-disable-clang-format-in-the-clang-test-tree/63498/2

We don't generally expect test files to be formatted according to the
style guide. Indeed, some tests may require specific formatting for the
purposes of the test.

When tests intentionally do not conform to the "correct" formatting,
this causes errors in the CI, which can drown out real errors and causes
people to stop trusting the CI over time.

From the history of the clang/test/.clang-format file, it looks as if
there have been attempts to make clang-format do a subset of formatting
that would be useful for tests. However, it looks as if it's hard to
make clang-format do exactly the right thing -- see the back-and-forth
between
13316a7
and
7b5bddf.

These changes disable the .clang-format file for clang/test, llvm/test,
and clang-tools-extra/test.

Fixes #55982
Differential Revision: https://reviews.llvm.org/D128706
2022-07-08 07:34:18 -04:00
Aaron Ballman 35f48572e3 Fix the Clang sphinx bot
This should resolve the issues with:
https://lab.llvm.org/buildbot/#/builders/92/builds/29439
2022-07-08 07:23:40 -04:00
OCHyams 6b62ca9043 [NFC][SelectionDAG] Fix debug prints in salvageUnresolvedDbgValue
The prints are printing pointer values - fix by dereferencing the pointers.
2022-07-08 12:09:30 +01:00
Nikita Popov 11541aa9fd [PhaseOrdering] Add test for IndVars + SROA interaction (NFC) 2022-07-08 13:04:24 +02:00
Jay Foad 8fc8bf59f2 [AMDGPU] Add GFX11 test coverage sharing checks with GFX10 2022-07-08 11:56:49 +01:00
David Green 4334cbd49b [AArch64] Remove incorrect use of DemandElts
This call to computeKnownBits was passing in a 0xff mask, looking like
it was expecting it to be used as a DemandBits, not a DemandElts mask.
2022-07-08 11:38:00 +01:00
serge-sans-paille 132d711554 [lldb/test] Disable TestStringLiteralExpr.test on Windows
This test, introduced by b042d15d2e, fails on
https://lab.llvm.org/buildbot/#/builders/83/builds/20933/steps/7/logs/stdio

but succeeds on other targets, see for instance
https://lab.llvm.org/buildbot/#/builders/68/builds/35462/steps/6/logs/stdio

This test is not be arch specific, just disabling it on Windows.
2022-07-08 12:17:31 +02:00
Kito Cheng 5c45ae4108 [RISCV] Fix wrong register rename for store value during make-compressible optimization
Current implementation will rename both register in store instructions if
we store base address into memory with same base register, it's OK if
the offset is 0, however that is wrong transform if offset isn't 0, give
a smalle example here:

sd      a0, 808(a0)

We should not transform into:

addi    a2, a0, 768
sd      a2, 40(a2)

That should just rename base address like this:

addi    a2, a0, 768
sd      a0, 40(a2)

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D128876
2022-07-08 18:07:17 +08:00
Jay Foad de3b5d7316 [AMDGPU] More GFX11 coverage for tests with generated checks 2022-07-08 11:06:02 +01:00
Cullen Rhodes 03af9ba680 [AArch64] Initial sched model for Neoverse N2
The optimization guide can be found here:
https://developer.arm.com/documentation/PJDOC-466751330-18256/latest/

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D128631
2022-07-08 09:39:13 +00:00
Andrew Ng 86a2f2e2db [Support] Fix Windows dump file hang with multi-threaded crashes
Prevents deadlock between MiniDumpWriteDump and
CryptAcquireContextW (called via fs::createTemporaryFile) in
WriteWindowsDumpFile.

However, there's no guarantee that deadlock can't still occur between
MiniDumpWriteDump and some other Win32 API call. But that would appear
to be the "accepted" risk of using MiniDumpWriteDump in this manner.

Differential Revision: https://reviews.llvm.org/D129004
2022-07-08 10:31:35 +01:00
Weining Lu 1d27f26426 [LoongArch] Add codegen support for multiplication operations
Reference:
https://llvm.org/docs/LangRef.html#mul-instruction

Differential Revision: https://reviews.llvm.org/D128194
2022-07-08 17:15:17 +08:00
zhongyunde 716e1b856a [IndVars] Eliminate redundant type cast between integer and float
Recompute the range: match for fptosi of sitofp, and then query the range of the input to the sitofp
according the comment on D129140.

Fixes https://github.com/llvm/llvm-project/issues/55505.

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D129191
2022-07-08 17:07:20 +08:00
Kito Cheng 7b9a3b9d6d [RISCV] Precommit testcase to show wrong result of make-compressible optimization
Use following example to demo what happened now:

  li      a1, 1
  sd      a1, 800(a0)
  sd      a0, 808(a0) # Store base address into base + offset
  li      a1, 2
  sd      a1, 816(a0)

Current will optimizate into:

  li      a1, 1
  addi    a2, a0, 768
  sd      a1, 32(a2)
  sd      a2, 40(a2) # Wrong replacement for the source register.
  li      a1, 2
  sd      a1, 48(a2)

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D128875
2022-07-08 17:01:22 +08:00
Jay Foad a59c3eb2f3 [AMDGPU] Add GFX11 coverage to shared sdag/gisel tests 2022-07-08 09:40:20 +01:00
Petar Avramovic 2483f43d47 [AArch64][GlobalISel] Fix call lowering for <3 x i32> vector arguments
Differential Revision: https://reviews.llvm.org/D129194
2022-07-08 10:25:45 +02:00
Sergei Barannikov 2247fdc84d [SelectionDAG] computeKnownBits / ComputeNumSignBits for the remaining overflow-aware nodes
Some overflow-aware nodes were missing from the switches in
computeKnownBits and ComputeNumSignBits.
2022-07-08 09:19:19 +01:00
Jay Foad 5cae88164e [AMDGPU] Add GFX11 test coverage
Add GFX11 test coverage to a bunch of tests where it was easy to do so,
mostly because the checks are autogenerated and/or GFX11 can share the
same checks as GFX10.

Differential Revision: https://reviews.llvm.org/D129295
2022-07-08 09:13:59 +01:00
Jesus Checa Hidalgo b042d15d2e [lldb/test] Add Shell/Expr/TestStringLiteralExpr.test
This test should exercise the usage of expressions containing
string literals and ensure that lldb doesn't crash.

Differential Revision: https://reviews.llvm.org/D129261
2022-07-08 10:01:07 +02:00
Nicolas Vasilache 69c8319e76 [mlir][Transform] Fix isDefiniteFailure helper
This newly added helper was returning definiteFailure even in the case of silenceableFailure.

Differential Revision: https://reviews.llvm.org/D129347
2022-07-08 00:39:42 -07:00
ChenYang Li 6d036b83d1 [JumpThreading] Avoid threadThroughTwoBasicBlocks when PredPred BB ends with indirectbranch
Since we can't change the destination of indirectbr, so when
encounter indirectbr as PredPredBB terminator, we should pass it.

Differential Revision: https://reviews.llvm.org/D129193
2022-07-08 09:29:17 +02:00
Nikita Popov 116c29a386 [CallSiteSplitting] Regenerate test checks (NFC)
This test requires --function-signature to work with unmodified UTC.
2022-07-08 09:24:11 +02:00
Nikita Popov 34a5c2bcf2 [BasicBlockUtils] Allow critical edge splitting with callbr terminators
After D129205, we support SplitBlockPredecessors() for predecessors
with callbr terminators. This means that it is now also safe to
invoke critical edge splitting for an edge coming from a callbr
terminator. Remove checks in various passes that were protecting
against that.

Differential Revision: https://reviews.llvm.org/D129256
2022-07-08 09:20:44 +02:00
Nikita Popov 9b37d48dd9 [UpdateTestChecks] Remove outdated help text
Manually modifying the result of update_test_checks.py is discouraged,
we prefer unmodified check lines where possible. The output is also
considered authoritative nowadays, at least for tests targeting core
middle-end components, where not using it is an automatic review
rejection.

Differential Revision: https://reviews.llvm.org/D129259
2022-07-08 09:19:16 +02:00