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59 Commits

Author SHA1 Message Date
NAKAMURA Takumi 0b865d445e Prune trailing linefeeds. 
llvm-svn: 193511
 2013-10-28 04:07:31 +00:00
Jyotsna Verma 2dca82ad1c Hexagon: Add patterns to generate 'combine' instructions. 
llvm-svn: 181805
 2013-05-14 17:16:38 +00:00
Jyotsna Verma 300f0b966c Hexagon: Fix switch cases in HexagonVLIWPacketizer.cpp. 
llvm-svn: 181624
 2013-05-10 20:27:34 +00:00
Jyotsna Verma a03eb9b5d5 Hexagon: Set accessSize and addrMode on all load/store instructions. 
llvm-svn: 181324
 2013-05-07 15:06:29 +00:00
Jyotsna Verma 84c471029b Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions. 
llvm-svn: 181235
 2013-05-06 18:49:23 +00:00
Jyotsna Verma a841af7556 reverting r180953 
llvm-svn: 180964
 2013-05-02 22:10:59 +00:00
Jyotsna Verma 7e7c730c4f Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions. 
llvm-svn: 180953
 2013-05-02 21:21:57 +00:00
Jyotsna Verma 5ed5181178 Hexagon: Use multiclass for Jump instructions. 
llvm-svn: 180885
 2013-05-01 21:37:34 +00:00
Jyotsna Verma af2359b98c Hexagon: Use multiclass for combine and STri[bhwd]_shl_V4 instructions. 
llvm-svn: 180145
 2013-04-23 21:17:40 +00:00
Jyotsna Verma f00aab98a0 Hexagon: Define relations for GP-relative instructions. 
No functionality change.

llvm-svn: 180144
 2013-04-23 21:05:55 +00:00
Jyotsna Verma a696239bec Hexagon: Remove duplicate instructions to handle global/immediate values 
for absolute/absolute-set addressing modes.

llvm-svn: 180120
 2013-04-23 17:11:46 +00:00
Jyotsna Verma ce1be1130f Hexagon: Set isPredicatedNew flag on predicate new instructions. 
llvm-svn: 179388
 2013-04-12 18:01:06 +00:00
Jyotsna Verma bea8327fcb Hexagon: Set isPredicatedFlase flag for all the instructions with negated predication. 
llvm-svn: 179387
 2013-04-12 17:46:52 +00:00
Jyotsna Verma 93e740485f Hexagon: Use multiclass for gp-relative instructions. 
Remove noV4T gp-relative instructions.

llvm-svn: 178246
 2013-03-28 16:25:57 +00:00
Jyotsna Verma 15957b129f Hexagon: Use multiclass for aslh, asrh, sxtb, sxth, zxtb and zxth. 
llvm-svn: 178032
 2013-03-26 15:43:57 +00:00
Jyotsna Verma fdc660bf2e Hexagon: Add and enable memops setbit, clrbit, &,|,+,- for byte, short, and word. 
llvm-svn: 177747
 2013-03-22 18:41:34 +00:00
Jyotsna Verma 7825e064b9 Hexagon: Add patterns for zero extended loads from i1->i64. 
llvm-svn: 176689
 2013-03-08 14:15:15 +00:00
Jyotsna Verma 2ba0c0b927 Hexagon: Add support to lower block address. 
llvm-svn: 176637
 2013-03-07 19:10:28 +00:00
Jyotsna Verma 457801f7ab reverting patch 176508. 
llvm-svn: 176513
 2013-03-05 20:29:23 +00:00
Jyotsna Verma 7179e712dd Hexagon: Add support for lowering block address. 
llvm-svn: 176508
 2013-03-05 19:37:46 +00:00
Jyotsna Verma a556848131 Hexagon: Set appropriate TSFlags to the loads/stores with global address to 
support constant extension.

This patch doesn't introduce any functionality changes.

llvm-svn: 175280
 2013-02-15 17:52:07 +00:00
Jyotsna Verma 3545d2fc41 Hexagon: Use multiclass for absolute addressing mode loads. 
This patch doesn't introduce any functionality changes.

llvm-svn: 175187
 2013-02-14 18:15:29 +00:00
Jyotsna Verma d92252469e Hexagon: Use absolute addressing mode loads/stores for global+offset 
instead of redefining separate instructions for them.

llvm-svn: 175086
 2013-02-13 21:38:46 +00:00
Jyotsna Verma 6031625b03 Hexagon: Use TFR_cond with cmpb.[eq,gt,gtu] to handle 
zext( set[ne,eq,gt,ugt] (...) ) type of dag patterns.

llvm-svn: 174429
 2013-02-05 19:20:45 +00:00
Jyotsna Verma 50ca6dd8a7 Hexagon: Use multiclass for absolute addressing mode stores. 
llvm-svn: 174412
 2013-02-05 18:15:34 +00:00
Jyotsna Verma 6f635b5488 Hexagon: Add V4 compare instructions. Enable relationship mapping 
for the existing instructions.

llvm-svn: 174389
 2013-02-05 16:42:24 +00:00
Jyotsna Verma 7ab68fbd1d Hexagon: Add V4 combine instructions and some more Def Pats for V2. 
llvm-svn: 174331
 2013-02-04 15:52:56 +00:00
Jyotsna Verma 2ceafa6684 Replace LDriu*[bhdw]_indexed_V4 instructions with "def Pats". 
llvm-svn: 174193
 2013-02-01 16:36:16 +00:00
Jyotsna Verma d6eda1c227 Add appropriate TSFlags to the instructions that must be always extended. 
llvm-svn: 174186
 2013-02-01 15:54:43 +00:00
Jyotsna Verma b16a9cb132 Use multiclass for post-increment store instructions. 
llvm-svn: 173816
 2013-01-29 18:42:41 +00:00
Jyotsna Verma a609b1c89d Add constant extender support for MInst type instructions. 
llvm-svn: 173813
 2013-01-29 18:18:50 +00:00
Craig Topper ae65212a4b Remove more unnecessary # operators with nothing to paste proceeding them. 
llvm-svn: 171702
 2013-01-07 06:14:20 +00:00
Craig Topper a8c5ec09c7 Remove # from the beginning and end of def names. The # is a paste operator and should only be used with something to paste on either side. 
llvm-svn: 171697
 2013-01-07 05:45:56 +00:00
Jyotsna Verma 56605448f2 Add constant extender support to GP-relative load/store instructions. 
llvm-svn: 170672
 2012-12-20 06:52:46 +00:00
Jyotsna Verma bf75aaf53e Add TSFlags to ALU32 type instructions for constant-extender/Relationship maps. 
llvm-svn: 170671
 2012-12-20 06:45:39 +00:00
Jyotsna Verma 92e71918b1 Use multiclass for new-value store instructions with MEMri operand. 
llvm-svn: 169814
 2012-12-11 05:12:25 +00:00
Jyotsna Verma d3746e6895 Define new-value store instructions with base+immediate addressing mode 
using multiclass.

llvm-svn: 169432
 2012-12-05 22:02:56 +00:00
Jyotsna Verma 90295156d8 Use multiclass to define store instructions with base+immediate offset 
addressing mode and immediate stored value.

llvm-svn: 169408
 2012-12-05 19:32:03 +00:00
Jyotsna Verma 4da904c8f8 Define store instructions with base+register offset addressing mode 
using multiclass.

llvm-svn: 169314
 2012-12-04 21:58:25 +00:00
Jyotsna Verma dfd779e108 Add patterns to define 'combine', 'tstbit', 'ct0/cl0' (count trailing/leading zeros) 
instructions.

llvm-svn: 169287
 2012-12-04 18:05:01 +00:00
Jyotsna Verma 6f3bd03e50 Define store instructions with base+immediate offset addressing mode 
using multiclass.

llvm-svn: 169168
 2012-12-03 22:26:28 +00:00
Jyotsna Verma b950ea61fc Use multiclass for the store instructions with MEMri operand. 
llvm-svn: 168983
 2012-11-30 06:10:22 +00:00
Jyotsna Verma ede608cce0 Use multiclass for the load instructions with 'base + register offset' 
addressing mode.

llvm-svn: 168976
 2012-11-30 04:19:09 +00:00
Jyotsna Verma c6f2465b5d Removing some unused instruction definitions from the Hexagon backend. 
llvm-svn: 168388
 2012-11-20 22:14:23 +00:00
Jyotsna Verma 6649360860 Added multiclass for post-increment load instructions. 
llvm-svn: 167974
 2012-11-14 20:38:48 +00:00
Jakob Stoklund Olesen ed6c0408fa Remove variable_ops from call instructions in most targets. 
Call instructions are no longer required to be variadic, and
variable_ops should only be used for instructions that encode a variable
number of arguments, like the ARM stm/ldm instructions.

llvm-svn: 160189
 2012-07-13 20:44:29 +00:00
Brendon Cahoon f6b687e5d1 Revert 156634 upon request until code improvement changes are made. 
llvm-svn: 156775
 2012-05-14 19:35:42 +00:00
Brendon Cahoon 31f8723ef3 Hexagon constant extender support. 
Patch by Jyotsna Verma.

llvm-svn: 156634
 2012-05-11 19:56:59 +00:00
Sirish Pande 1c9f7dbc10 Update load/store instruction patterns in Hexagon V4. 
llvm-svn: 156411
 2012-05-08 19:50:20 +00:00
Sirish Pande c92c31674e Extensions of Hexagon V4 instructions. 
This adds new instructions for Hexagon V4 architecture.

llvm-svn: 156071
 2012-05-03 16:18:50 +00:00