d3917157d5
Instead of emitting an implicit use for the super-register of
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X86::CL that was used, emit an EXTRACT_SUBREG from the CL
super-register to CL. This more precisely describes how the
CL register is being used.
llvm-svn: 57264
2008-10-07 21:50:36 +00:00
b01a9c94d4
Fix X86FastISel to handle dynamic allocas that have avoided
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getting inserted into the ValueMap. This avoids infinite
recursion in some rare cases.
llvm-svn: 56989
2008-10-03 01:27:49 +00:00
1ab1d31f7a
Optimize conditional branches in X86FastISel. This replaces
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sequences like this:
sete %al
testb %al, %al
jne LBB11_1
with this:
je LBB11_1
llvm-svn: 56969
2008-10-02 22:15:21 +00:00
b158fd751c
Work around an interaction between fast-isel and regalloc=local. The
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local register allocator's physreg liveness doesn't recognize subregs,
so it doesn't know that defs of %ecx that are immediately followed by
uses of %cl aren't dead. This comes up due to the way fast-isel emits
shift instructions.
This is a temporary workaround. Arguably, local regalloc should
handle subreg references correctly. On the other hand, perhaps
fast-isel should use INSERT_SUBREG instead of just assigning to the
most convenient super-register of %cl when lowering shifts.
This fixes MultiSource/Benchmarks/MallocBench/espresso,
MultiSource/Applications/hexxagon, and others, under -fast.
llvm-svn: 56947
2008-10-02 14:56:12 +00:00
6388dde98e
Split x86's ADJCALLSTACK instructions into 32-bit and 64-bit forms.
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This allows the 64-bit forms to use+def RSP instead of ESP. This
doesn't fix any real bugs today, but it is more precise and it
makes the debug dumps on x86-64 look more consistent.
Also, add some comments describing the CALL instructions' physreg
operand uses and defs.
llvm-svn: 56925
2008-10-01 18:28:06 +00:00
8392f0c75d
Fix X86FastISel's output for x86-32 PIC constant pool addresses.
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llvm-svn: 56829
2008-09-30 01:21:32 +00:00
6ebe734ca6
Move the GlobalBaseReg field out of X86ISelDAGToDAG.cpp
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and X86FastISel.cpp into X86MachineFunction.h, so that it
can be shared, instead of having each selector keep track
of its own.
llvm-svn: 56825
2008-09-30 00:58:23 +00:00
5033136825
Disable all x87 usage, including f32 and f64 when the subtarget
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doesn't have SSE(2), with X86FastISel.
llvm-svn: 56823
2008-09-30 00:48:39 +00:00
c02dbf451e
Fix an over-pessimization about GlobalVariable addresses in X86FastISel.
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llvm-svn: 56802
2008-09-29 21:13:15 +00:00
2564b900ce
Fix X86FastISel's address folding to check displacement
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values for overflow.
llvm-svn: 56686
2008-09-26 20:04:15 +00:00
007a6bb9b9
Factor out the code for determining when symblic addresses
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require RIP-relative addressing and use it to fix a bug
in X86FastISel in x86-64 PIC mode, where it was trying to
use base/index registers with RIP-relative addresses. This
fixes a bunch of x86-64 testsuite failures.
llvm-svn: 56676
2008-09-26 19:15:30 +00:00
839105d254
Disable support for x86_f80 in X86FastISel. Supporting it would
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require more work.
llvm-svn: 56637
2008-09-26 01:39:32 +00:00
0c1b884df1
Fix a bug in which address displacements were being added to the
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load from the stub, instead of the result of the load from the stub.
llvm-svn: 56626
2008-09-25 23:34:02 +00:00
4c758ea3e0
Large mechanical patch.
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s/ParamAttr/Attribute/g
s/PAList/AttrList/g
s/FnAttributeWithIndex/AttributeWithIndex/g
s/FnAttr/Attribute/g
This sets the stage
- to implement function notes as function attributes and
- to distinguish between function attributes and return value attributes.
This requires corresponding changes in llvm-gcc and clang.
llvm-svn: 56622
2008-09-25 21:00:45 +00:00
3691d507c4
PIC support in X86FastISel.
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llvm-svn: 56608
2008-09-25 15:24:26 +00:00
918fe08a56
Arrange for FastISel code to have access to the MachineModuleInfo
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object. This will be needed to support debug info.
llvm-svn: 56508
2008-09-23 21:53:34 +00:00
796a271c5f
Change the calling convention used when tail call optimization is enabled from CC_X86_32_TailCall to CC_X86_32_FastCC.
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llvm-svn: 56436
2008-09-22 14:50:07 +00:00
f1280cf744
Fold immediates into X86 shifts with fast isel. This generates:
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sarl $3, %ecx
instead of:
movl $3, %ecx
sarl %cl, %edx
This shrinks fast isel 176.gcc by about 2000 instructions (.3%)
llvm-svn: 56413
2008-09-21 21:44:29 +00:00
098786e9f7
Fix a FastISel GlobalVariable CSE bug.
...
llvm-svn: 56376
2008-09-19 23:42:04 +00:00
9801ba451a
Refactor X86SelectConstAddr, folding it into X86SelectAddress. This
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results in better code for globals. Also, unbreak the local CSE for
GlobalValue stub loads.
llvm-svn: 56371
2008-09-19 22:16:54 +00:00
6e005fdc8d
Address-mode folding for X86FastISel. It's pretty basic, but it
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catches a fair number of common cases. Note that this currently
causes Fast-ISel to leave behind lots of dead instructions.
Those will be dealt with in subsequent commits.
llvm-svn: 56320
2008-09-18 23:23:44 +00:00
e91edeb61c
Simplify this code. The FastISel class has its own TD member.
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llvm-svn: 56311
2008-09-18 18:26:43 +00:00
af13bf1ebd
FastISel: For calls, prefer using the callee's address as a constant
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over having it in a register. And wait until after checking type
legality before requesting that the callee address be placed in a
register. Also, fix support for calls with void return type.
This speeds up fast-isel isel time by about 15% and reduces
instruction counts by about 3% overall on certain testcases. It also
changes many indirect calls to direct calls.
llvm-svn: 56292
2008-09-17 21:18:49 +00:00
453564bfba
Fix a bug in ANY_EXTEND handling that was breaking 403.gcc on X86-64 in fast isel.
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llvm-svn: 56117
2008-09-11 19:44:55 +00:00
41baf8b22a
If ISD::ANY_EXTEND fails, try ISD::ZERO_EXTEND and ISD::SIGN_EXTEND before giving up. This fixes 445.gobmk on
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X86-64 in fast isel.
llvm-svn: 56088
2008-09-11 02:41:37 +00:00
bf646f2986
X86FastISel support for double->float and float->double casts.
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llvm-svn: 56070
2008-09-10 21:02:08 +00:00
39d82f902a
Add X86FastISel support for static allocas, and refences
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to static allocas. As part of this change, refactor the
address mode code for laods and stores.
llvm-svn: 56066
2008-09-10 20:11:02 +00:00
1e97901388
Fix a constant lowering bug. Now we can do load and store instructions with funky getelementptr embedded in the address operand.
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llvm-svn: 55975
2008-09-09 01:26:59 +00:00
d172048b59
Handle calls which produce i1 results: promote to i8 but and it with 1 to get the low bit.
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llvm-svn: 55925
2008-09-08 17:15:42 +00:00
8f658bac2f
Fix copy+pastos in comments.
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llvm-svn: 55918
2008-09-08 16:31:35 +00:00
6500d1711a
Add support to extend call operands when needed. Enable x86 fastisel call support.
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llvm-svn: 55891
2008-09-08 06:35:17 +00:00
6c8f55c841
Initial fastisel call support for C, Fast, and X86_FastCall calling conventions. It's meant to handle "simple" calls, i.e. no byval, structret, etc. It doesn't support multi-result returns either.
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Not yet turned on, it needs to support sext / zext of arguments and result.
llvm-svn: 55882
2008-09-07 09:09:33 +00:00
b928669409
Handle x86 truncate to i8 with target hook for now.
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llvm-svn: 55877
2008-09-07 08:47:42 +00:00
d41c7160d0
Fix constant pool loads, and remove broken versions of addConstantPoolReference.
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llvm-svn: 55868
2008-09-06 01:11:01 +00:00
db06a99239
Fix X86FastISel's shift and select code to reject illegal types.
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llvm-svn: 55857
2008-09-05 21:27:34 +00:00
e556018dc0
Fix the opcodes used by X86FastISel for shifts and conditional moves.
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llvm-svn: 55855
2008-09-05 21:13:04 +00:00
f5bc7e57bc
Factor out code that emits load and store instructions.
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llvm-svn: 55854
2008-09-05 21:00:03 +00:00
ffcc884c77
Rename method.
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llvm-svn: 55853
2008-09-05 20:49:33 +00:00
7d7a26df65
X86FastISel support for shifts and conditional moves.
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llvm-svn: 55844
2008-09-05 18:30:08 +00:00
09faf81b6c
Check a comparion's operand type for legality before
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expanding its operands.
llvm-svn: 55820
2008-09-05 01:33:56 +00:00
ffd89d40d2
Fix X86FastISel code for comparisons and conditional branches
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to check the result of getRegForValue before using it, and
to check for illegal operand types.
llvm-svn: 55819
2008-09-05 01:15:35 +00:00
a5753b31be
X86FastISel support for conditional branches.
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llvm-svn: 55816
2008-09-05 01:06:14 +00:00
50288e3c99
Add initial support for selecting constant materializations that require constant
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pool loads on X86 in fast isel. This isn't actually used yet.
llvm-svn: 55814
2008-09-05 00:06:23 +00:00
09fdbcf400
X86FastISel support for ICmpInst and FCmpInst.
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llvm-svn: 55811
2008-09-04 23:26:51 +00:00
b8c7ba228f
Fix the ordering of operands to the store (inverted relative to LLVM IR), and fix the testcase.
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llvm-svn: 55777
2008-09-04 16:48:33 +00:00
4f948bd87a
Add a first attempt at implementing stores for X86 fast isel using target hooks.
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Dan or Evan, please review.
llvm-svn: 55764
2008-09-04 07:08:58 +00:00
8d8f47d50b
Load from GV stub should be locally CSE'd.
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llvm-svn: 55763
2008-09-04 06:18:33 +00:00
7bda51f5a4
Create HandlePHINodesInSuccessorBlocksFast, a version of
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HandlePHINodesInSuccessorBlocks that works FastISel-style. This
allows PHI nodes to be updated correctly while using FastISel.
This also involves some code reorganization; ValueMap and
MBBMap are now members of the FastISel class, so they needn't
be passed around explicitly anymore. Also, SelectInstructions
is changed to SelectInstruction, and only does one instruction
at a time.
llvm-svn: 55746
2008-09-03 23:12:08 +00:00
a41ee2974b
Add X86 target hook to implement load (even from GlobalAddress).
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llvm-svn: 55693
2008-09-03 06:44:39 +00:00
8f23ec96b0
Unbreak fast isel.
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llvm-svn: 55685
2008-09-03 01:04:47 +00:00
24422d4928
Let tblgen only generate fastisel routines, not the class definition. This makes it easier for targets to define its own fastisel class.
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llvm-svn: 55679
2008-09-03 00:03:49 +00:00
0673a8af14
Add initial support for fast isel of instructions that have inputs pinned to physical registers.
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llvm-svn: 55545
2008-08-29 17:45:56 +00:00
d58f3e36d0
Add a target callback for FastISel.
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llvm-svn: 55512
2008-08-28 23:21:34 +00:00
49e19e906f
Factor out the predicate check code from DAGISelEmitter.cpp
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and use it in FastISelEmitter.cpp, and make FastISel
subtarget aware. Among other things, this lets it work
properly on x86 targets that don't have SSE, where it
successfully selects x87 instructions.
llvm-svn: 55156
2008-08-22 00:20:26 +00:00
daef7f43af
Instantiate FastISel for X86.
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llvm-svn: 55011
2008-08-19 21:45:35 +00:00
Dan Gohman