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54 Commits

Author SHA1 Message Date
Akira Hatanaka 6bbe1f0d10 Fix bugs which were introduced when support for base+index floating point loads 
and stores was added.

- SelectAddr should return false if Parent is an unaligned f32 load or store.
- Only aligned load and store nodes should be matched to select reg+imm
  floating point instructions.
- MIPS does not have support for f64 unaligned load or store instructions.

llvm-svn: 151843
 2012-03-01 22:12:30 +00:00
Jia Liu f54f60f3ce remove blanks, and some code format 
llvm-svn: 151625
 2012-02-28 07:46:26 +00:00
Akira Hatanaka 330d901ce3 Add support for floating point base register + offset register addressing mode 
load and store instructions.

llvm-svn: 151611
 2012-02-28 02:55:02 +00:00
Akira Hatanaka b260f206d2 Remove unnecessary template parameters. 
llvm-svn: 151540
 2012-02-27 19:17:53 +00:00
Akira Hatanaka 3c5cab4730 Fix instruction predicates that were not set correctly. 
llvm-svn: 151538
 2012-02-27 19:09:08 +00:00
Akira Hatanaka 60f7a8e710 Add definitions of floating point multiply add/sub and negative multiply 
add/sub instructions.

llvm-svn: 151415
 2012-02-25 00:21:52 +00:00
Akira Hatanaka 4705b0cc1c Remove trailing whitespace. Add newline. 
llvm-svn: 150706
 2012-02-16 17:48:20 +00:00
Akira Hatanaka 77dbd786c8 Pattern for f32 to i64 conversion. 
llvm-svn: 148869
 2012-01-24 22:05:25 +00:00
Akira Hatanaka 2216f73676 Various Mips64 floating point instruction patterns. 
llvm-svn: 144019
 2011-11-07 21:38:58 +00:00
Akira Hatanaka b2d37760a2 Add definition of the base class for floating point comparison instructions 
and add Mips64's version too.

llvm-svn: 144018
 2011-11-07 21:37:33 +00:00
Akira Hatanaka 1537e297e1 Add definitions of 64-bit instructions which move data between integer and 
floating pointer registers.

llvm-svn: 144016
 2011-11-07 21:32:58 +00:00
Bruno Cardoso Lopes 2312a3aaa0 Final patch that completes old JIT support for Mips: 
-Fix binary codes and rename operands in .td files so that automatically
generated function MipsCodeEmitter::getBinaryCodeForInstr gives correct
encoding for instructions.
-Define new class FMem for instructions that access memory.
-Define new class FFRGPR for instructions that move data between GPR and
FPU general and control registers.
-Define custom encoder methods for memory operands, and also for size
operands of ext and ins instructions.
-Only static relocation model is currently implemented.

Patch by Sasa Stankovic

llvm-svn: 142378
 2011-10-18 17:50:36 +00:00
Akira Hatanaka 975bfc9b45 Move class and instruction definitions for conditional moves to a seperate file. 
llvm-svn: 142220
 2011-10-17 18:43:19 +00:00
Akira Hatanaka b6d72cbeb9 Make changes necessary for supporting floating point load and store instructions 
that have 64-bit pointers or access the 32 x 64-bit floating pointer register
file. Update functions in MipsInstrInfo.cpp too.

llvm-svn: 141623
 2011-10-11 01:12:52 +00:00
Akira Hatanaka 6be7d6c976 Simplify definition of FP move instructions. 
llvm-svn: 141476
 2011-10-08 03:50:18 +00:00
Akira Hatanaka 2365f90676 Define classes and multiclasses for FP binary instructions. 
llvm-svn: 141475
 2011-10-08 03:38:41 +00:00
Akira Hatanaka c7548dec7d Define multiclasses for FP-to-FP instructions. 
llvm-svn: 141474
 2011-10-08 03:29:22 +00:00
Akira Hatanaka 13ae13bdc2 Define classes for FP unary instructions and multiclasses for FP-to-fixed point 
conversion instructions. 

llvm-svn: 141473
 2011-10-08 03:19:38 +00:00
Jakob Stoklund Olesen 6728958279 Revert r140731, "Define classes for unary and binary FP instructions and use them to define" 
It broke the unit tests.  Please reapply with tests fixed.

llvm-svn: 140735
 2011-09-28 23:59:28 +00:00
Akira Hatanaka 5a1b4a80c3 Define classes for unary and binary FP instructions and use them to define 
multiclasses.

llvm-svn: 140731
 2011-09-28 21:58:01 +00:00
Akira Hatanaka 6f37b4a5a5 Rename predicate In32BitMode to NotFP64bit and add definition of IsFP64bit. 
llvm-svn: 140705
 2011-09-28 18:11:19 +00:00
Akira Hatanaka edc172d4cc Remove definitions of branch-on-FP-likely instructions. They are deprecated. 
llvm-svn: 140704
 2011-09-28 17:56:55 +00:00
Akira Hatanaka ae40dc735d Remove MipsFPRound. Mips1 is no longer supported. 
llvm-svn: 140661
 2011-09-27 23:55:37 +00:00
Akira Hatanaka a5d18f2d7e Embed patterns in definitions of MFC1 and MTC1 instead of defining them outside 
of the instruction definitions using Pat<>.

llvm-svn: 140644
 2011-09-27 22:01:01 +00:00
Akira Hatanaka f25c37e384 Make changes in instruction and pattern definitions so that tablegen does not 
complain it cannot infer types in patterns. Fix a mistake in definition of 
SDT_MipsExtractElementF64.

llvm-svn: 140354
 2011-09-22 23:31:54 +00:00
Akira Hatanaka 4444daeec5 Drop support for Mips1 and Mips2. 
llvm-svn: 139405
 2011-09-09 20:45:50 +00:00
Akira Hatanaka 2263c10946 Fix handling of double precision loads and stores when Mips1 is targeted. 
Mips1 does not support double precision loads or stores, therefore two single
precision loads or stores must be used in place of these instructions. This 
patch treats double precision loads and stores as if they are legal
instructions until MCInstLowering, instead of generating the single precision
instructions during instruction selection or Prolog/Epilog code insertion.

Without the changes made in this patch, llc produces code that has the same 
problem described in r137484 or bails out when
MipsInstrInfo::storeRegToStackSlot or loadRegFromStackSlot is called before
register allocation.

llvm-svn: 137711
 2011-08-16 03:51:51 +00:00
Akira Hatanaka dde4aac02b Use tabs to separate opcode and operand strings. 
llvm-svn: 132718
 2011-06-07 18:16:51 +00:00
Akira Hatanaka 6af5bd2537 Add pattern for double-to-integer conversion. Patch by Sasa Stankovic. 
llvm-svn: 131927
 2011-05-23 22:16:43 +00:00
Akira Hatanaka e50a3d16e9 Fix setting of isCommutable flag. 
llvm-svn: 131233
 2011-05-12 17:42:08 +00:00
Eric Christopher 5dc19f916c Fix td file comments for Mips. 
Patch by Liu <proljc@gmail.com>!

llvm-svn: 131086
 2011-05-09 18:16:46 +00:00
Akira Hatanaka e24891251c Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality. 
llvm-svn: 129612
 2011-04-15 21:51:11 +00:00
Akira Hatanaka aef55c8801 Fix lines that have incorrect indentation or exceed 80 columns. There is no change in functionality. 
llvm-svn: 129606
 2011-04-15 21:00:26 +00:00
Akira Hatanaka 279169771b Add pass that expands pseudo instructions into target instructions after register allocation. Define pseudos that get expanded into mtc1 or mfc1 instructions. 
llvm-svn: 129594
 2011-04-15 19:52:08 +00:00
Chris Lattner 0ab5e2cded Fix a ton of comment typos found by codespell. Patch by 
Luis Felipe Strano Moraes!

llvm-svn: 129558
 2011-04-15 05:18:47 +00:00
Akira Hatanaka a535270d91 Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons. 
llvm-svn: 128650
 2011-03-31 18:26:17 +00:00
Bruno Cardoso Lopes ed874eff93 Remove (hopefully) all trailing whitespaces from the mips backend. Patch by Hatanaka, Akira 
llvm-svn: 127003
 2011-03-04 17:51:39 +00:00
Chris Lattner 2a0a3b43d7 Flag -> Glue, the ongoing saga 
llvm-svn: 122513
 2010-12-23 18:28:41 +00:00
Chris Lattner 72a364c107 fix emacs language spec's, patch by Edmund Grimley-Evans! 
llvm-svn: 111241
 2010-08-17 16:20:04 +00:00
Chris Lattner e83591c616 the FPCmp node returns an i32. 
llvm-svn: 99737
 2010-03-28 05:12:57 +00:00
Bruno Cardoso Lopes 7ee71912ed Fix mov.d out register by using the FFR register class directly 
llvm-svn: 94914
 2010-01-30 18:29:19 +00:00
Bruno Cardoso Lopes 5bf807688e Disable ldc1/sdc1 instructions for mips1 targets. 
llvm-svn: 88887
 2009-11-16 04:35:29 +00:00
Bruno Cardoso Lopes 626d49f684 A real solution for the first part of PR5445 
llvm-svn: 86895
 2009-11-11 23:09:33 +00:00
Bruno Cardoso Lopes 05671ea10a Fix PR5445 
llvm-svn: 86651
 2009-11-10 02:35:13 +00:00
Dan Gohman 453d64c9f5 Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a 
bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.

llvm-svn: 85517
 2009-10-29 18:10:34 +00:00
Bruno Cardoso Lopes a72a505a80 Added support for fround, fextend and FP_TO_SINT 
llvm-svn: 72483
 2009-05-27 17:23:44 +00:00
Bruno Cardoso Lopes 9b9586a5ae Removed AFGR32 register class 
Handle odd registers allocation in FGR32.

llvm-svn: 67422
 2009-03-21 00:05:07 +00:00
Bruno Cardoso Lopes 2ca70df58b Handle i32->f32 bitconvert results. 
llvm-svn: 54315
 2008-08-04 06:44:31 +00:00
Bruno Cardoso Lopes 2d7ddea240 Added pattern for floating point zero immediate (avoiding a constant pool 
access).
Added pattern to match bitconvert node.
Fixed MTC1 asm string bug.

llvm-svn: 54229
 2008-07-30 19:00:31 +00:00
Bruno Cardoso Lopes e683bbabc7 Added floating point lowering for select. 
llvm-svn: 54167
 2008-07-29 19:05:28 +00:00