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6 Commits

Author SHA1 Message Date
Andrew Trick 5a1e0af838 Temporarily enable MI-Sched on X86. 
Sorry for the unit test churn. I'll try to make the change permanently
next time.

llvm-svn: 184705
 2013-06-24 09:13:20 +00:00
Eli Friedman 3f5eccbe7a Teach the x86 backend a couple tricks for dealing with v16i8 sra by a constant splat value. Fixes PR11289. 
llvm-svn: 143498
 2011-11-01 21:18:39 +00:00
Benjamin Kramer 7402ee6ec2 X86: Emit logical shift by constant splat of <16 x i8> as a <8 x i16> shift and zero out the bits where zeros should've been shifted in. 
llvm-svn: 143315
 2011-10-30 17:31:21 +00:00
Nadav Rotem c602b2c4de Fix pr11266. 
On x86: (shl V, 1) -> add V,V

Hardware support for vector-shift is sparse and in many cases we scalarize the
result. Additionally, on sandybridge padd is faster than shl.

llvm-svn: 143311
 2011-10-30 13:24:22 +00:00
Nadav Rotem 486ff59a9f Enable element promotion type legalization by deafault. 
Changed tests which assumed that vectors are legalized by widening them.

llvm-svn: 142152
 2011-10-16 20:31:33 +00:00
Nadav Rotem 8f971c27fb Add custom lowering of X86 vector SRA/SRL/SHL when the shift amount is a splat vector. 
llvm-svn: 131179
 2011-05-11 08:12:09 +00:00