c85e3ff334
Mips MC object code emission improvements:
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"With this patch we can now generate runnable Mips code through LLVM
direct object emission. We have run numerous simple programs, both C
and C++ and with -O0 and -O3 from the output. The code is not production
ready, but quite useful for experimentation." Patch and message by
Jack Carter
llvm-svn: 144414
2011-11-11 22:58:42 +00:00
21cbc25bbb
64-bit atomic instructions.
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llvm-svn: 144372
2011-11-11 04:14:30 +00:00
4bdfec57ba
Add 64-bit versions of LEA_ADDiu and DynAlloc. Modify LowerDYNAMIC_STACKALLOC.
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llvm-svn: 144370
2011-11-11 04:06:38 +00:00
0009dc2088
64-bit versions of jal, jalr and bal.
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llvm-svn: 144368
2011-11-11 04:03:54 +00:00
2b8d1f163f
Add definition of 64-bit load upper immediate.
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llvm-svn: 143994
2011-11-07 19:10:49 +00:00
770f0646db
Make the type of shift amount i32 in order to reduce the number of shift
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instruction definitions.
llvm-svn: 143989
2011-11-07 18:59:49 +00:00
2312a3aaa0
Final patch that completes old JIT support for Mips:
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-Fix binary codes and rename operands in .td files so that automatically
generated function MipsCodeEmitter::getBinaryCodeForInstr gives correct
encoding for instructions.
-Define new class FMem for instructions that access memory.
-Define new class FFRGPR for instructions that move data between GPR and
FPU general and control registers.
-Define custom encoder methods for memory operands, and also for size
operands of ext and ins instructions.
-Only static relocation model is currently implemented.
Patch by Sasa Stankovic
llvm-svn: 142378
2011-10-18 17:50:36 +00:00
a7e0b90897
Add definitions of conditional moves with 64-bit operands. Comment out code for
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expanding conditional moves, which is not needed since architectures that lack
support for conditional moves have been removed.
llvm-svn: 142226
2011-10-17 18:53:29 +00:00
975bfc9b45
Move class and instruction definitions for conditional moves to a seperate file.
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llvm-svn: 142220
2011-10-17 18:43:19 +00:00
33fe8f908c
Redefine count-leading 0s and 1s instructions.
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llvm-svn: 142216
2011-10-17 18:26:37 +00:00
8c446be204
Redefine mfhi/lo and mthi/lo instructions.
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llvm-svn: 142214
2011-10-17 18:24:15 +00:00
0317b65367
Redefine multiply and divide instructions.
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llvm-svn: 142211
2011-10-17 18:21:24 +00:00
2736bbc09e
Add definition of a base class for logical shift/rotate instructions with two
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source registers and redefine 32-bit and 64-bit instructions.
llvm-svn: 142210
2011-10-17 18:17:58 +00:00
73081309c3
Add definition of a base class for logical shift/rotate immediate instructions
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and have 32-bit and 64-bit instructions derive from it.
llvm-svn: 142207
2011-10-17 18:06:56 +00:00
e3f27b79dc
Add definition of immZExt5_64 and redefine immZExt5 as an ImmLeaf.
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llvm-svn: 142205
2011-10-17 18:01:00 +00:00
3261c0fa6e
Define base class LogicNOR and make 32-bit and 64-bit NOR derive from it.
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llvm-svn: 141761
2011-10-12 01:05:13 +00:00
c57febff4a
Fix encoding of 32-bit integer instructions. Change names of operands and nodes.
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Remove unused classes.
llvm-svn: 141757
2011-10-12 00:56:06 +00:00
0f4ecf7548
Change name of class to ArithOverflowR.
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llvm-svn: 141743
2011-10-11 23:43:48 +00:00
8f0d549c4c
Define class ArithLogicI. Make 32-bit and 64-bit arithmetic and logical
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instructions with two register operands derive from it.
llvm-svn: 141742
2011-10-11 23:38:52 +00:00
8d4f74a6b1
Fix comment.
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llvm-svn: 141737
2011-10-11 23:12:12 +00:00
ae5a9d6578
Define classes ArithLogicR and ArithLogicOfR and make 32-bit and 64-bit
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arithmetic and logical instructions with three register operands derive from
them. Fix instruction encoding too.
llvm-svn: 141736
2011-10-11 23:05:46 +00:00
10ae11fd57
Remove unused PatLeaf.
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llvm-svn: 141720
2011-10-11 21:53:08 +00:00
46a7994ac9
Remove redundancy in setcc patterns using multiclass.
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llvm-svn: 141715
2011-10-11 21:40:01 +00:00
8c1c51045d
Use sltiu instead of sltu when a register operand and immediate are compared.
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llvm-svn: 141708
2011-10-11 20:44:43 +00:00
7148bce86e
Add patterns for conditional branches with 64-bit register operands.
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llvm-svn: 141696
2011-10-11 19:09:09 +00:00
f75add6236
Add support for 64-bit set-on-less-than instructions.
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llvm-svn: 141695
2011-10-11 18:53:46 +00:00
4b6ac98fcf
Add support for conditional branch instructions with 64-bit register operands.
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llvm-svn: 141694
2011-10-11 18:49:17 +00:00
b6d72cbeb9
Make changes necessary for supporting floating point load and store instructions
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that have 64-bit pointers or access the 32 x 64-bit floating pointer register
file. Update functions in MipsInstrInfo.cpp too.
llvm-svn: 141623
2011-10-11 01:12:52 +00:00
be68f3c348
Add definitions of 64-bit loads and stores. Add a patterns for unaligned
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zextloadi32 for which there is no corresponding pseudo or real instruction.
llvm-svn: 141608
2011-10-11 00:27:28 +00:00
fd2d7dcc31
Change definitions of classes LoadM and StoreM in preparation for adding support
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for 64-bit load and store instructions. Add definitions of 64-bit memory operand
and 16-bit immediate operand.
llvm-svn: 141603
2011-10-11 00:11:12 +00:00
557c8e3443
Add patterns for unaligned load and store instructions and enable the
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instruction selector to generate them.
llvm-svn: 141471
2011-10-08 02:24:10 +00:00
b1538f91dc
Add support for 64-bit divide instructions.
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llvm-svn: 141024
2011-10-03 21:06:13 +00:00
cdcc74563c
Add definitions of instructions which move values between 64-bit integer
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registers and 64-bit HI and LO registers. Fix encoding of the 32-bit versions
of the instructions.
llvm-svn: 141015
2011-10-03 19:28:44 +00:00
e96273e75d
Preparation for adding simple Mips64 instructions.
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llvm-svn: 140443
2011-09-24 01:34:44 +00:00
f25c37e384
Make changes in instruction and pattern definitions so that tablegen does not
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complain it cannot infer types in patterns. Fix a mistake in definition of
SDT_MipsExtractElementF64.
llvm-svn: 140354
2011-09-22 23:31:54 +00:00
bb49e721b8
Change the names of functions isMips* to hasMips*.
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llvm-svn: 140214
2011-09-20 23:53:09 +00:00
fba4bd62b1
Add pattern used to match MipsLo, which is needed when the instruction selector
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tries to match a dead MipsLo node (explanation in the link below).
http://article.gmane.org/gmane.comp.compilers.llvm.devel/42757/match=dagcombiner+dead
llvm-svn: 139634
2011-09-13 20:13:58 +00:00
4444daeec5
Drop support for Mips1 and Mips2.
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llvm-svn: 139405
2011-09-09 20:45:50 +00:00
2b8078a2cd
Clenup and fix encoding for Mips ins and ext instruction
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llvm-svn: 137943
2011-08-18 16:30:49 +00:00
eea541ce4e
Changed definition of EXT and INS per Bruno's comments.
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llvm-svn: 137892
2011-08-17 22:59:46 +00:00
b2e7558c40
Add support for half-word unaligned loads and stores.
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llvm-svn: 137848
2011-08-17 18:49:18 +00:00
5360f88355
Add support for ext and ins.
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llvm-svn: 137804
2011-08-17 02:05:42 +00:00
2fcc1cfdce
Define unaligned load and store.
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llvm-svn: 137515
2011-08-12 21:30:06 +00:00
6d8c039ab1
Add isIndirectBranch flag.
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llvm-svn: 137351
2011-08-11 21:05:37 +00:00
170581488f
Change name of class.
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llvm-svn: 135550
2011-07-20 00:53:09 +00:00
969edcdf74
Define classes for definitions of atomic instructions.
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llvm-svn: 135546
2011-07-20 00:23:01 +00:00
a4c09bce9b
Lower memory barriers to sync instructions.
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llvm-svn: 135537
2011-07-19 23:30:50 +00:00
27292638bd
Set mayLoad or mayStore flags for SC and LL in order to prevent LICM from
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moving them out of the loop. Previously, stores and loads to a stack frame
object were inserted to accomplish this. Remove the code that was needed to do
this. Patch by Sasa Stankovic.
llvm-svn: 135415
2011-07-18 18:52:12 +00:00
28d6677a53
Remove unnecessary newline.
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llvm-svn: 134645
2011-07-07 22:06:18 +00:00
9f6f6f6ecc
Rather than having printMemOperand change the way memory operands are printed
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based on a modifier, split it into two functions.
llvm-svn: 134637
2011-07-07 20:54:20 +00:00
Bruno Cardoso Lopes