Commit Graph

359121 Commits

Author SHA1 Message Date
Erich Keane 19c35526d9 Limit x86 test to require target to fix buildbot (from 2831a317b)
The modification of the features apparently requires the backend to be
instantiated, so make sure this is required to fix the ARM build bots.
2020-07-01 07:35:39 -07:00
Guillaume Chatelet ef36f5143d [Alignment] TargetLowering::hasPairedLoad must use Align for RequiredAlignment
As per documentation of `hasPairLoad`:
"`RequiredAlignment` gives the minimal alignment constraints that must be met to be able to select this paired load."
In this sense, `0` is strictly equivalent to `1`. We make this obvious by using `Align` instead of unsigned.
There is only one implementor of this interface.

Differential Revision: https://reviews.llvm.org/D82958
2020-07-01 14:32:30 +00:00
Guillaume Chatelet d3085c2501 [Alignment][NFC] Transition and simplify calls to DL::getABITypeAlignment
This patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

Differential Revision: https://reviews.llvm.org/D82956
2020-07-01 14:31:56 +00:00
Guillaume Chatelet 27bbc8ede1 [Alignment][NFC] Migrate TargetTransformInfo::CreateVariableSizedObject to Align
This patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

Differential Revision: https://reviews.llvm.org/D82939
2020-07-01 14:31:21 +00:00
rojamd 63eddb679a [cmake][Windows] Add libpath to CMAKE_MODULE_LINKER_FLAGS too
Followup to b8000c0ce8, the library path needs to go in
CMAKE_MODULE_LINKER_FLAGS too, for the sake of a few files
like LLVMHello.dll.

Reviewed By: hans

Differential Revision: https://reviews.llvm.org/D82888
2020-07-01 10:19:19 -04:00
Erich Keane 2831a317b6 Implement AVX ABI Warning/error
The x86-64 "avx" feature changes how >128 bit vector types are passed,
instead of being passed in separate 128 bit registers, they can be
passed in 256 bit registers.

"avx512f" does the same thing, except it switches from 256 bit registers
to 512 bit registers.

The result of both of these is an ABI incompatibility between functions
compiled with and without these features.

This patch implements a warning/error pair upon an attempt to call a
function that would run afoul of this. First, if a function is called
that would have its ABI changed, we issue a warning.

Second, if said call is made in a situation where the caller and callee
are known to have different calling conventions (such as the case of
'target'), we instead issue an error.

Differential Revision: https://reviews.llvm.org/D82562
2020-07-01 07:14:31 -07:00
David Sherwood 97a7a9abb2 [CodeGen] Fix up warnings in visitEXTRACT_SUBVECTOR
It's perfectly valid to do certain DAG combines where we extract
subvectors from a concat vector when we have scalable vector types.
However, we can do this in a way that avoids generating compiler
warnings by replacing calls to getVectorNumElements() with
getVectorMinNumElements(). Due to the way subvector extracts are
designed to work with scalable vector types this is ok.

This eliminates some warnings from existing tests in this file:

  llvm/test/CodeGen/AArch64/sve-intrinsics-loads.ll

Differential Revision: https://reviews.llvm.org/D82655
2020-07-01 15:10:53 +01:00
Raphael Isemann f3b5bf3eb7 [lldb] Fix NSDate test after Scalar change
The formatter was requesting an unsigned integer from the ValueObject,
but CFAbsoluteTime is a signed double, so in the NSDate test the formatter
actually just printed the 'error value' date which is the Cocoa epoch. This
started failing after the recent Scalar changes.

This patch just changes the logic to use a signed value which fits to the data
we try to read and avoids this issue.
2020-07-01 16:00:10 +02:00
Nicolas Vasilache 7d9518c800 [mlir][Linalg] Add an option to use Alloca instead of malloc/free pairs.
Summary: A relevant test is also added.

Subscribers: mehdi_amini, rriddle, jpienaar, shauheen, antiagainst, arpith-jacob, mgester, lucyrfox, aartbik, liufengdb, stephenneuendorffer, Joonsoo, grosul1, Kayjukh, jurahul, msifontes

Tags: #mlir

Differential Revision: https://reviews.llvm.org/D82959
2020-07-01 09:44:01 -04:00
Pavel Labath a03dc8c9fa [lldb] Add basic -flimit-debug-info support to expression evaluator
Summary:
This patch adds support for evaluation of expressions referring to types
which were compiled in -flimit-debug-info (a.k.a -fno-standalone-debug)
in clang. In this mode it's possible that the debug information needed
to fully describe a c++ type is not present in a single shared library
-- for example debug info for a base class or a member of a type can
only be found in another shared library.  This situation is not
currently handled well within lldb as we are limited to searching within
a single shared library (lldb_private::Module) when searching for the
definition of these types.

The way that this patch gets around this limitation is by doing the
search at a later stage -- during the construction of the expression ast
context. This works by having the parser (currently SymbolFileDWARF, but
a similar approach is probably needed for PDBs too) mark a type as
"forcefully completed". What this means is that the parser has marked
the type as "complete" in the module ast context (as this is necessary
to e.g. derive classes from it), but its definition is not really there.
This is done via a new field on the ClangASTMetadata struct.

Later, when we are importing such a type into the expression ast, we
check this flag. If the flag is set, we try to find a better definition
for the type in other shared libraries. We do this by initiating a
new lookup for the "forcefully completed" classes, which then imports the
type from a module with a full definition.

This patch only implements this handling for base classes, but other
cases (members, array element types, etc.). The changes for that should
be fairly simple and mostly revolve around marking these types as
"forcefully completed" at an approriate time -- the importing logic is
generic already.

Another aspect, which is also not handled by this patch is viewing these
types via the "frame variable" command. This does not use the AST
importer and so it will need to handle these types on its own -- that
will be the subject of another patch.

Differential Revision: https://reviews.llvm.org/D81561
2020-07-01 14:50:14 +02:00
Alexey Bataev e35a5876e4 Revert "[StackSafety,NFC] Remove unneded constexpr"
This reverts commit 38470baa54 because it
breaks builds with lld and gold linkers.
2020-07-01 08:41:45 -04:00
Nathan James 669494e9c0
[clang-tidy] fix cppcoreguidelines-init-variables with catch variables
Ignore catch statement var decls.

Reviewed By: aaron.ballman

Differential Revision: https://reviews.llvm.org/D82924
2020-07-01 13:40:20 +01:00
Georgii Rymar 37dd8b6ce5 [llvm-readobj] - Simplify the symbols.test
We are able to use YAML macros to avoid having
4 independent YAML descriptions.

Differential revision: https://reviews.llvm.org/D82942
2020-07-01 15:26:05 +03:00
Simon Pilgrim 65647ed1e5 Pass DIEnumerator APInt args by const reference not value.
Noticed by clang-tidy performance-unnecessary-value-param warning.
2020-07-01 13:16:07 +01:00
Stefan Pintilie b294e00fb0 [PowerPC] Fix for PC Relative call protocol
The situation where the caller uses a TOC and the callee does not
but is marked as clobbers the TOC (st_other=1) was not being compiled
correctly if both functions where in the same object file.

The call site where we had `callee` was missing a nop after the call.
This is because it was assumed that since the two functions where in
the same DSO they would be sharing a TOC. This is not the case if the
callee uses PC Relative because in that case it may clobber the TOC.
This patch makes sure that we add the cnop correctly so that the
linker has a place to restore the TOC.

Reviewers: sfertile, NeHuang, saghir

Differential Revision: https://reviews.llvm.org/D81126
2020-07-01 07:08:41 -05:00
Simon Pilgrim 2c7af6dffc Pass stripNonLineTableDebugInfo remapDebugLoc lambda DebugLoc arg by const reference not value.
Noticed by clang-tidy performance-unnecessary-value-param warning.
2020-07-01 12:37:47 +01:00
Simon Pilgrim b485586482 [X86][SSE] Fix targetShrinkDemandedConstant constant vector sign extensions
D82257/rG3521ecf1f8a3 was incorrectly sign-extending a constant vector from the lsb, this is fine if all the constant elements are 'allsignbits' in the active bits, but if only some of the elements are, then we are corrupting the constant values for those elements.

This fix ensures we sign extend from the msb of the active/demanded bits instead.
2020-07-01 12:12:53 +01:00
gbreynoo 41ca82cbe8 [llvm-size] Output REL, RELA and STRTAB sections when allocatable
gnu size has a number of special cases regarding REL, RELA and STRTAB
sections being considered in size output. To avoid unnecessary
complexity this commit makes llvm size outputs these sections in cases
they have the SHF_ALLOC flag.

Differential Revision: https://reviews.llvm.org/D82479
2020-07-01 12:02:32 +01:00
Simon Pilgrim 93707fe309 [X86][SSE] Add test showing incorrect sign-extension by targetShrinkDemandedConstant 2020-07-01 12:01:19 +01:00
Simon Pilgrim cfb5b144cf Fix Wdocumentation warnings by only tagging a param id once per doxygen comment block. NFC. 2020-07-01 12:01:19 +01:00
Simon Pilgrim 36aaffbf56 Fix Wdocumentation warnings due to outdated parameter list. NFC. 2020-07-01 12:01:18 +01:00
Simon Pilgrim 0144f501a6 AttrBuilder::merge/remove - use const& for iterator values in for-range loops.
Noticed by clang-tidy performance-for-range-copy warning.
2020-07-01 12:01:18 +01:00
Sam Elliott 7dc892661e [RISCV] Implement Hooks to avoid chaining SELECT
Summary:
This implements two hooks that attempt to avoid control flow for RISC-V. RISC-V
will lower SELECTs into control flow, which is not a great idea.

The hook `hasMultipleConditionRegisters()` turns off the following
DAGCombiner folds:
    select(C0|C1, x, y) <=> select(C0, x, select(C1, x, y))
    select(C0&C1, x, y) <=> select(C0, select(C1, x, y), y)

The second hook `setJumpIsExpensive` controls a flag that has a similar purpose
and is used in CodeGenPrepare and the SelectionDAGBuilder.

Both of these have the effect of ensuring more logic is done before fewer jumps.

Note: with the `B` extension, we may be able to lower select into a conditional
move instruction, so at some point these hooks will need to be guarded based on
enabled extensions.

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D79268
2020-07-01 11:56:31 +01:00
Sam Elliott c44266dc48 [RISCV][NFC] Add Test for (select (or B1, B2), X, Y)
Summary:
As shown, LLVM is keen to avoid logic and introduce selects (in DAGCombiner, and
other places). This leads to control flow on RISC-V which we should attempt to
avoid.

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D79267
2020-07-01 11:56:11 +01:00
Adam Balogh c79745ed48 [Analyzer] Quick fix for broken tests on Windows 2020-07-01 12:52:47 +02:00
Kirill Bobyrev 22a3e4055f [clangd] Set gRPC deadlines to all remote index requests
Summary: "TL;DR: Always set a deadline.", https://grpc.io/blog/deadlines/

Reviewers: sammccall

Reviewed By: sammccall

Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, kadircet, usaxena95, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D82844
2020-07-01 12:46:29 +02:00
Med Ismail Bennani f70cad2612
[lldb/api] Improve error reporting in SBBreakpoint::AddName (NFCI)
This patch improves the error reporting for SBBreakpoint::AddName by
adding a new method `SBBreakpoint::AddNameWithErrorHandling` that returns
a SBError instead of a boolean.

This way, if the breakpoint naming failed in the backend, the client
(i.e. Xcode), will be able to report the reason of that failure to the
user.

rdar://64765461

Differential Revision: https://reviews.llvm.org/D82879

Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com>
2020-07-01 12:45:05 +02:00
Med Ismail Bennani a61f62a7b6 Revert "[lldb/api] Improve error reporting in SBBreakpoint::AddName (NFCI)"
This reverts commit 56bb1d1755.
2020-07-01 12:41:32 +02:00
Med Ismail Bennani 56bb1d1755 [lldb/api] Improve error reporting in SBBreakpoint::AddName (NFCI)
This patch improves the error reporting for SBBreakpoint::AddName by
adding a new method `SBBreakpoint::AddNameWithErrorHandling` that returns
a SBError instead of a boolean.

This way, if the breakpoint naming failed in the backend, the client
(i.e. Xcode), will be able to report the reason of that failure to the
user.

rdar://64765461

Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com>
2020-07-01 12:37:00 +02:00
Daniel Kiss 070acb1d1e [Driver][ARM] parse version of arm/thumb architecture correctly
Summary:
If you execute the following commandline multiple times, the behavior was not always the same:
  clang++ --target=thumbv7em-none-windows-eabi-coff -march=armv7-m -mcpu=cortex-m7 -o temp.obj -c -x c++ empty.cpp

Most of the time the compilation succeeded, but sometimes clang reported this error:
  clang++: error: the target architecture 'thumbv7em' is not supported by the target 'thumbv7em-none-windows-eabi'

The cause of the inconsistent behavior was the uninitialized variable Version.

With these commandline arguments, the variable Version was not set by getAsInteger(),
because it cannot parse a number from the substring "7em" (of "thumbv7em").
To get a consistent behaviour, it's enough to initialize the variable Version to zero.
Zero is smaller than 7, so the comparison will be true.
Then the command always fails with the error message seen above.

By using consumeInteger() instead of getAsInteger() we get 7 from the substring "7em"
and the command does not fail.

Reviewers: compnerd, danielkiss

Reviewed By: danielkiss

Subscribers: danielkiss, kristof.beyls, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D75453
2020-07-01 12:13:52 +02:00
Vitaly Buka 8180a39965 [StackSafety,NFC] Remove expensive assert
Differential Revision: https://reviews.llvm.org/D80908
2020-07-01 02:54:27 -07:00
Vitaly Buka 38470baa54 [StackSafety,NFC] Remove unneded constexpr
Differential Revision: https://reviews.llvm.org/D80908
2020-07-01 02:54:27 -07:00
Petar Avramovic 4b9ae1b7e5 AMDGPU/GlobalISel: Select init_exec intrinsic
Change imm with timm in pattern for SI_INIT_EXEC_LO and
remove regbank mappings for non register operands.

Differential Revision: https://reviews.llvm.org/D82885
2020-07-01 11:50:59 +02:00
Kerry McLaughlin 4c6683eafc [AArch64][SVE] Add reg+imm addressing mode for unpredicated loads
Reviewers: efriedma, sdesmalen, david-arm

Reviewed By: efriedma

Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, danielkiss, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D82893
2020-07-01 10:33:56 +01:00
Sam McCall 7dcc3858e7 [clangd] Fix name conflict again, unbreak GCC. NFC 2020-07-01 11:28:25 +02:00
Georgii Rymar 61f967dcca [llvm-readobj] - Don't crash when checking the number of dynamic symbols.
When we deriving the number of symbols from the DT_HASH table, we can crash when
calculate the number of symbols in the symbol table when SHT_DYNSYM
has sh_entsize == 0.

The patch fixes the issue.

Differential revision: https://reviews.llvm.org/D82877
2020-07-01 12:14:10 +03:00
Georgii Rymar 917bdfaca6 [llvm-readobj] - Simplify and refine hash table tests
Now we are able to have default values for macros in YAML descriptions.
I've applied it for hash table tests and also fixed few copy-paste issues
in their comments.

Differential revision: https://reviews.llvm.org/D82870
2020-07-01 12:09:08 +03:00
David Stenberg 85460c4ea2 [DebugInfo] Do not emit entry values for composite locations
Summary:
This is a fix for PR45009.

When working on D67492 I made DwarfExpression emit a single
DW_OP_entry_value operation covering the whole composite location
description that is produced if a register does not have a valid DWARF
number, and is instead composed of multiple register pieces. Looking
closer at the standard, this appears to not be valid DWARF. A
DW_OP_entry_value operation's block can only be a DWARF expression or a
register location description, so it appears to not be valid for it to
hold a composite location description like that.

See DWARFv5 sec. 2.5.1.7:

"The DW_OP_entry_value operation pushes the value that the described
 location held upon entering the current subprogram. It has two
 operands: an unsigned LEB128 length, followed by a block containing a
 DWARF expression or a register location description (see Section
 2.6.1.1.3 on page 39)."

Here is a dwarf-discuss mail thread regarding this:

http://lists.dwarfstd.org/pipermail/dwarf-discuss-dwarfstd.org/2020-March/004610.html

There was not a strong consensus reached there, but people seem to lean
towards that operations specified under 2.6 (e.g. DW_OP_piece) may not
be part of a DWARF expression, and thus the DW_OP_entry_value operation
can't contain those.

Perhaps we instead want to emit a entry value operation per each
DW_OP_reg* operation, e.g.:

  - DW_OP_entry_value(DW_OP_regx sub_reg0),
    DW_OP_stack_value,
    DW_OP_piece 8,
  - DW_OP_entry_value(DW_OP_regx sub_reg1),
    DW_OP_stack_value,
    DW_OP_piece 8,
  [...]

The question then becomes how the call site should look; should a
composite location description be emitted there, and we then leave it up
to the debugger to match those two composite location descriptions?
Another alternative could be to emit a call site parameter entry for
each sub-register, but firstly I'm unsure if that is even valid DWARF,
and secondly it seems like that would complicate the collection of call
site values quite a bit. As far as I can tell GCC does not emit any
entry values / call sites in these cases, so we do not have something to
compare with, but the former seems like the more reasonable approach.

Currently when trying to emit a call site entry for a parameter composed
of multiple DWARF registers a (DwarfRegs.size() == 1) assert is
triggered in addMachineRegExpression(). Until the call site
representation is figured out, and until there is use for these entry
values in practice, this commit simply stops the invalid DWARF from
being emitted.

Reviewers: djtodoro, vsk, aprantl

Reviewed By: djtodoro, vsk

Subscribers: jyknight, hiraditya, fedor.sergeev, jrtc27, llvm-commits

Tags: #debug-info, #llvm

Differential Revision: https://reviews.llvm.org/D75270
2020-07-01 10:50:55 +02:00
Guillaume Chatelet 7f37d88306 [Alignment][NFC] Migrate MachineFrameInfo::CreateSpillStackObject to Align
iThis patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

Differential Revision: https://reviews.llvm.org/D82934
2020-07-01 08:49:28 +00:00
Pavel Labath 8270a903ba [lldb] Scalar re-fix UB in float->int conversions
The refactor in 48ca15592f reintroduced UB when converting out-of-bounds
floating point numbers to integers -- the behavior for ULongLong() was
originally fixed in r341685, but did not survive my refactor because I
based my template code on one of the methods which did not have this
fix.

This time, I apply the fix to all float->int conversions, instead of
just the "double->unsigned long long" case. I also use a slightly
simpler version of the code, with fewer round-trips
(APFloat->APSInt->native_int vs
APFloat->native_float->APInt->native_int).

I also add some unit tests for the conversions.
2020-07-01 10:29:42 +02:00
Sam Parker f0ecfb789b [NFC][ARM] Add test. 2020-07-01 09:28:56 +01:00
Tony 76b2d9cbeb [AMDGPU] Correct AMDGPUUsage.rst DW_AT_LLVM_lane_pc example
- Correct typo of DW_OP_xaddr to DW_OP_addrx in AMDGPUUsage.rst for
  DW_AT_LLVM_lane_pc example.

Change-Id: I1b0ee2b24362a0240388e4c2f044c1d4883509b9
2020-07-01 08:23:15 +00:00
Paul Walker a1aed80a35 [SVE] Relax merge requirement for IR based divides.
We currently lower SDIV to SDIV_MERGE_OP1. This forces the value
for inactive lanes in a way that can hamper register allocation,
however, the lowering has no requirement for inactive lanes.

Instead this patch replaces SDIV_MERGE_OP1 with SDIV_PRED thus
freeing the register allocator. Once done the only user of
SDIV_MERGE_OP1 is intrinsic lowering so I've removed the node
and perform ISel on the intrinsic directly. This also allows
us to implement MOVPRFX based zeroing in the same manner as SUB.

This patch also renames UDIV_MERGE_OP1 and [F]ADD_MERGE_OP1 for
the same reason but in the ADD cases the ISel code is already
as required.

Differential Revision: https://reviews.llvm.org/D82783
2020-07-01 08:18:42 +00:00
LLVM GN Syncbot 9d347f6efa [gn build] Port f12cd99c44 2020-07-01 08:09:43 +00:00
Endre Fülöp 52f6532366 [analyzer][CrossTU] Lower CTUImportThreshold default value
Summary:
The default value of 100 makes the analysis slow. Projects of considerable
size can take more time to finish than it is practical. The new default
setting of 8 is based on the analysis of LLVM itself. With the old default
value of 100 the analysis time was over a magnitude slower. Thresholding the
load of ASTUnits is to be extended in the future with a more fine-tuneable
solution that accomodates to the specifics of the project analyzed.

Reviewers: martong, balazske, Szelethus

Subscribers: whisperity, xazax.hun, baloghadamsoftware, szepet, rnkovacs, a.sidorin, mikhail.ramalho, Szelethus, donat.nagy, dkrupp, Charusso, steakhal, ASDenysPetrov, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D82561
2020-07-01 10:08:52 +02:00
Sam McCall f12cd99c44 [clangd] Config: compile Fragment -> CompiledFragment -> Config
Subscribers: mgorny, ilya-biryukov, MaskRay, jkorous, arphaman, kadircet, usaxena95, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D82612
2020-07-01 10:04:19 +02:00
Hans Wennborg a8e582c830 [ThinLTO] Always parse module level inline asm with At&t dialect (PR46503)
clang-cl passes -x86-asm-syntax=intel to the cc1 invocation so that
assembly listings produced by the /FA flag are printed in Intel dialect.
That flag however should not affect the *parsing* of inline assembly in
the program. (See r322652)

When compiling normally, AsmPrinter::emitInlineAsm is used for
assembling and defaults to At&t dialect. However, when compiling for
ThinLTO, the code which parses module level inline asm to find symbols
for the symbol table was failing to set the dialect. This patch fixes
that. (See the bug for more details.)

Differential revision: https://reviews.llvm.org/D82862
2020-07-01 09:43:45 +02:00
Saiyedul Islam 9182316395 [AMDGPU] Spill more than wavesize CSR SGPRs
In case of more than wavesize CSR SGPR spills, lanes of reserved VGPR were getting
overwritten due to wrap around.

Reserve a VGPR (when NumVGPRSpillLanes = 0, WaveSize, 2*WaveSize, ..) and when one
of the two conditions is true:
 1. One reserved VGPR being tracked by VGPRReservedForSGPRSpill is not yet reserved.
 2. All spill lanes of reserved VGPR(s) are full and another spill lane is required.

Reviewed By: arsenm, kerbowa

Differential Revision: https://reviews.llvm.org/D82463
2020-07-01 07:40:47 +00:00
Sam Parker 3ee580d017 [ARM][LowOverheadLoops] Handle reductions
While validating live-out values, record instructions that look like
a reduction. This will comprise of a vector op (for now only vadd),
a vorr (vmov) which store the previous value of vadd and then a vpsel
in the exit block which is predicated upon a vctp. This vctp will
combine the last two iterations using the vmov and vadd into a vector
which can then be consumed by a vaddv.

Once we have determined that it's safe to perform tail-predication,
we need to change this sequence of instructions so that the
predication doesn't produce incorrect code. This involves changing
the register allocation of the vadd so it updates itself and the
predication on the final iteration will not update the falsely
predicated lanes. This mimics what the vmov, vctp and vpsel do and
so we then don't need any of those instructions.

Differential Revision: https://reviews.llvm.org/D75533
2020-07-01 08:31:49 +01:00
serge-sans-paille ffee804053 Correctly track GCOVProfiling IR update
Differential Revision: https://reviews.llvm.org/D82742
2020-07-01 09:30:59 +02:00