208 Commits

Author	SHA1	Message	Date
Vikram S. Adve	7366fa1aa6	(1) Added special register class containing (for now) %fsr. ... Fixed spilling of %fcc[0-3] which are part of %fsr. (2) Moved some machine-independent reg-class code to class TargetRegInfo from SparcReg{Class,}Info. (3) Renamed MachienOperand::opIsDef to MachineOperand::opIsDefOnly() and related functions and flags. Fixed several bugs where only "isDef" was being checked, not "isDefAndUse". llvm-svn: 6341	2003-05-27 00:05:23 +00:00
Chris Lattner	584bae4733	* Keep the BBMap around as long as the pass is live ... * Change getVarInfo to take real virtual register numbers and offset them itself. This has caused me so much grief, it's not even funny. llvm-svn: 6115	2003-05-12 14:24:00 +00:00
Chris Lattner	5ab42e5739	Add a vector to keep track of which registers are allocatable. Remove FIXMEs ... llvm-svn: 6015	2003-05-07 20:08:36 +00:00
Chris Lattner	9eb2172176	Re-add gross hack, it's still necessary. :( ... llvm-svn: 6012	2003-05-06 21:44:54 +00:00
Chris Lattner	824698b891	Remove hideously nasty hack ... llvm-svn: 6011	2003-05-06 21:32:39 +00:00
Chris Lattner	f641fd08bc	Minor cleanup ... llvm-svn: 5976	2003-05-01 21:18:47 +00:00
Chris Lattner	b4d58d7f9e	Rename MachineInstrInfo -> TargetInstrInfo ... llvm-svn: 5272	2003-01-14 22:00:31 +00:00
Chris Lattner	cab0b442f2	New files ... llvm-svn: 5262	2003-01-13 20:01:16 +00:00