Commit Graph

137 Commits

Author SHA1 Message Date
Evan Cheng e349d01acf We were not adjusting the frame size to ensure proper alignment when alloca /
vla are present in the function. This causes a crash when a leaf function
allocates space on the stack used to store / load with 128-bit SSE
instructions.

llvm-svn: 27698
2006-04-14 07:26:43 +00:00
Evan Cheng c9ed8e4c1a Use movaps to do VR128 reg-to-reg copies for now. It's shorter and available for SSE1.
llvm-svn: 27554
2006-04-10 07:21:31 +00:00
Jim Laskey 2d7298c362 Foundation for call frame information.
llvm-svn: 27491
2006-04-07 16:34:46 +00:00
Evan Cheng 8f3b6b8d8a Minor fixes + naming changes.
llvm-svn: 27410
2006-04-04 19:12:30 +00:00
Jim Laskey d1aa1638c6 Expose base register for DwarfWriter. Refactor code accordingly.
llvm-svn: 27225
2006-03-28 13:48:33 +00:00
Jim Laskey fa53b276d0 Translate llvm target registers to dwarf register numbers properly.
llvm-svn: 27180
2006-03-27 20:18:45 +00:00
Jim Laskey 3c43609f1f Add support to locate local variables in frames (early version.)
llvm-svn: 26994
2006-03-23 18:12:57 +00:00
Evan Cheng 9bf978dc20 Use the generic vector register classes VR64 / VR128 rather than V4F32,
V8I16, etc.

llvm-svn: 26838
2006-03-18 01:23:20 +00:00
Evan Cheng bfc2e97383 Also fold MOV8r0, MOV16r0, MOV32r0 + store to MOV8mi, MOV16mi, and MOV32mi.
llvm-svn: 26817
2006-03-17 02:36:22 +00:00
Evan Cheng aca7915b70 Add some missing entries to X86RegisterInfo::foldMemoryOperand(). e.g.
ADD32ri8.

llvm-svn: 26816
2006-03-17 02:25:01 +00:00
Evan Cheng 42d5ac557c Fix an obvious bug exposed when we are doing
ADD X, 4
==>
MOV32ri $X+4, ...

llvm-svn: 26366
2006-02-25 01:37:02 +00:00
Evan Cheng fa57a0add9 Added SSE2 128-bit integer packed types: V16I8, V8I16, V4I32, and V2I64.
Added generic vector types: VR64 and VR128.

llvm-svn: 26295
2006-02-21 01:38:21 +00:00
Evan Cheng 43070b7541 Added x86 integer vector types: 64-bit packed byte integer (v16i8), 64-bit
packed word integer (v8i16), and 64-bit packed doubleword integer (v2i32).

llvm-svn: 26294
2006-02-20 22:34:53 +00:00
Evan Cheng 24c461b51e 1. Use pxor instead of xoraps / xorapd to clear FR32 / FR64 registers. This
proves to be worth 20% on Ptrdist/ks. Might be related to dependency
   breaking support.
2. Added FsMOVAPSrr and FsMOVAPDrr as aliases to MOVAPSrr and MOVAPDrr. These
   are used for FR32 / FR64 reg-to-reg copies.
3. Tell reg-allocator to generate MOVSSrm / MOVSDrm and MOVSSmr / MOVSDmr to
   spill / restore FsMOVAPSrr and FsMOVAPDrr.

llvm-svn: 26241
2006-02-16 22:45:17 +00:00
Evan Cheng 3f99628939 Use movaps / movapd to spill / restore V4F4 / V2F8 registers.
llvm-svn: 26240
2006-02-16 21:20:26 +00:00
Evan Cheng ae82498e81 Use movaps / movapd (instead of movss / movsd) to do FR32 / FR64 reg to reg
transfer.

According to the Intel P4 Optimization Manual:

Moves that write a portion of a register can introduce unwanted
dependences. The movsd reg, reg instruction writes only the bottom
64 bits of a register, not to all 128 bits. This introduces a dependence on
the preceding instruction that produces the upper 64 bits (even if those
bits are not longer wanted). The dependence inhibits register renaming,
and thereby reduces parallelism.

Not to mention movaps is shorter than movss.

llvm-svn: 26226
2006-02-16 01:50:02 +00:00
Chris Lattner c408558638 When rewriting frame instructions, emit the appropriate small-immediate
instruction when possible.

llvm-svn: 25938
2006-02-03 18:20:04 +00:00
Chris Lattner bb53acd03c Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far more logical place. Other methods should also be moved if anyoneis interested. :)
llvm-svn: 25913
2006-02-02 20:12:32 +00:00
Chris Lattner 246ee44c8f implement isStoreToStackSlot
llvm-svn: 25911
2006-02-02 20:00:41 +00:00
Evan Cheng f1ed826c2a Added SSE entries to foldMemoryOperand().
llvm-svn: 25888
2006-02-01 23:02:25 +00:00
Evan Cheng 9c249c37f8 Support for ADD_PARTS, SUB_PARTS, SHL_PARTS, SHR_PARTS, and SRA_PARTS.
llvm-svn: 25158
2006-01-09 18:33:28 +00:00
Evan Cheng 172fce7050 * Fast call support.
* FP cmp, setcc, etc.

llvm-svn: 25117
2006-01-06 00:43:03 +00:00
Evan Cheng 782b654e6f Let the helper functions know about X86::FR32RegClass and X86::FR64RegClass.
llvm-svn: 25004
2005-12-24 09:48:35 +00:00
Evan Cheng 9ae486047e * Removed the use of FLAG. Now use hasFlagIn and hasFlagOut instead.
* Added a pseudo instruction (for each target) that represent "return void".
  This is a workaround for lack of optional flag operand (return void is not
  lowered so it does not have a flag operand.)

llvm-svn: 24997
2005-12-23 22:14:32 +00:00
Chris Lattner f431ad4477 Rewrite FP stackifier support in the X86InstrInfo.td file, splitting patterns
that were overloaded to work before and after the stackifier runs.  With the
new clean world, it is possible to write patterns for these instructions: woo!

This also adds a few simple patterns here and there, though there are a lot
still missing.  These should be easy to add though. :)

See the comments under "Floating Point Stack Support" for more details on
the new world order.

This patch as absolutely no effect on the generated code, woo!

llvm-svn: 24899
2005-12-21 07:47:04 +00:00
Nate Begeman 9d7008b08d Properly split f32 and f64 into separate register classes for scalar sse fp
fixing a bunch of nasty hackery

llvm-svn: 23735
2005-10-14 22:06:00 +00:00
Chris Lattner bb1c9ecb17 simplify this code using the new regclass info passed in
llvm-svn: 23557
2005-09-30 17:12:38 +00:00
Chris Lattner a654525c1c Pass extra regclasses into spilling code
llvm-svn: 23537
2005-09-30 01:29:42 +00:00
Chris Lattner de3c87a2ab Implement the isLoadFromStackSlot interface
llvm-svn: 23387
2005-09-19 05:23:44 +00:00
Chris Lattner 8ad3700a3e The simple isel being gone makes this dead!
llvm-svn: 22914
2005-08-19 18:32:03 +00:00
Jeff Cohen 5f4ef3c5a8 Eliminate all remaining tabs and trailing spaces.
llvm-svn: 22523
2005-07-27 06:12:32 +00:00
Nate Begeman 8a0933608a First round of support for doing scalar FP using the SSE2 ISA extension and
XMM registers.  There are many known deficiencies and fixmes, which will be
addressed ASAP.  The major benefit of this work is that it will allow the
LLVM register allocator to allocate FP registers across basic blocks.

The x86 backend will still default to x87 style FP.  To enable this work,
you must pass -enable-sse-scalar-fp and either -sse2 or -sse3 to llc.

An example before and after would be for:
double foo(double *P) { double Sum = 0; int i; for (i = 0; i < 1000; ++i)
                        Sum += P[i]; return Sum; }

The inner loop looks like the following:
x87:
.LBB_foo_1:     # no_exit
        fldl (%esp)
        faddl (%eax,%ecx,8)
        fstpl (%esp)
        incl %ecx
        cmpl $1000, %ecx
        #FP_REG_KILL
        jne .LBB_foo_1  # no_exit

SSE2:
        addsd (%eax,%ecx,8), %xmm0
        incl %ecx
        cmpl $1000, %ecx
        #FP_REG_KILL
        jne .LBB_foo_1  # no_exit

llvm-svn: 22340
2005-07-06 18:59:04 +00:00
Chris Lattner 97e3b65652 Teach reginfo how to deal with ADJSTACKPTRri, allowing us to generate:
add %ESP, 20
        jmp %EDX  # TAIL CALL

instead of:
        add %ESP, -8
        add %ESP, 28
        jmp %EDX  # TAIL CALL

llvm-svn: 22047
2005-05-15 05:49:58 +00:00
Chris Lattner 5366c859a7 When emitting the function epilog, check to see if there already a stack
adjustment.  If so, we merge the adjustment into the existing one.  This
allows us to generate:

caller2:
        sub %ESP, 12
        mov DWORD PTR [%ESP], 0
        mov %EAX, 1234567890
        mov %EDX, 0
        call func2
        add %ESP, 8
        ret 4

intead of:

caller2:
        sub %ESP, 12
        mov DWORD PTR [%ESP], 0
        mov %EAX, 1234567890
        mov %EDX, 0
        call func2
        sub %ESP, 4
        add %ESP, 12
        ret 4

for X86/fast-cc-merge-stack-adj.ll

llvm-svn: 22038
2005-05-14 23:53:43 +00:00
Chris Lattner f0649db870 Add some new instructions
llvm-svn: 22036
2005-05-14 23:35:21 +00:00
Chris Lattner c0e369ed66 switch to having the callee pop stack operands for fastcc. This is currently buggy
do not use

llvm-svn: 21984
2005-05-13 21:44:04 +00:00
Chris Lattner 1a12476531 allow RETI
llvm-svn: 21980
2005-05-13 20:46:35 +00:00
Chris Lattner c21db6b15c add signed versions of the extra precision multiplies
llvm-svn: 21106
2005-04-06 04:19:22 +00:00
Chris Lattner 0edf9535b9 Add rotate instructions.
llvm-svn: 19690
2005-01-19 07:50:03 +00:00
Chris Lattner d54845f530 Improve coverage of the X86 instruction set by adding 16-bit shift doubles.
llvm-svn: 19687
2005-01-19 07:31:24 +00:00
Chris Lattner 5b589ec0c4 Add conditional moves for the parity flag.
llvm-svn: 19437
2005-01-10 22:09:33 +00:00
Chris Lattner b62b45b3fc Add support for SETNPr to lower to memory form.
llvm-svn: 19248
2005-01-02 02:37:46 +00:00
Chris Lattner 33660426a5 Spill/restore X86 floating point stack registers with 64-bits of precision
instead of 80-bits of precision.  This fixes PR467.

This change speeds up fldry on X86 with LLC from 7.32s on apoc to 4.68s.

llvm-svn: 18433
2004-12-02 18:17:31 +00:00
Chris Lattner e9bfa5a2a4 Add some new instructions. Fix the asm string for sbb32rr
llvm-svn: 16759
2004-10-06 04:01:02 +00:00
Reid Spencer 7c16caa336 Changes For Bug 352
Move include/Config and include/Support into include/llvm/Config,
include/llvm/ADT and include/llvm/Support. From here on out, all LLVM
public header files must be under include/llvm/.

llvm-svn: 16137
2004-09-01 22:55:40 +00:00
Chris Lattner 7c98308013 Reduce uses of getRegClass
llvm-svn: 15973
2004-08-21 20:13:52 +00:00
Chris Lattner a0b38d3cb1 Code insertion methods now return void instead of an int.
llvm-svn: 15780
2004-08-15 22:15:11 +00:00
Chris Lattner 98de1d7795 These methods no longer take a TargetRegisterClass* operand.
llvm-svn: 15774
2004-08-15 21:56:44 +00:00
Nate Begeman a4da0d6294 Eliminate MachineFunction& argument from eliminateFrameIndex in x86 Target. Get MachineFunction from MachineInstruction's parent's parent
llvm-svn: 15739
2004-08-14 22:05:10 +00:00
Chris Lattner 8a4039ed9a Reserve the correct amt of space.
llvm-svn: 14913
2004-07-17 20:24:05 +00:00