26d6a0449a
Convert 'and' to single instance of a multipattern
...
which instantiates the 34 versions of and all in one
swoop. The BaseOpc/BaseOpc2/BaseOpc4 stuff should not
be required, but tblgen's feeble brain explodes when I
use Or4<BaseOpc>.V in the multipattern.
No change in the generated .inc files.
llvm-svn: 115893
2010-10-07 01:10:20 +00:00
5b255c2dd6
Allow use of the 16-bit literal move instruction in CMOVs for Thumb2 mode.
...
llvm-svn: 115890
2010-10-07 00:53:56 +00:00
b71a77d7b8
add a new BinOpAI class to represent the immediate form that directly acts on EAX.
...
This does change the generated .inc files to include the implicit use/def of eax.
Since these instructions are only generated by the assembler and disassembler it
doesn't actually matter though.
llvm-svn: 115885
2010-10-07 00:43:39 +00:00
742adc328a
Allow use of the 16-bit literal move instruction in CMOVs for ARM mode.
...
llvm-svn: 115884
2010-10-07 00:42:42 +00:00
894d2e6146
add a bunch of classes for other common patterns.
...
As usual, no change in generated .inc files.
llvm-svn: 115882
2010-10-07 00:35:28 +00:00
6da4d820fa
Since the Hello pass is built as a loadable dynamic library, don't try to convert it to new-style registration yet.
...
llvm-svn: 115881
2010-10-07 00:31:16 +00:00
e17d7212f1
Define a new BinOpRI8 class and use it to define the imm8 versions of and.
...
llvm-svn: 115880
2010-10-07 00:12:45 +00:00
b19bae4e3e
Constrain the offset register to a *_NOSP register class when inserting LEA
...
instructions.
This unbreaks the machine code verifier and fixes PR8317.
llvm-svn: 115879
2010-10-07 00:07:26 +00:00
356f16c142
add the pattern operator to match to X86TypeInfo, use this to
...
convert AND64ri32 to use BinOpRI.
llvm-svn: 115878
2010-10-07 00:01:39 +00:00
bf7cffc730
add a common SDPatternOperator base class to SDNode and PatFrag for
...
stuff that wants to take one or the other. These can both be used
as the operation of a dag in a pattern match.
llvm-svn: 115877
2010-10-07 00:01:00 +00:00
b2dd88db6b
Properly handle GR32_NOSP in X86RegisterInfo::getMatchingSuperRegClass.
...
This function looks like it is about ready to be generated by TebleGen.
llvm-svn: 115876
2010-10-06 23:56:46 +00:00
18842783cc
Add MachineRegisterInfo::constrainRegClass and use it in MachineCSE.
...
This function is intended to be used when inserting a machine instruction that
trivially restricts the legal registers, like LEA requiring a GR32_NOSP
argument.
llvm-svn: 115875
2010-10-06 23:54:39 +00:00
1a065e4e5b
Skip unused registers when verifying LiveIntervals.
...
llvm-svn: 115874
2010-10-06 23:54:35 +00:00
c473587e28
Fixed RELEASE_28 tags.
...
llvm-svn: 115872
2010-10-06 23:50:30 +00:00
25cd3bfbd7
remove trailing whitespace
...
llvm-svn: 115860
2010-10-06 22:46:47 +00:00
bff84d418f
First in a sequence of ARM/MC/*ELF* specific work.
...
Lifted the EmitRawText calls to ARMAsmPrinter::emitAttribute()
Added ARMAsmPrinter::emitAttributes() (plural s).
TODO:
.cpu attribute needs to be refactored
llvm-svn: 115859
2010-10-06 22:36:46 +00:00
883936ce0b
Another case of 256 sections not being enough :-)
...
llvm-svn: 115858
2010-10-06 22:28:19 +00:00
af08ad4350
Appease the clang self-host buildbot by providing a correct instantiation.
...
llvm-svn: 115857
2010-10-06 22:23:20 +00:00
24ab1ce8c2
Clean up MOVi32imm and t2MOVi32imm pseudo instruction definitions.
...
llvm-svn: 115853
2010-10-06 22:01:26 +00:00
f49540cb4f
Kill of the vestiges of the 'call' Modifier (no longer needed for PLT).
...
llvm-svn: 115845
2010-10-06 21:36:43 +00:00
2c95027258
Now that VDUPfqf and VDUPfdfare properly pseudos, kill the no-longer-needed
...
"lane" operand modifier.
llvm-svn: 115843
2010-10-06 21:22:32 +00:00
b270f28c1a
Now that VDUPfqf and VDUPfdfare properly pseudos, nuke the special handling.
...
llvm-svn: 115841
2010-10-06 21:17:07 +00:00
2e3e2a006b
Change the NEON VDUPfdf and VDUPfqf pseudo-instructions to actually be
...
pseudo instructions.
llvm-svn: 115840
2010-10-06 21:16:16 +00:00
436bc5fdb3
Fix libc++ link in release notes.
...
llvm-svn: 115837
2010-10-06 21:07:30 +00:00
5f2d6a5cd9
Get binding and visibility info from the the alias, but Type from the symbol
...
being aliased.
llvm-svn: 115836
2010-10-06 21:02:29 +00:00
ad8134f03b
Hide analysis group registration behind a macro, just like pass registration.
...
llvm-svn: 115835
2010-10-06 21:02:27 +00:00
9a33ec24eb
Add support for DW_TAG_unspecified_parameters.
...
llvm-svn: 115833
2010-10-06 20:50:40 +00:00
233b3a2f95
Add a 'pattern' arg to the ARM PseudoNeonI class.
...
llvm-svn: 115831
2010-10-06 20:36:55 +00:00
e535b01a74
MC: Add missing forward in MCLoggingStreamer.
...
llvm-svn: 115830
2010-10-06 20:36:47 +00:00
7fb03204cd
Cleanup Whitespace.
...
llvm-svn: 115829
2010-10-06 20:36:38 +00:00
5ed50b6151
Revert "RequiresUnique" patch. This should be handled at a lower level.
...
llvm-svn: 115827
2010-10-06 20:18:44 +00:00
b93cf04d9a
Pass initialization functions should take a PassRegistry as a parameter
...
rather than being fixed to the global registry.
llvm-svn: 115824
2010-10-06 20:07:03 +00:00
d444577382
If a symbol is global, reloc against it even if it is in a mergeable section.
...
llvm-svn: 115817
2010-10-06 19:27:21 +00:00
ec0da969fb
Remove unused variables.
...
llvm-svn: 115802
2010-10-06 18:11:50 +00:00
3ab7e510e9
Remove compatibilty code for old-style multiple return values.
...
llvm-svn: 115799
2010-10-06 16:59:24 +00:00
8025f89860
target operand flag values aren't a bitmask
...
llvm-svn: 115798
2010-10-06 16:51:55 +00:00
83b2a3337f
Make sure weak symbols are listed after the local ones.
...
llvm-svn: 115795
2010-10-06 16:47:31 +00:00
8f3d2c9058
Correctly handle GOTPCREL relocations.
...
llvm-svn: 115793
2010-10-06 16:23:36 +00:00
aadc5596f1
ComputeLinearIndex doesn't need its TLI argument.
...
llvm-svn: 115792
2010-10-06 16:18:29 +00:00
3f0068d661
Constify isReachableFromEntry.
...
llvm-svn: 115788
2010-10-06 15:49:14 +00:00
5af766bb1e
Add missing "-" to the command line.
...
llvm-svn: 115777
2010-10-06 11:43:06 +00:00
546548036c
Remove tabs.
...
llvm-svn: 115764
2010-10-06 07:19:18 +00:00
10f60fa411
Change RequiresMerge to RequiresUnique. It's a better description of what this
...
fix is trying to accomplish.
This code could still use some polishing.
llvm-svn: 115759
2010-10-06 07:03:52 +00:00
6f2ae72c90
No need to check out everything: binutils is enough.
...
Patch by John Tytgat.
llvm-svn: 115757
2010-10-06 06:45:11 +00:00
49d4c0bd18
- Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This
...
allow target to correctly compute latency for cases where static scheduling
itineraries isn't sufficient. e.g. variable_ops instructions such as
ARM::ldm.
This also allows target without scheduling itineraries to compute operand
latencies. e.g. X86 can return (approximated) latencies for high latency
instructions such as division.
- Compute operand latencies for those defined by load multiple instructions,
e.g. ldm and those used by store multiple instructions, e.g. stm.
llvm-svn: 115755
2010-10-06 06:27:31 +00:00
cd8fe46d4b
If the destination module all ready has a copy of the global coming from the
...
source module *and* it must be merged (instead of simply replaced or appended
to), then merge instead of replacing or adding another global.
The ObjC __image_info section was being appended to because of this
failure. This caused a crash because the linker expects the image info section
to be a specific size.
<rdar://problem/8198537>
llvm-svn: 115753
2010-10-06 06:16:30 +00:00
6e85be2ecf
enhance X86TypeInfo to include information about the encoding and
...
operand kind for immediates. Use these to define a new BinOpRI
class and switch AND8/16/32ri over to it. AND64ri32 needs some
more refactoring before it can make the switcheroo.
llvm-svn: 115752
2010-10-06 05:55:42 +00:00
3d7ec7b55d
Update release location.
...
llvm-svn: 115749
2010-10-06 05:36:01 +00:00
94eff91dc0
add a class for _REV nodes.
...
llvm-svn: 115748
2010-10-06 05:35:22 +00:00
a46073b56b
sink more intelligence into the ITy base class. Now it knows
...
that i8 operations are even and i16,i32,i64 operations have a
low opcode bit set (they are odd).
llvm-svn: 115747
2010-10-06 05:28:38 +00:00
b6da2be7e8
refactor things a bit, now the REX_W and OpSize prefix bytes are inferred from the type info.
...
llvm-svn: 115745
2010-10-06 05:20:57 +00:00
7bbd809b6c
with tblgen suitably extended, we can now get the load node from typeinfo.
...
llvm-svn: 115744
2010-10-06 04:58:43 +00:00
28f034c21a
Generalize tblgen's dag parsing logic to handle arbitrary expressions
...
as the operator of the dag. Specifically, this allows parsing things
like (F.x 4) in addition to just (a 4).
Unfortunately, this runs afoul of an idiom being used by llvmc. It
is using dags like (foo [1,2,3]) to represent a list of stuff being
passed into foo. With this change, this is parsed as a [1,2,3]
subscript on foo instead of being the first argument to the dag.
Cope with this in the short term by requiring a "-llvmc-temp-hack"
argument to tblgen to get the old parsing behavior.
llvm-svn: 115742
2010-10-06 04:55:48 +00:00
805b74d650
rename add some comments.
...
llvm-svn: 115741
2010-10-06 04:37:17 +00:00
7d5bb96723
filecheckize
...
llvm-svn: 115740
2010-10-06 04:36:30 +00:00
e76cfcf8a8
cleanups
...
llvm-svn: 115739
2010-10-06 04:31:40 +00:00
ad205575fc
lib/System/Win32/Signals.inc: Enable LLVM_DISABLE_CRT_DEBUG also on mingw.
...
llvm-svn: 115731
2010-10-06 02:15:22 +00:00
0198ce06fc
Provide a fast "get me the target triple from the module" API. This can
...
drastically reduce the linking time during LTO.
Patch by Shantonu Sen!
llvm-svn: 115728
2010-10-06 01:22:42 +00:00
1fc81e90f7
lets go all meta and define new X86 type wrappers that declare the associated
...
gunk that goes along with an MVT (e.g. reg class, preferred load operation,
memory operand)
llvm-svn: 115727
2010-10-06 00:45:24 +00:00
eadaeaab93
introduce a new BinOpRM class and use it to factor AND*rm. This points out
...
that I need a heavier handed approach to get ultimate factorization.
llvm-svn: 115726
2010-10-06 00:30:49 +00:00
9402633637
remove the !nameconcat tblgen feature. It "shorthand" and only used in 4 places
...
where !cast is just as short.
llvm-svn: 115722
2010-10-06 00:19:21 +00:00
04c342ea20
replace stuff like:
...
let AsmString = !strconcat(
!strconcat(!strconcat(opc, "${p}"), !strconcat(".", dt)),
!strconcat("\t", asm));
with:
let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
:)
llvm-svn: 115720
2010-10-06 00:05:18 +00:00
61ea00b494
allow !strconcat to take more than two operands to eliminate
...
!strconcat(!strconcat(!strconcat(!strconcat
Simplify some x86 td files to use it.
llvm-svn: 115719
2010-10-05 23:58:18 +00:00
d7565c3a06
Use a relocation against the symbol if it is a PLT and the symbol is in another
...
section. Common because of linkonce sections.
llvm-svn: 115718
2010-10-05 23:57:26 +00:00
b9f2d50d5f
Comment out fastisel debugging message.
...
llvm-svn: 115717
2010-10-05 23:50:58 +00:00
97b1368ae3
associate the instruction suffix letter with the integer gpr
...
register class, and use this to simplify use of BinOpRR.
llvm-svn: 115716
2010-10-05 23:43:04 +00:00
7359194b63
introduce a new BinOpRR class, and convert 4 and instructions to use it.
...
llvm-svn: 115715
2010-10-05 23:32:05 +00:00
8cfc459274
Random cleanup and make the intermediate register in fptosi a
...
32-bit fp reg, not 64-bit.
Fixes SingleSource.
llvm-svn: 115711
2010-10-05 23:13:24 +00:00
4d5156c7d0
Count uses in all nested loops, not just the deepest.
...
llvm-svn: 115710
2010-10-05 23:10:12 +00:00
56e2925e6c
Remove SplitAnalysis::removeUse. It was only used to make SplitAnalysis
...
reusable, but that is no longer relevant since a split will always replace the
original.
llvm-svn: 115709
2010-10-05 23:10:09 +00:00
0445e2a053
dupli always has an interval now.
...
llvm-svn: 115708
2010-10-05 23:10:04 +00:00
cff5b0ea36
Move cmov pseudo instructions to InstrCompiler,
...
convert all the rest of the cmovs to the multiclass,
with good results:
X86InstrCMovSetCC.td | 598 +--------------------------------------------------
X86InstrCompiler.td | 61 +++++
2 files changed, 77 insertions(+), 582 deletions(-)
llvm-svn: 115707
2010-10-05 23:09:10 +00:00
1a1c600110
Use #NAME# to have the CMOV multiclass define things with the same names as before
...
(e.g. CMOVBE16rr instead of CMOVBErr16).
llvm-svn: 115705
2010-10-05 23:00:14 +00:00
b8ff8f0cb6
when david added support for #NAME# he didn't update the comments and
...
tried (but failed) to artificially constrain it to working with #NAME#.
Just allow any # in identifiers, and update the comments.
llvm-svn: 115704
2010-10-05 22:59:29 +00:00
c25b39702f
Another step towards getting rid of static ctors for pass registration: have INITIALIZE_PASS AND INITIALIZE_AG_PASS
...
expand to an initializeMyPass() function (in additional to the extant static ctors). Eventually, these will be called
from a big InitializeAllPasses() function, and the PassInfo's they create (which would be leaked if this code were used
at the moment) will be handed off to a PassRegistry for ownership.
llvm-svn: 115703
2010-10-05 22:58:16 +00:00
7538ed80a9
enhance tblgen to support anonymous defm's, use this to
...
simplify the X86 CMOVmr's.
llvm-svn: 115702
2010-10-05 22:51:56 +00:00
fa25dd9548
convert cmov mr patterns to use a multipattern. Death to redundancy
...
and verbosity
llvm-svn: 115701
2010-10-05 22:42:54 +00:00
0ad137e98e
Implement more alias cases.
...
llvm-svn: 115699
2010-10-05 22:26:43 +00:00
0067ee02f9
switch CMOVBE to the multipattern:
...
21 insertions(+), 53 deletions(-)
Moar change coming before I switch the rest.
llvm-svn: 115697
2010-10-05 22:23:58 +00:00
2dfa8be26a
We can split around loops with multiple exits now.
...
llvm-svn: 115696
2010-10-05 22:19:35 +00:00
89d276aa48
Update SplitEditor API to reflect the fact that the original live interval is
...
never kept after splitting.
Keeping the original interval made sense when the split region doesn't modify
the register, and the original is spilled. We can get the same effect by
detecting reloaded values when spilling around copies.
llvm-svn: 115695
2010-10-05 22:19:33 +00:00
b46d32367f
Intervals are half-open.
...
llvm-svn: 115694
2010-10-05 22:19:29 +00:00
907d86db22
fix a bug I introduced in r115669, which ended up with MOV64mr_TC
...
not getting marked as mayStore. This fixes llvm-gcc bootstrap.
llvm-svn: 115693
2010-10-05 22:16:48 +00:00
c3a767e9b0
add a multiclass for cmov's, but don't start using it yet.
...
llvm-svn: 115692
2010-10-05 22:01:02 +00:00
10a0fdeab5
PSHUFW is in SSE, not SSSE3.
...
llvm-svn: 115691
2010-10-05 21:58:12 +00:00
aa02c1c91d
use a multipattern to define setcc instructions:
...
X86InstrCMovSetCC.td | 200 ++++++---------------------------------------------
1 file changed, 27 insertions(+), 173 deletions(-)
llvm-svn: 115689
2010-10-05 21:34:29 +00:00
3844da781f
256 sections should be enough for anyone...
...
llvm-svn: 115687
2010-10-05 21:20:07 +00:00
8f4f1d1136
move SETB pseudos into the same place in InstrCompiler.td
...
llvm-svn: 115686
2010-10-05 21:18:04 +00:00
13111b08fb
Replace a gross hack (the MOV64ri_alt instruction) with a slightly less
...
gross hack (having the asmmatcher handle the alias).
llvm-svn: 115685
2010-10-05 21:09:45 +00:00
c58a37ea51
Don't crash in a strange .size directive.
...
llvm-svn: 115684
2010-10-05 21:02:45 +00:00
ab85ef9e55
distribute the rest of the contents of X86Instr64bit.td out to
...
the right places. X86Instr64bit.td now dies, long live x86-64!
llvm-svn: 115669
2010-10-05 20:49:15 +00:00
671bab1c7d
When we find a reaching definition, make sure it is visited from all paths by
...
erasing it from the visited set. That ensures we create the right phi defs.
llvm-svn: 115666
2010-10-05 20:36:28 +00:00
b0cedd5f96
Don't use nextIndex to check for live out of instruction.
...
Insert copy after defining instruction.
Fix LiveIntervalMap::extendTo to properly handle live segments starting before
the current basic block.
Make sure the open live range is extended to the inserted copy's use slot.
llvm-svn: 115665
2010-10-05 20:36:25 +00:00
c1526595b3
trailing whitespace
...
llvm-svn: 115664
2010-10-05 20:35:57 +00:00
27c763d342
move the rest of the simple 64-bit arithmetic into InstrArithmetic.td
...
llvm-svn: 115663
2010-10-05 20:35:37 +00:00
0e008f18cb
Remove trailing space. This is just an excuse to poke the
...
buildbots, since I seem to have blown up the build master :(
llvm-svn: 115662
2010-10-05 20:32:15 +00:00
c2f5e5764f
continue moving 64-bit stuff into X86InstrArithmetic.td
...
llvm-svn: 115660
2010-10-05 20:23:31 +00:00
a65d17a5ca
Fix Punctuation.
...
llvm-svn: 115657
2010-10-05 19:48:12 +00:00
a3b34ed2df
MC-COFF: Fix (PR8278) temporary symbol relocations.
...
llvm-svn: 115656
2010-10-05 19:48:03 +00:00
b91bac6c96
Add support for a fill value in the .zero directive.
...
llvm-svn: 115655
2010-10-05 19:42:57 +00:00
9a414901db
Tweak VNInfo printing.
...
llvm-svn: 115650
2010-10-05 18:48:57 +00:00
1c9afa1aeb
Add assert for valid slot indexes.
...
llvm-svn: 115649
2010-10-05 18:48:55 +00:00
e929899a3f
Increase the number of bits used internally by the ARM target to represent the
...
addressing mode from four to five.
llvm-svn: 115645
2010-10-05 18:14:55 +00:00
b1d0789357
Implement a simple alias case and refactor the code a bit so that the
...
isInSymtab and isLocal logic in the two loops don't get easily out of sync.
llvm-svn: 115643
2010-10-05 18:01:23 +00:00
8ccdd25fbd
test/COFF: Fix symbol indexes and names. Update tests to match.
...
llvm-svn: 115642
2010-10-05 17:57:08 +00:00
f6230d1d4b
test/COFF: Remove temp file usage.
...
llvm-svn: 115641
2010-10-05 17:56:56 +00:00
e58f37f74d
test/coff-dump: Support reading from stdin.
...
llvm-svn: 115640
2010-10-05 17:56:46 +00:00
868aaf3c3d
Cleanup Whitespace.
...
llvm-svn: 115639
2010-10-05 17:56:37 +00:00
d8d1dcc09a
Use a more efficient lowering of uint64_t --> float that can take advantage of hardware signed integer conversion without
...
having to do a double cast (uint64_t --> double --> float). This is based on the algorithm from compiler_rt's __floatundisf
for X86-64.
llvm-svn: 115634
2010-10-05 17:24:05 +00:00
7552d15d19
move 64-bit add and adc to InstrArithmetic.
...
llvm-svn: 115632
2010-10-05 16:59:08 +00:00
182e87caaf
rewrote two addr constraints so that they are only set, not set and then nestedly cleared.
...
llvm-svn: 115631
2010-10-05 16:52:25 +00:00
39c70f4833
split the 32-bit integer arithmetic instructions out to their own file.
...
llvm-svn: 115627
2010-10-05 16:39:12 +00:00
c4abc7036d
Update attribute reading for the changed source location code.
...
llvm-svn: 115624
2010-10-05 15:59:36 +00:00
d03e81dba8
Produce a undefined reference to _GLOBAL_OFFSET_TABLE_ when needed.
...
llvm-svn: 115623
2010-10-05 15:48:37 +00:00
259bcdad06
Tests that now pass.
...
llvm-svn: 115622
2010-10-05 15:43:32 +00:00
6547a50f49
After printing "Running 'Graphviz' program... " and running the
...
Graphviz program, print something with a newline, to avoid leaving
the line unfinished.
llvm-svn: 115620
2010-10-05 15:30:27 +00:00
bce26a1ee0
On ELF we need to know which symbols are used in relocations to decide if
...
they should be in the symbol table or not. Instead of "guessing", just compute
the symbol table after the relocations are known.
llvm-svn: 115619
2010-10-05 15:11:03 +00:00
9ddb678d45
Properly deserialize Clang types that are used as attribute arguments
...
llvm-svn: 115616
2010-10-05 14:51:48 +00:00
7681b41720
test/CodeGen/X86/atomic_op.ll: Rename @main to @func. Extra sequences will be inserted to @main as prologue on cygming, to fail.
...
llvm-svn: 115611
2010-10-05 11:16:24 +00:00
1818dd510e
integrate the 64-bit shifts into X86InstrShiftRotate.td. Enough for tonight.
...
llvm-svn: 115608
2010-10-05 07:13:35 +00:00
1b3aa8678e
move 32-bit shift and rotates out to their own file.
...
llvm-svn: 115607
2010-10-05 07:00:12 +00:00
89497a990e
add new file
...
llvm-svn: 115606
2010-10-05 06:52:35 +00:00
a68466c202
move sign and zero extensions out to their own file.
...
llvm-svn: 115605
2010-10-05 06:52:26 +00:00
84571a1581
move some instructions from Instr64Bit -> InstrInfo.
...
bswap32 doesn't read eflags.
llvm-svn: 115604
2010-10-05 06:47:35 +00:00
da8c94ef44
move CMOV_FR32 and friends to InstrCompiler, since they are
...
pseudo instructions.
Move POPCNT to InstrSSE since they are SSE4 instructions.
llvm-svn: 115603
2010-10-05 06:41:40 +00:00
44a5a2b569
move various pattern matching support goop out of X86Instr64Bit, to live
...
with the 32-bit stuff.
llvm-svn: 115602
2010-10-05 06:37:31 +00:00
fa9b058eef
split conditional moves and setcc's out to their own file.
...
llvm-svn: 115601
2010-10-05 06:33:16 +00:00
f9594ba4e7
move string pseudo instructions to InstrCompiler consolidate 64-bit and 32-bit together.
...
llvm-svn: 115600
2010-10-05 06:27:48 +00:00
c184a57e98
move the atomic pseudo instructions out to X86InstrCompiler.td
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llvm-svn: 115599
2010-10-05 06:22:35 +00:00
c793f8bca6
move more pseudo instructions out to X86InstrCompiler.td
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llvm-svn: 115598
2010-10-05 06:10:16 +00:00
52d3935dfe
move VMX instructions out to their own file.
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llvm-svn: 115597
2010-10-05 06:06:53 +00:00
ae33f5d93b
continue moving stuff out to X86InstrSystem.td. Move
...
control flow stuff out to X86InstrControl.td. Move
some compiler pseudo instructions and Pat<> patterns
out to X86InstrCompiler.td
llvm-svn: 115596
2010-10-05 06:04:14 +00:00
bdd77df090
Support: Add __forceinline to Compiler.h on MSVC.
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llvm-svn: 115595
2010-10-05 06:00:52 +00:00
70ac5fa42c
fix MSVC 2010 build.
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llvm-svn: 115594
2010-10-05 06:00:43 +00:00
e7f00cbb7c
Cleanup Whitespace.
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llvm-svn: 115593
2010-10-05 06:00:33 +00:00
dec85b8c64
refactor .td files a bit, moving system instructions out to X86InstrSystem.td
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llvm-svn: 115591
2010-10-05 05:32:15 +00:00
1e8b44e470
s/The ARM has/The ARM backend has/
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llvm-svn: 115584
2010-10-05 01:00:42 +00:00
f5e294027e
Update LLVMLibDeps
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llvm-svn: 115583
2010-10-05 00:35:16 +00:00
a85a4e21c9
Re-apply r115363 and r115366 now that r115525 has removed the un-needed header
...
that caused the circular dependencies on Linux.
Built OK for me on OSX and Linux (Ubuntu) with configure/make and CMake. Will
keep an eye on the bots....
llvm-svn: 115582
2010-10-05 00:34:11 +00:00
6296bbbb65
Added a testcase for the ENTER instruction.
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llvm-svn: 115580
2010-10-05 00:21:40 +00:00
8d302b2e71
Fixed the disassembler to handle two new X86
...
instruction forms. Now the ENTER instruction
disassembles correctly.
llvm-svn: 115573
2010-10-04 22:45:51 +00:00
c8d6cfd730
This DAG combine BRCOND transformation can look pass truncate of the operand:
...
// %a = ...
// %b = and i32 %a, 2
// %c = srl i32 %b, 1
// brcond i32 %c ...
//
// into
//
// %a = ...
// %b = and i32 %a, 2
// %c = setcc eq %b, 0
// brcond %c ...
Make sure it restores local variable N1, which corresponds to the condition operand if it fails to match.
This apparently breaks TCE but since that backend isn't in the tree I don't have a test for it.
llvm-svn: 115571
2010-10-04 22:41:01 +00:00
3ae4d87d6f
AVX intrinsics and builtins were also added to clang
...
llvm-svn: 115566
2010-10-04 22:07:22 +00:00
7e79556d96
Spell AltiVec correctly
...
llvm-svn: 115560
2010-10-04 21:12:06 +00:00
402e54822b
The pshufw instruction came about in MMX2 when SSE was introduced. Don't place
...
it in with the SSSE3 instructions.
Steward! Could you place this chair by the aft sun deck? I'm trying to get away
from the Astors. They are such boors!
llvm-svn: 115552
2010-10-04 20:24:01 +00:00
a68d004d88
Incorporate suggestions by Daniel Dunbar after his review. Thanks Daniel!
...
1) Changed ValidateDwarfFileNumber() to isValidDwarfFileNumber() to be better
named. Since it is just a predicate and isn't actually changing any state.
2) Added a missing return in the comments for setCurrentDwarfLoc() in
include/llvm/MC/MCContext.h for fix formatting.
3) Changed clearDwarfLocSeen() to ClearDwarfLocSeen() since it does change
state.
4) Simplified the last test in isValidDwarfFileNumber() to just a one line
boolean test of MCDwarfFiles[FileNumber] != 0 for the final return statement.
llvm-svn: 115551
2010-10-04 20:17:24 +00:00
f70898affa
ReleaseNotes: Note some changes to LLVM development infrastructure.
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llvm-svn: 115550
2010-10-04 20:11:41 +00:00
efefb206a5
ReleaseNotes: Note a header rename.
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llvm-svn: 115549
2010-10-04 20:11:39 +00:00
fd1fff8b19
Implement ELF::R_X86_64_GOTPCREL.
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llvm-svn: 115547
2010-10-04 19:51:39 +00:00
308363336b
Move isFixupKindX86PCRel.
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llvm-svn: 115545
2010-10-04 19:46:28 +00:00
Chris Lattner