forked from OSchip/llvm-project
[mips][microMIPS] Adding code size reduction pass for MicroMIPS
Author: milena.vujosevic.janicic Reviewers: sdardis The code implements size reduction pass for MicroMIPS. Load and store instructions are examined and transformed, if possible. lw32 instruction is transformed into 16-bit instruction lwsp sw32 instruction is transformed into 16-bit instruction swsp Arithmetic instrcutions are examined and transformed, if possible. addu32 instruction is transformed into 16-bit instruction addu16 subu32 instruction is transformed into 16-bit instruction subu16 Differential Revision: https://reviews.llvm.org/D15144 llvm-svn: 301540
This commit is contained in:
Zoran Jovanovic
parent
742c5fce67
commit
ffef3e3c6a
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@ -47,6 +47,7 @@ add_llvm_target(MipsCodeGen
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MipsSubtarget.cpp
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MipsTargetMachine.cpp
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MipsTargetObjectFile.cpp
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MicroMipsSizeReduction.cpp
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)
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add_subdirectory(InstPrinter)
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@ -0,0 +1,335 @@
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//=== MicroMipsSizeReduction.cpp - MicroMips size reduction pass --------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///\file
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/// This pass is used to reduce the size of instructions where applicable.
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///
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/// TODO: Implement microMIPS64 support.
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/// TODO: Implement support for reducing into lwp/swp instruction.
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//===----------------------------------------------------------------------===//
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#include "Mips.h"
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#include "MipsInstrInfo.h"
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#include "MipsSubtarget.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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#define DEBUG_TYPE "micromips-reduce-size"
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STATISTIC(NumReduced, "Number of 32-bit instructions reduced to 16-bit ones");
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namespace {
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/// Order of operands to transfer
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// TODO: Will be extended when additional optimizations are added
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enum OperandTransfer {
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OT_NA, ///< Not applicable
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OT_OperandsAll, ///< Transfer all operands
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};
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/// Reduction type
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// TODO: Will be extended when additional optimizations are added
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enum ReduceType {
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RT_OneInstr ///< Reduce one instruction into a smaller instruction
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};
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// Information about immediate field restrictions
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struct ImmField {
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ImmField() : ImmFieldOperand(-1), Shift(0), LBound(0), HBound(0) {}
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ImmField(uint8_t Shift, int16_t LBound, int16_t HBound,
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int8_t ImmFieldOperand)
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: ImmFieldOperand(ImmFieldOperand), Shift(Shift), LBound(LBound),
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HBound(HBound) {}
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int8_t ImmFieldOperand; // Immediate operand, -1 if it does not exist
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uint8_t Shift; // Shift value
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int16_t LBound; // Low bound of the immediate operand
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int16_t HBound; // High bound of the immediate operand
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};
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/// Information about operands
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// TODO: Will be extended when additional optimizations are added
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struct OpInfo {
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OpInfo(enum OperandTransfer TransferOperands)
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: TransferOperands(TransferOperands) {}
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OpInfo() : TransferOperands(OT_NA) {}
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enum OperandTransfer
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TransferOperands; ///< Operands to transfer to the new instruction
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};
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// Information about opcodes
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struct OpCodes {
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OpCodes(unsigned WideOpc, unsigned NarrowOpc)
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: WideOpc(WideOpc), NarrowOpc(NarrowOpc) {}
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unsigned WideOpc; ///< Wide opcode
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unsigned NarrowOpc; ///< Narrow opcode
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};
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/// ReduceTable - A static table with information on mapping from wide
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/// opcodes to narrow
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struct ReduceEntry {
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enum ReduceType eRType; ///< Reduction type
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bool (*ReduceFunction)(
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MachineInstr *MI,
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const ReduceEntry &Entry); ///< Pointer to reduce function
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struct OpCodes Ops; ///< All relevant OpCodes
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struct OpInfo OpInf; ///< Characteristics of operands
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struct ImmField Imm; ///< Characteristics of immediate field
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ReduceEntry(enum ReduceType RType, struct OpCodes Op,
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bool (*F)(MachineInstr *MI, const ReduceEntry &Entry),
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struct OpInfo OpInf, struct ImmField Imm)
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: eRType(RType), ReduceFunction(F), Ops(Op), OpInf(OpInf), Imm(Imm) {}
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unsigned NarrowOpc() const { return Ops.NarrowOpc; }
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unsigned WideOpc() const { return Ops.WideOpc; }
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int16_t LBound() const { return Imm.LBound; }
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int16_t HBound() const { return Imm.HBound; }
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uint8_t Shift() const { return Imm.Shift; }
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int8_t ImmField() const { return Imm.ImmFieldOperand; }
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enum OperandTransfer TransferOperands() const {
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return OpInf.TransferOperands;
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}
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enum ReduceType RType() const { return eRType; }
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// operator used by std::equal_range
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bool operator<(const unsigned int r) const { return (WideOpc() < r); }
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// operator used by std::equal_range
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friend bool operator<(const unsigned int r, const struct ReduceEntry &re) {
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return (r < re.WideOpc());
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}
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};
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class MicroMipsSizeReduce : public MachineFunctionPass {
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public:
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static char ID;
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MicroMipsSizeReduce();
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static const MipsInstrInfo *MipsII;
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const MipsSubtarget *Subtarget;
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bool runOnMachineFunction(MachineFunction &MF) override;
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llvm::StringRef getPassName() const override {
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return "microMIPS instruction size reduction pass";
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}
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private:
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/// Reduces width of instructions in the specified basic block.
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bool ReduceMBB(MachineBasicBlock &MBB);
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/// Attempts to reduce MI, returns true on success.
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bool ReduceMI(const MachineBasicBlock::instr_iterator &MII);
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// Attempts to reduce LW/SW instruction into LWSP/SWSP,
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// returns true on success.
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static bool ReduceXWtoXWSP(MachineInstr *MI, const ReduceEntry &Entry);
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// Attempts to reduce arithmetic instructions, returns true on success
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static bool ReduceArithmeticInstructions(MachineInstr *MI,
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const ReduceEntry &Entry);
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// Changes opcode of an instruction
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static bool ReplaceInstruction(MachineInstr *MI, const ReduceEntry &Entry);
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// Table with transformation rules for each instruction
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static llvm::SmallVector<ReduceEntry, 16> ReduceTable;
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};
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char MicroMipsSizeReduce::ID = 0;
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const MipsInstrInfo *MicroMipsSizeReduce::MipsII;
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// This table must be sorted by WideOpc as a main criterion and
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// ReduceType as a sub-criterion (when wide opcodes are the same)
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llvm::SmallVector<ReduceEntry, 16> MicroMipsSizeReduce::ReduceTable = {
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// ReduceType, OpCodes, ReduceFunction,
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// OpInfo(TransferOperands),
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// ImmField(Shift, LBound, HBound, ImmFieldPosition)
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{RT_OneInstr, OpCodes(Mips::ADDu, Mips::ADDU16_MM),
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ReduceArithmeticInstructions, OpInfo(OT_OperandsAll),
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ImmField(0, 0, 0, -1)},
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{RT_OneInstr, OpCodes(Mips::ADDu_MM, Mips::ADDU16_MM),
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ReduceArithmeticInstructions, OpInfo(OT_OperandsAll),
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ImmField(0, 0, 0, -1)},
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{RT_OneInstr, OpCodes(Mips::LW, Mips::LWSP_MM), ReduceXWtoXWSP,
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OpInfo(OT_OperandsAll), ImmField(2, 0, 32, 2)},
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{RT_OneInstr, OpCodes(Mips::LW_MM, Mips::LWSP_MM), ReduceXWtoXWSP,
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OpInfo(OT_OperandsAll), ImmField(2, 0, 32, 2)},
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{RT_OneInstr, OpCodes(Mips::SUBu, Mips::SUBU16_MM),
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ReduceArithmeticInstructions, OpInfo(OT_OperandsAll),
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ImmField(0, 0, 0, -1)},
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{RT_OneInstr, OpCodes(Mips::SUBu_MM, Mips::SUBU16_MM),
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ReduceArithmeticInstructions, OpInfo(OT_OperandsAll),
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ImmField(0, 0, 0, -1)},
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{RT_OneInstr, OpCodes(Mips::SW, Mips::SWSP_MM), ReduceXWtoXWSP,
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OpInfo(OT_OperandsAll), ImmField(2, 0, 32, 2)},
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{RT_OneInstr, OpCodes(Mips::SW_MM, Mips::SWSP_MM), ReduceXWtoXWSP,
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OpInfo(OT_OperandsAll), ImmField(2, 0, 32, 2)},
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};
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}
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// Returns true if the machine operand MO is register SP
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static bool IsSP(const MachineOperand &MO) {
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if (MO.isReg() && ((MO.getReg() == Mips::SP)))
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return true;
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return false;
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}
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// Returns true if the machine operand MO is register $16, $17, or $2-$7.
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static bool isMMThreeBitGPRegister(const MachineOperand &MO) {
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if (MO.isReg() && Mips::GPRMM16RegClass.contains(MO.getReg()))
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return true;
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return false;
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}
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// Returns true if the operand Op is an immediate value
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// and writes the immediate value into variable Imm
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static bool GetImm(MachineInstr *MI, unsigned Op, int64_t &Imm) {
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if (!MI->getOperand(Op).isImm())
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return false;
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Imm = MI->getOperand(Op).getImm();
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return true;
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}
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// Returns true if the variable Value has the number of least-significant zero
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// bits equal to Shift and if the shifted value is between the bounds
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static bool InRange(int64_t Value, unsigned short Shift, int LBound,
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int HBound) {
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int64_t Value2 = Value >> Shift;
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if ((Value2 << Shift) == Value && (Value2 >= LBound) && (Value2 < HBound))
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return true;
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return false;
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}
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// Returns true if immediate operand is in range
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static bool ImmInRange(MachineInstr *MI, const ReduceEntry &Entry) {
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int64_t offset;
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if (!GetImm(MI, Entry.ImmField(), offset))
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return false;
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if (!InRange(offset, Entry.Shift(), Entry.LBound(), Entry.HBound()))
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return false;
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return true;
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}
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MicroMipsSizeReduce::MicroMipsSizeReduce() : MachineFunctionPass(ID) {}
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bool MicroMipsSizeReduce::ReduceMI(
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const MachineBasicBlock::instr_iterator &MII) {
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MachineInstr *MI = &*MII;
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unsigned Opcode = MI->getOpcode();
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// Search the table.
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llvm::SmallVector<ReduceEntry, 16>::const_iterator Start =
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std::begin(ReduceTable);
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llvm::SmallVector<ReduceEntry, 16>::const_iterator End =
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std::end(ReduceTable);
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std::pair<llvm::SmallVector<ReduceEntry, 16>::const_iterator,
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llvm::SmallVector<ReduceEntry, 16>::const_iterator>
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Range = std::equal_range(Start, End, Opcode);
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if (Range.first == Range.second)
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return false;
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for (llvm::SmallVector<ReduceEntry, 16>::const_iterator Entry = Range.first;
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Entry != Range.second; ++Entry)
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if (((*Entry).ReduceFunction)(&(*MII), *Entry))
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return true;
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return false;
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}
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bool MicroMipsSizeReduce::ReduceXWtoXWSP(MachineInstr *MI,
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const ReduceEntry &Entry) {
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if (!ImmInRange(MI, Entry))
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return false;
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if (!IsSP(MI->getOperand(1)))
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return false;
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return ReplaceInstruction(MI, Entry);
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}
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bool MicroMipsSizeReduce::ReduceArithmeticInstructions(
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MachineInstr *MI, const ReduceEntry &Entry) {
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if (!isMMThreeBitGPRegister(MI->getOperand(0)) ||
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!isMMThreeBitGPRegister(MI->getOperand(1)) ||
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!isMMThreeBitGPRegister(MI->getOperand(2)))
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return false;
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return ReplaceInstruction(MI, Entry);
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}
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bool MicroMipsSizeReduce::ReduceMBB(MachineBasicBlock &MBB) {
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bool Modified = false;
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MachineBasicBlock::instr_iterator MII = MBB.instr_begin(),
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E = MBB.instr_end();
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MachineBasicBlock::instr_iterator NextMII;
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// Iterate through the instructions in the basic block
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for (; MII != E; MII = NextMII) {
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NextMII = std::next(MII);
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MachineInstr *MI = &*MII;
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// Don't reduce bundled instructions or pseudo operations
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if (MI->isBundle() || MI->isTransient())
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continue;
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// Try to reduce 32-bit instruction into 16-bit instruction
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Modified |= ReduceMI(MII);
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}
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return Modified;
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}
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bool MicroMipsSizeReduce::ReplaceInstruction(MachineInstr *MI,
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const ReduceEntry &Entry) {
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MI->setDesc(MipsII->get(Entry.NarrowOpc()));
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DEBUG(dbgs() << "Converted into 16-bit: " << *MI);
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++NumReduced;
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return true;
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}
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bool MicroMipsSizeReduce::runOnMachineFunction(MachineFunction &MF) {
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Subtarget = &static_cast<const MipsSubtarget &>(MF.getSubtarget());
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// TODO: Add support for other subtargets:
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// microMIPS32r6 and microMIPS64r6
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if (!Subtarget->inMicroMipsMode() || !Subtarget->hasMips32r2())
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return false;
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MipsII = static_cast<const MipsInstrInfo *>(Subtarget->getInstrInfo());
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bool Modified = false;
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MachineFunction::iterator I = MF.begin(), E = MF.end();
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for (; I != E; ++I)
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Modified |= ReduceMBB(*I);
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return Modified;
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}
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/// Returns an instance of the MicroMips size reduction pass.
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FunctionPass *llvm::createMicroMipsSizeReductionPass() {
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return new MicroMipsSizeReduce();
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}
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@ -32,6 +32,7 @@ namespace llvm {
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FunctionPass *createMipsHazardSchedule();
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FunctionPass *createMipsLongBranchPass(MipsTargetMachine &TM);
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FunctionPass *createMipsConstantIslandPass();
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FunctionPass *createMicroMipsSizeReductionPass();
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} // end namespace llvm;
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#endif
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@ -260,6 +260,7 @@ TargetIRAnalysis MipsTargetMachine::getTargetIRAnalysis() {
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// print out the code after the passes.
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void MipsPassConfig::addPreEmitPass() {
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MipsTargetMachine &TM = getMipsTargetMachine();
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addPass(createMicroMipsSizeReductionPass());
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// The delay slot filler pass can potientially create forbidden slot (FS)
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// hazards for MIPSR6 which the hazard schedule pass (HSP) will fix. Any
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@ -24,7 +24,7 @@
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; RUN: -check-prefixes=ALL,R2-R6,GP64
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; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
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; RUN: -check-prefixes=ALL,R2-R6,GP64
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; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -O2 | FileCheck %s \
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; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -O2 -verify-machineinstrs | FileCheck %s \
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; RUN: -check-prefixes=ALL,MMR6,MM32
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; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -O2 | FileCheck %s \
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; RUN: -check-prefixes=ALL,MMR6,MM32
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@ -117,7 +117,7 @@ entry:
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; GP64: daddu $2, $4, $5
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; MM32: addu $3, $5, $7
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; MM32: addu16 $3, $5, $7
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; MM32: sltu $[[T0:[0-9]+]], $3, $7
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; MM32: addu $[[T1:[0-9]+]], $[[T0]], $6
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; MM32: addu $2, $4, $[[T1]]
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@ -158,16 +158,16 @@ entry:
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; MM32: addu $[[T1:[0-9]+]], $7, $[[T0]]
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; MM32: sltu $[[T2:[0-9]+]], $[[T1]], $[[T0]]
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; MM32: lw $[[T3:[0-9]+]], 24($sp)
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; MM32: addu $[[T4:[0-9]+]], $[[T2]], $[[T3]]
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; MM32: addu $[[T5:[0-9]+]], $6, $[[T4]]
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; MM32: addu16 $[[T4:[0-9]+]], $[[T2]], $[[T3]]
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; MM32: addu16 $[[T5:[0-9]+]], $6, $[[T4]]
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; MM32: sltu $[[T6:[0-9]+]], $[[T5]], $[[T3]]
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; MM32: lw $[[T7:[0-9]+]], 20($sp)
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; MM32: addu $[[T8:[0-9]+]], $[[T6]], $[[T7]]
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; MM32: addu16 $[[T8:[0-9]+]], $[[T6]], $[[T7]]
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; MM32: lw $[[T9:[0-9]+]], 16($sp)
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; MM32: addu $[[T10:[0-9]+]], $5, $[[T8]]
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; MM32: addu16 $[[T10:[0-9]+]], $5, $[[T8]]
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; MM32: sltu $[[T11:[0-9]+]], $[[T10]], $[[T7]]
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; MM32: addu $[[T12:[0-9]+]], $[[T11]], $[[T9]]
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; MM32: addu $[[T13:[0-9]+]], $4, $[[T12]]
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; MM32: addu16 $[[T13:[0-9]+]], $4, $[[T12]]
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; MM32: move $4, $[[T5]]
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; MM32: move $5, $[[T1]]
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@ -289,12 +289,12 @@ define signext i128 @add_i128_4(i128 signext %a) {
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; MM32: addiu $[[T0:[0-9]+]], $7, 4
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; MM32: li16 $[[T1:[0-9]+]], 4
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; MM32: sltu $[[T1]], $[[T0]], $[[T1]]
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; MM32: addu $[[T2:[0-9]+]], $6, $[[T1]]
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; MM32: addu16 $[[T2:[0-9]+]], $6, $[[T1]]
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; MM32: li16 $[[T1]], 0
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; MM32: sltu $[[T3:[0-9]+]], $[[T2]], $[[T1]]
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; MM32: addu $[[T3]], $5, $[[T3]]
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; MM32: addu16 $[[T3]], $5, $[[T3]]
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; MM32: sltu $[[T1]], $[[T3]], $[[T1]]
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; MM32: addu $[[T1]], $4, $[[T1]]
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; MM32: addu16 $[[T1]], $4, $[[T1]]
|
||||
; MM32: move $4, $[[T2]]
|
||||
; MM32: move $5, $[[T0]]
|
||||
|
||||
|
|
@ -419,12 +419,12 @@ define signext i128 @add_i128_3(i128 signext %a) {
|
|||
; MM32: addiu $[[T0:[0-9]+]], $7, 3
|
||||
; MM32: li16 $[[T1:[0-9]+]], 3
|
||||
; MM32: sltu $[[T1]], $[[T0]], $[[T1]]
|
||||
; MM32: addu $[[T2:[0-9]+]], $6, $[[T1]]
|
||||
; MM32: addu16 $[[T2:[0-9]+]], $6, $[[T1]]
|
||||
; MM32: li16 $[[T3:[0-9]+]], 0
|
||||
; MM32: sltu $[[T4:[0-9]+]], $[[T2]], $[[T3]]
|
||||
; MM32: addu $[[T4]], $5, $[[T4]]
|
||||
; MM32: addu16 $[[T4]], $5, $[[T4]]
|
||||
; MM32: sltu $[[T5:[0-9]+]], $[[T4]], $[[T3]]
|
||||
; MM32: addu $[[T5]], $4, $[[T5]]
|
||||
; MM32: addu16 $[[T5]], $4, $[[T5]]
|
||||
; MM32: move $4, $[[T2]]
|
||||
; MM32: move $5, $[[T0]]
|
||||
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@
|
|||
; RUN: -check-prefixes=R2-R6,GP32,GP32-NOT-MM,NOT-MM
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
|
||||
; RUN: -check-prefixes=R2-R6,GP32,GP32-NOT-MM,NOT-MM
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -verify-machineinstrs | FileCheck %s \
|
||||
; RUN: -check-prefixes=GP32-MM,GP32,MM
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
|
||||
; RUN: -check-prefixes=GP32-MM,GP32,MM
|
||||
|
|
@ -100,7 +100,7 @@ define signext i64 @sub_i64(i64 signext %a, i64 signext %b) {
|
|||
entry:
|
||||
; ALL-LABEL: sub_i64:
|
||||
|
||||
; GP32: subu $3, $5, $7
|
||||
; GP32-NOT-MM subu $3, $5, $7
|
||||
; GP32: sltu $[[T0:[0-9]+]], $5, $7
|
||||
; GP32: addu $[[T1:[0-9]+]], $[[T0]], $6
|
||||
; GP32: subu $2, $4, $[[T1]]
|
||||
|
|
@ -138,13 +138,13 @@ entry:
|
|||
; GP32-MM: lw $[[T4:[0-9]+]], 24($sp)
|
||||
; GP32-MM: lw $[[T5:[0-9]+]], 28($sp)
|
||||
; GP32-MM: subu $[[T1]], $7, $[[T5]]
|
||||
; GP32-MM: subu $[[T3]], $[[T6:[0-9]+]], $[[T3]]
|
||||
; GP32-MM: subu16 $[[T3]], $[[T6:[0-9]+]], $[[T3]]
|
||||
; GP32-MM: sltu $[[T6]], $6, $[[T4]]
|
||||
; GP32-MM: addu $[[T0]], $[[T6]], $[[T0]]
|
||||
; GP32-MM: subu $[[T0]], $5, $[[T0]]
|
||||
; GP32-MM: addu16 $[[T0]], $[[T6]], $[[T0]]
|
||||
; GP32-MM: subu16 $[[T0]], $5, $[[T0]]
|
||||
; GP32-MM: sltu $[[T6]], $7, $[[T5]]
|
||||
; GP32-MM: addu $[[T6]], $[[T6]], $[[T4]]
|
||||
; GP32-MM: subu $[[T6]], $6, $[[T6]]
|
||||
; GP32-MM: subu16 $[[T6]], $6, $[[T6]]
|
||||
; GP32-MM: move $[[T2]], $[[T1]]
|
||||
|
||||
; GP64: dsubu $3, $5, $7
|
||||
|
|
|
|||
|
|
@ -0,0 +1,11 @@
|
|||
; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips -asm-show-inst -verify-machineinstrs < %s | FileCheck %s
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define i32 @function1(i32 (i32)* %f) {
|
||||
entry:
|
||||
; CHECK-LABEL: function1:
|
||||
; CHECK: SWSP_MM
|
||||
; CHECK: LWSP_MM
|
||||
%call = call i32 %f(i32 0)
|
||||
ret i32 0
|
||||
}
|
||||
Loading…
Reference in New Issue