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[AMDGPU] Don't constrain callees with inlinehint from inlining on MaxBB check 

Summary: Function bodies marked inline in an opencl source are eliminated but MaxBB check may prevent inlining them leaving undefined references.

Reviewers: rampitec, arsenm

Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, Anastasia, t-tye, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63337

llvm-svn: 363418
This commit is contained in:
Valery Pykhtin 2019-06-14 16:37:33 +00:00
parent fece7c6c83
commit ffeb01c113
2 changed files with 36 additions and 1 deletions
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2
llvm/lib/Target/AMDGPU/AMDGPUInline.cpp
View File

@ -218,7 +218,7 @@ InlineCost AMDGPUInliner::getInlineCost(CallSite CS) {
LocalParams, TTI, GetAssumptionCache, None, PSI,
RemarksEnabled ? &ORE : nullptr);
if (IC && !IC.isAlways()) {
if (IC && !IC.isAlways() && !Callee->hasFnAttribute(Attribute::InlineHint)) {
// Single BB does not increase total BB amount, thus subtract 1
size_t Size = Caller->size() + Callee->size() - 1;
if (MaxBB && Size > MaxBB)

35
llvm/test/CodeGen/AMDGPU/inline-maxbb.ll
View File

@ -31,3 +31,38 @@ define amdgpu_kernel void @caller(i32 %x) {
store volatile i32 %res, i32 addrspace(1)* undef
ret void
}
; inlinehint
define i32 @callee_hint(i32 %x) #0 {
entry:
%cc = icmp eq i32 %x, 1
br i1 %cc, label %ret_res, label %mulx
mulx:
%mul1 = mul i32 %x, %x
%mul2 = mul i32 %mul1, %x
%mul3 = mul i32 %mul1, %mul2
%mul4 = mul i32 %mul3, %mul2
%mul5 = mul i32 %mul4, %mul3
br label %ret_res
ret_res:
%r = phi i32 [ %mul5, %mulx ], [ %x, %entry ]
ret i32 %r
}
; INL-LABEL: @caller_hint
; NOINL-LABEL: @caller_hint
; INL: mul i32
; INL-NOT: call i32
; NOINL: mul i32
; NOINL-NOT: call i32
define amdgpu_kernel void @caller_hint(i32 %x) {
%res = call i32 @callee_hint(i32 %x)
store volatile i32 %res, i32 addrspace(1)* undef
ret void
}
attributes #0 = { inlinehint }