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RegAllocGreedy: Follow-up to r296722 

We can now end up in situations where we initiate LiveIntervalUnion
queries with different SubRanges against the same register unit, so the
assert() no longer holds in all cases. Just recalculate now when we know
the cache is out of date.

llvm-svn: 296928
This commit is contained in:
Matthias Braun 2017-03-03 23:27:20 +00:00
parent 65a16dd858
commit ffe40dd69e
1 changed files with 5 additions and 1 deletions
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6
llvm/lib/CodeGen/RegAllocGreedy.cpp
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@ -849,7 +849,11 @@ void RAGreedy::evictInterference(LiveInterval &VirtReg, unsigned PhysReg,
SmallVector<LiveInterval*, 8> Intfs; SmallVector<LiveInterval*, 8> Intfs;
for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units); LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
assert(Q.seenAllInterferences() && "Didn't check all interfererences."); // We usually have the interfering VRegs cached so collectInterferingVRegs()
// should be fast, we may need to recalculate if when different physregs
// overlap the same register unit so we had different SubRanges queried
// against it.
Q.collectInterferingVRegs();
ArrayRef<LiveInterval*> IVR = Q.interferingVRegs(); ArrayRef<LiveInterval*> IVR = Q.interferingVRegs();
Intfs.append(IVR.begin(), IVR.end()); Intfs.append(IVR.begin(), IVR.end());
} }