forked from OSchip/llvm-project
[X86][SSE] LowerMULH vXi8 - use SSE shifts directly.
We know these vXi16 extended cases are legal constant splat shifts. llvm-svn: 340414
This commit is contained in:
Simon Pilgrim
parent
564e65a4c0
commit
ffdfe45645
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@ -22904,7 +22904,7 @@ static SDValue LowerMULH(SDValue Op, const X86Subtarget &Subtarget,
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// With SSE41 we can use sign/zero extend, but for pre-SSE41 we unpack
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// and then ashr/lshr the upper bits down to the lower bits before multiply.
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unsigned Opcode = Op.getOpcode();
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unsigned ExShift = (ISD::MULHU == Opcode ? ISD::SRL : ISD::SRA);
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unsigned ExShift = (ISD::MULHU == Opcode ? X86ISD::VSRLI : X86ISD::VSRAI);
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unsigned ExAVX = (ISD::MULHU == Opcode ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND);
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// For 512-bit vectors, split into 256-bit vectors to allow the
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@ -22920,36 +22920,36 @@ static SDValue LowerMULH(SDValue Op, const X86Subtarget &Subtarget,
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if (VT == MVT::v32i8) {
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if (Subtarget.canExtendTo512BW()) {
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SDValue ExA = DAG.getNode(ExAVX, dl, MVT::v32i16, A);
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SDValue ExB = DAG.getNode(ExAVX, dl, MVT::v32i16, B);
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SDValue Mul = DAG.getNode(ISD::MUL, dl, MVT::v32i16, ExA, ExB);
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Mul = DAG.getNode(ISD::SRL, dl, MVT::v32i16, Mul,
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DAG.getConstant(8, dl, MVT::v32i16));
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MVT ExVT = MVT::v32i16;
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SDValue ExA = DAG.getNode(ExAVX, dl, ExVT, A);
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SDValue ExB = DAG.getNode(ExAVX, dl, ExVT, B);
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SDValue Mul = DAG.getNode(ISD::MUL, dl, ExVT, ExA, ExB);
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Mul = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ExVT, Mul, 8, DAG);
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return DAG.getNode(ISD::TRUNCATE, dl, VT, Mul);
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}
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MVT ExVT = MVT::v16i16;
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SDValue ALo = extract128BitVector(A, 0, DAG, dl);
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SDValue BLo = extract128BitVector(B, 0, DAG, dl);
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SDValue AHi = extract128BitVector(A, NumElems / 2, DAG, dl);
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SDValue BHi = extract128BitVector(B, NumElems / 2, DAG, dl);
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ALo = DAG.getNode(ExAVX, dl, MVT::v16i16, ALo);
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BLo = DAG.getNode(ExAVX, dl, MVT::v16i16, BLo);
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AHi = DAG.getNode(ExAVX, dl, MVT::v16i16, AHi);
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BHi = DAG.getNode(ExAVX, dl, MVT::v16i16, BHi);
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Lo = DAG.getNode(ISD::SRL, dl, MVT::v16i16,
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DAG.getNode(ISD::MUL, dl, MVT::v16i16, ALo, BLo),
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DAG.getConstant(8, dl, MVT::v16i16));
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Hi = DAG.getNode(ISD::SRL, dl, MVT::v16i16,
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DAG.getNode(ISD::MUL, dl, MVT::v16i16, AHi, BHi),
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DAG.getConstant(8, dl, MVT::v16i16));
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// The ymm variant of PACKUS treats the 128-bit lanes separately, so before
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// using PACKUS we need to permute the inputs to the correct lo/hi xmm lane.
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ALo = DAG.getNode(ExAVX, dl, ExVT, ALo);
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BLo = DAG.getNode(ExAVX, dl, ExVT, BLo);
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AHi = DAG.getNode(ExAVX, dl, ExVT, AHi);
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BHi = DAG.getNode(ExAVX, dl, ExVT, BHi);
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Lo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo);
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Hi = DAG.getNode(ISD::MUL, dl, ExVT, AHi, BHi);
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Lo = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ExVT, Lo, 8, DAG);
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Hi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ExVT, Hi, 8, DAG);
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// The ymm variant of PACKUS treats the 128-bit lanes separately, so
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// before using PACKUS we need to permute the inputs to the correct lo/hi
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// xmm lane.
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const int LoMask[] = {0, 1, 2, 3, 4, 5, 6, 7,
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16, 17, 18, 19, 20, 21, 22, 23};
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const int HiMask[] = {8, 9, 10, 11, 12, 13, 14, 15,
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24, 25, 26, 27, 28, 29, 30, 31};
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return DAG.getNode(X86ISD::PACKUS, dl, VT,
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DAG.getVectorShuffle(MVT::v16i16, dl, Lo, Hi, LoMask),
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DAG.getVectorShuffle(MVT::v16i16, dl, Lo, Hi, HiMask));
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DAG.getVectorShuffle(ExVT, dl, Lo, Hi, LoMask),
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DAG.getVectorShuffle(ExVT, dl, Lo, Hi, HiMask));
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}
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assert(VT == MVT::v16i8 && "Unexpected VT");
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@ -22957,8 +22957,8 @@ static SDValue LowerMULH(SDValue Op, const X86Subtarget &Subtarget,
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SDValue ExA = DAG.getNode(ExAVX, dl, MVT::v16i16, A);
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SDValue ExB = DAG.getNode(ExAVX, dl, MVT::v16i16, B);
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SDValue Mul = DAG.getNode(ISD::MUL, dl, MVT::v16i16, ExA, ExB);
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Mul = DAG.getNode(ISD::SRL, dl, MVT::v16i16, Mul,
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DAG.getConstant(8, dl, MVT::v16i16));
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Mul =
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getTargetVShiftByConstNode(X86ISD::VSRLI, dl, MVT::v16i16, Mul, 8, DAG);
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// If we have BWI we can use truncate instruction.
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if (Subtarget.hasBWI())
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return DAG.getNode(ISD::TRUNCATE, dl, VT, Mul);
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@ -22985,8 +22985,8 @@ static SDValue LowerMULH(SDValue Op, const X86Subtarget &Subtarget,
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BLo = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
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ALo = DAG.getBitcast(ExVT, ALo);
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BLo = DAG.getBitcast(ExVT, BLo);
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ALo = DAG.getNode(ExShift, dl, ExVT, ALo, DAG.getConstant(8, dl, ExVT));
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BLo = DAG.getNode(ExShift, dl, ExVT, BLo, DAG.getConstant(8, dl, ExVT));
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ALo = getTargetVShiftByConstNode(ExShift, dl, ExVT, ALo, 8, DAG);
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BLo = getTargetVShiftByConstNode(ExShift, dl, ExVT, BLo, 8, DAG);
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}
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// Extract the hi parts and zero/sign extend to i16.
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@ -23005,16 +23005,16 @@ static SDValue LowerMULH(SDValue Op, const X86Subtarget &Subtarget,
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BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
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AHi = DAG.getBitcast(ExVT, AHi);
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BHi = DAG.getBitcast(ExVT, BHi);
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AHi = DAG.getNode(ExShift, dl, ExVT, AHi, DAG.getConstant(8, dl, ExVT));
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BHi = DAG.getNode(ExShift, dl, ExVT, BHi, DAG.getConstant(8, dl, ExVT));
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AHi = getTargetVShiftByConstNode(ExShift, dl, ExVT, AHi, 8, DAG);
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BHi = getTargetVShiftByConstNode(ExShift, dl, ExVT, BHi, 8, DAG);
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}
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// Multiply, lshr the upper 8bits to the lower 8bits of the lo/hi results and
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// pack back to v16i8.
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SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo);
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SDValue RHi = DAG.getNode(ISD::MUL, dl, ExVT, AHi, BHi);
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RLo = DAG.getNode(ISD::SRL, dl, ExVT, RLo, DAG.getConstant(8, dl, ExVT));
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RHi = DAG.getNode(ISD::SRL, dl, ExVT, RHi, DAG.getConstant(8, dl, ExVT));
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RLo = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ExVT, RLo, 8, DAG);
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RHi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ExVT, RHi, 8, DAG);
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return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
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}
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@ -3350,35 +3350,12 @@ define <16 x i8> @pr38658(<16 x i8> %x) {
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; SSE41-LABEL: pr38658:
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; SSE41: # %bb.0:
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; SSE41-NEXT: movdqa %xmm0, %xmm1
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; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [8,8,8,8,8,8,8,8]
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; SSE41-NEXT: movdqa %xmm0, %xmm2
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; SSE41-NEXT: psllw $12, %xmm2
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; SSE41-NEXT: psllw $4, %xmm0
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; SSE41-NEXT: por %xmm2, %xmm0
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; SSE41-NEXT: movdqa %xmm0, %xmm2
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; SSE41-NEXT: paddw %xmm0, %xmm2
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; SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm1[2,3,0,1]
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; SSE41-NEXT: pmovsxbw %xmm3, %xmm3
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; SSE41-NEXT: pmullw {{.*}}(%rip), %xmm3
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; SSE41-NEXT: movdqa %xmm3, %xmm4
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; SSE41-NEXT: psrlw $8, %xmm4
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; SSE41-NEXT: pblendvb %xmm0, %xmm4, %xmm3
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; SSE41-NEXT: movdqa %xmm3, %xmm4
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; SSE41-NEXT: psrlw $4, %xmm4
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; SSE41-NEXT: movdqa %xmm2, %xmm0
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; SSE41-NEXT: pblendvb %xmm0, %xmm4, %xmm3
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; SSE41-NEXT: movdqa %xmm3, %xmm4
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; SSE41-NEXT: psrlw $2, %xmm4
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; SSE41-NEXT: paddw %xmm2, %xmm2
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; SSE41-NEXT: movdqa %xmm2, %xmm0
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; SSE41-NEXT: pblendvb %xmm0, %xmm4, %xmm3
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; SSE41-NEXT: movdqa %xmm3, %xmm4
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; SSE41-NEXT: psrlw $1, %xmm4
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; SSE41-NEXT: paddw %xmm2, %xmm2
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; SSE41-NEXT: movdqa %xmm2, %xmm0
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; SSE41-NEXT: pblendvb %xmm0, %xmm4, %xmm3
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; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
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; SSE41-NEXT: pmovsxbw %xmm0, %xmm2
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; SSE41-NEXT: pmullw {{.*}}(%rip), %xmm2
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; SSE41-NEXT: psrlw $8, %xmm2
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; SSE41-NEXT: pxor %xmm0, %xmm0
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; SSE41-NEXT: packuswb %xmm3, %xmm0
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; SSE41-NEXT: packuswb %xmm2, %xmm0
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; SSE41-NEXT: paddb %xmm1, %xmm0
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; SSE41-NEXT: movdqa %xmm0, %xmm1
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; SSE41-NEXT: punpckhbw {{.*#+}} xmm1 = xmm1[8],xmm0[8],xmm1[9],xmm0[9],xmm1[10],xmm0[10],xmm1[11],xmm0[11],xmm1[12],xmm0[12],xmm1[13],xmm0[13],xmm1[14],xmm0[14],xmm1[15],xmm0[15]
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@ -3402,24 +3379,10 @@ define <16 x i8> @pr38658(<16 x i8> %x) {
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;
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; AVX1-LABEL: pr38658:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [8,8,8,8,8,8,8,8]
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; AVX1-NEXT: vpsllw $12, %xmm1, %xmm2
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; AVX1-NEXT: vpsllw $4, %xmm1, %xmm1
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; AVX1-NEXT: vpor %xmm2, %xmm1, %xmm1
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; AVX1-NEXT: vpaddw %xmm1, %xmm1, %xmm2
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; AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[2,3,0,1]
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; AVX1-NEXT: vpmovsxbw %xmm3, %xmm3
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; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm3, %xmm3
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; AVX1-NEXT: vpsrlw $8, %xmm3, %xmm4
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; AVX1-NEXT: vpblendvb %xmm1, %xmm4, %xmm3, %xmm1
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; AVX1-NEXT: vpsrlw $4, %xmm1, %xmm3
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; AVX1-NEXT: vpblendvb %xmm2, %xmm3, %xmm1, %xmm1
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; AVX1-NEXT: vpsrlw $2, %xmm1, %xmm3
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; AVX1-NEXT: vpaddw %xmm2, %xmm2, %xmm2
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; AVX1-NEXT: vpblendvb %xmm2, %xmm3, %xmm1, %xmm1
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; AVX1-NEXT: vpsrlw $1, %xmm1, %xmm3
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; AVX1-NEXT: vpaddw %xmm2, %xmm2, %xmm2
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; AVX1-NEXT: vpblendvb %xmm2, %xmm3, %xmm1, %xmm1
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; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
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; AVX1-NEXT: vpmovsxbw %xmm1, %xmm1
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; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm1, %xmm1
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; AVX1-NEXT: vpsrlw $8, %xmm1, %xmm1
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; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
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; AVX1-NEXT: vpackuswb %xmm1, %xmm2, %xmm1
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; AVX1-NEXT: vpaddb %xmm0, %xmm1, %xmm0
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@ -847,117 +847,51 @@ define <16 x i8> @combine_vec_udiv_nonuniform4(<16 x i8> %x) {
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;
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; SSE41-LABEL: combine_vec_udiv_nonuniform4:
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; SSE41: # %bb.0:
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; SSE41-NEXT: movdqa %xmm0, %xmm8
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; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [8,8,8,8,8,8,8,8]
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; SSE41-NEXT: movdqa %xmm2, %xmm0
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; SSE41-NEXT: psllw $12, %xmm0
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; SSE41-NEXT: psllw $4, %xmm2
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; SSE41-NEXT: por %xmm0, %xmm2
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; SSE41-NEXT: movdqa %xmm0, %xmm1
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; SSE41-NEXT: movl $171, %eax
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; SSE41-NEXT: movd %eax, %xmm7
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; SSE41-NEXT: pmovzxbw {{.*#+}} xmm6 = xmm8[0],zero,xmm8[1],zero,xmm8[2],zero,xmm8[3],zero,xmm8[4],zero,xmm8[5],zero,xmm8[6],zero,xmm8[7],zero
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; SSE41-NEXT: pmullw %xmm7, %xmm6
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; SSE41-NEXT: movdqa %xmm6, %xmm3
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; SSE41-NEXT: psrlw $8, %xmm3
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; SSE41-NEXT: movdqa %xmm2, %xmm0
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; SSE41-NEXT: pblendvb %xmm0, %xmm3, %xmm6
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; SSE41-NEXT: movdqa %xmm6, %xmm4
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; SSE41-NEXT: psrlw $4, %xmm4
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; SSE41-NEXT: movdqa %xmm2, %xmm3
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; SSE41-NEXT: paddw %xmm2, %xmm3
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; SSE41-NEXT: movdqa %xmm3, %xmm0
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; SSE41-NEXT: pblendvb %xmm0, %xmm4, %xmm6
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; SSE41-NEXT: movdqa %xmm6, %xmm5
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; SSE41-NEXT: psrlw $2, %xmm5
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; SSE41-NEXT: movdqa %xmm3, %xmm4
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; SSE41-NEXT: paddw %xmm3, %xmm4
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; SSE41-NEXT: movdqa %xmm4, %xmm0
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; SSE41-NEXT: pblendvb %xmm0, %xmm5, %xmm6
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; SSE41-NEXT: movdqa %xmm6, %xmm1
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; SSE41-NEXT: psrlw $1, %xmm1
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; SSE41-NEXT: movdqa %xmm4, %xmm5
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; SSE41-NEXT: paddw %xmm4, %xmm5
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; SSE41-NEXT: movdqa %xmm5, %xmm0
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; SSE41-NEXT: pblendvb %xmm0, %xmm1, %xmm6
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; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm8[2,3,0,1]
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; SSE41-NEXT: pmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
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; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm7[2,3,0,1]
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; SSE41-NEXT: pmovzxbw {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
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; SSE41-NEXT: pmullw %xmm0, %xmm1
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; SSE41-NEXT: movdqa %xmm1, %xmm7
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; SSE41-NEXT: psrlw $8, %xmm7
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; SSE41-NEXT: movdqa %xmm2, %xmm0
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; SSE41-NEXT: pblendvb %xmm0, %xmm7, %xmm1
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; SSE41-NEXT: movdqa %xmm1, %xmm2
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; SSE41-NEXT: psrlw $4, %xmm2
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; SSE41-NEXT: movdqa %xmm3, %xmm0
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; SSE41-NEXT: pblendvb %xmm0, %xmm2, %xmm1
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; SSE41-NEXT: movdqa %xmm1, %xmm2
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; SSE41-NEXT: psrlw $2, %xmm2
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; SSE41-NEXT: movdqa %xmm4, %xmm0
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; SSE41-NEXT: pblendvb %xmm0, %xmm2, %xmm1
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; SSE41-NEXT: movdqa %xmm1, %xmm2
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; SSE41-NEXT: psrlw $1, %xmm2
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; SSE41-NEXT: movdqa %xmm5, %xmm0
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; SSE41-NEXT: pblendvb %xmm0, %xmm2, %xmm1
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; SSE41-NEXT: packuswb %xmm1, %xmm6
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; SSE41-NEXT: pxor %xmm0, %xmm0
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; SSE41-NEXT: pxor %xmm1, %xmm1
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; SSE41-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm6[0],xmm1[1],xmm6[1],xmm1[2],xmm6[2],xmm1[3],xmm6[3],xmm1[4],xmm6[4],xmm1[5],xmm6[5],xmm1[6],xmm6[6],xmm1[7],xmm6[7]
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; SSE41-NEXT: pmovzxbw {{.*#+}} xmm2 = xmm6[0],zero,xmm6[1],zero,xmm6[2],zero,xmm6[3],zero,xmm6[4],zero,xmm6[5],zero,xmm6[6],zero,xmm6[7],zero
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; SSE41-NEXT: psllw $1, %xmm2
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; SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0],xmm1[1,2,3,4,5,6,7]
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; SSE41-NEXT: movd %eax, %xmm0
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; SSE41-NEXT: pmovzxbw {{.*#+}} xmm2 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
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; SSE41-NEXT: pmullw %xmm0, %xmm2
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; SSE41-NEXT: psrlw $8, %xmm2
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; SSE41-NEXT: punpckhbw {{.*#+}} xmm6 = xmm6[8],xmm0[8],xmm6[9],xmm0[9],xmm6[10],xmm0[10],xmm6[11],xmm0[11],xmm6[12],xmm0[12],xmm6[13],xmm0[13],xmm6[14],xmm0[14],xmm6[15],xmm0[15]
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; SSE41-NEXT: packuswb %xmm6, %xmm2
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; SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm1[2,3,0,1]
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; SSE41-NEXT: pmovzxbw {{.*#+}} xmm3 = xmm3[0],zero,xmm3[1],zero,xmm3[2],zero,xmm3[3],zero,xmm3[4],zero,xmm3[5],zero,xmm3[6],zero,xmm3[7],zero
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; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
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; SSE41-NEXT: pmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
|
||||
; SSE41-NEXT: pmullw %xmm3, %xmm0
|
||||
; SSE41-NEXT: psrlw $8, %xmm0
|
||||
; SSE41-NEXT: movdqa %xmm2, %xmm3
|
||||
; SSE41-NEXT: packuswb %xmm0, %xmm3
|
||||
; SSE41-NEXT: pmovzxbw {{.*#+}} xmm3 = xmm3[0],zero,xmm3[1],zero,xmm3[2],zero,xmm3[3],zero,xmm3[4],zero,xmm3[5],zero,xmm3[6],zero,xmm3[7],zero
|
||||
; SSE41-NEXT: psllw $1, %xmm3
|
||||
; SSE41-NEXT: psllw $8, %xmm2
|
||||
; SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm3[0],xmm2[1,2,3,4,5,6,7]
|
||||
; SSE41-NEXT: psrlw $8, %xmm2
|
||||
; SSE41-NEXT: packuswb %xmm0, %xmm2
|
||||
; SSE41-NEXT: movaps {{.*#+}} xmm0 = [0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
|
||||
; SSE41-NEXT: pblendvb %xmm0, %xmm8, %xmm2
|
||||
; SSE41-NEXT: pblendvb %xmm0, %xmm1, %xmm2
|
||||
; SSE41-NEXT: movdqa %xmm2, %xmm0
|
||||
; SSE41-NEXT: retq
|
||||
;
|
||||
; AVX1-LABEL: combine_vec_udiv_nonuniform4:
|
||||
; AVX1: # %bb.0:
|
||||
; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [8,8,8,8,8,8,8,8]
|
||||
; AVX1-NEXT: vpsllw $12, %xmm1, %xmm2
|
||||
; AVX1-NEXT: vpsllw $4, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vpor %xmm2, %xmm1, %xmm1
|
||||
; AVX1-NEXT: movl $171, %eax
|
||||
; AVX1-NEXT: vmovd %eax, %xmm2
|
||||
; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm3 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
|
||||
; AVX1-NEXT: vpmullw %xmm2, %xmm3, %xmm3
|
||||
; AVX1-NEXT: vpsrlw $8, %xmm3, %xmm4
|
||||
; AVX1-NEXT: vpblendvb %xmm1, %xmm4, %xmm3, %xmm3
|
||||
; AVX1-NEXT: vpsrlw $4, %xmm3, %xmm4
|
||||
; AVX1-NEXT: vpaddw %xmm1, %xmm1, %xmm5
|
||||
; AVX1-NEXT: vpblendvb %xmm5, %xmm4, %xmm3, %xmm3
|
||||
; AVX1-NEXT: vpsrlw $2, %xmm3, %xmm4
|
||||
; AVX1-NEXT: vpaddw %xmm5, %xmm5, %xmm6
|
||||
; AVX1-NEXT: vpblendvb %xmm6, %xmm4, %xmm3, %xmm3
|
||||
; AVX1-NEXT: vpsrlw $1, %xmm3, %xmm4
|
||||
; AVX1-NEXT: vpaddw %xmm6, %xmm6, %xmm7
|
||||
; AVX1-NEXT: vpblendvb %xmm7, %xmm4, %xmm3, %xmm3
|
||||
; AVX1-NEXT: vpshufd {{.*#+}} xmm4 = xmm0[2,3,0,1]
|
||||
; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm4 = xmm4[0],zero,xmm4[1],zero,xmm4[2],zero,xmm4[3],zero,xmm4[4],zero,xmm4[5],zero,xmm4[6],zero,xmm4[7],zero
|
||||
; AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[2,3,0,1]
|
||||
; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm2 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero,xmm2[4],zero,xmm2[5],zero,xmm2[6],zero,xmm2[7],zero
|
||||
; AVX1-NEXT: vpmullw %xmm2, %xmm4, %xmm2
|
||||
; AVX1-NEXT: vpsrlw $8, %xmm2, %xmm4
|
||||
; AVX1-NEXT: vpblendvb %xmm1, %xmm4, %xmm2, %xmm1
|
||||
; AVX1-NEXT: vpsrlw $4, %xmm1, %xmm2
|
||||
; AVX1-NEXT: vpblendvb %xmm5, %xmm2, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vpsrlw $2, %xmm1, %xmm2
|
||||
; AVX1-NEXT: vpblendvb %xmm6, %xmm2, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vpsrlw $1, %xmm1, %xmm2
|
||||
; AVX1-NEXT: vpblendvb %xmm7, %xmm2, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vpackuswb %xmm1, %xmm3, %xmm1
|
||||
; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm3 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3],xmm2[4],xmm1[4],xmm2[5],xmm1[5],xmm2[6],xmm1[6],xmm2[7],xmm1[7]
|
||||
; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm4 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
|
||||
; AVX1-NEXT: vpsllw $1, %xmm4, %xmm4
|
||||
; AVX1-NEXT: vpblendw {{.*#+}} xmm3 = xmm4[0],xmm3[1,2,3,4,5,6,7]
|
||||
; AVX1-NEXT: vpsrlw $8, %xmm3, %xmm3
|
||||
; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm1 = xmm1[8],xmm2[8],xmm1[9],xmm2[9],xmm1[10],xmm2[10],xmm1[11],xmm2[11],xmm1[12],xmm2[12],xmm1[13],xmm2[13],xmm1[14],xmm2[14],xmm1[15],xmm2[15]
|
||||
; AVX1-NEXT: vpackuswb %xmm1, %xmm3, %xmm1
|
||||
; AVX1-NEXT: vmovd %eax, %xmm1
|
||||
; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm2 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
|
||||
; AVX1-NEXT: vpmullw %xmm1, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vpsrlw $8, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[2,3,0,1]
|
||||
; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm3 = xmm3[0],zero,xmm3[1],zero,xmm3[2],zero,xmm3[3],zero,xmm3[4],zero,xmm3[5],zero,xmm3[6],zero,xmm3[7],zero
|
||||
; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
|
||||
; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
|
||||
; AVX1-NEXT: vpmullw %xmm1, %xmm3, %xmm1
|
||||
; AVX1-NEXT: vpsrlw $8, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vpackuswb %xmm1, %xmm2, %xmm3
|
||||
; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm3 = xmm3[0],zero,xmm3[1],zero,xmm3[2],zero,xmm3[3],zero,xmm3[4],zero,xmm3[5],zero,xmm3[6],zero,xmm3[7],zero
|
||||
; AVX1-NEXT: vpsllw $1, %xmm3, %xmm3
|
||||
; AVX1-NEXT: vpsllw $8, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm3[0],xmm2[1,2,3,4,5,6,7]
|
||||
; AVX1-NEXT: vpsrlw $8, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vpackuswb %xmm1, %xmm2, %xmm1
|
||||
; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
|
||||
; AVX1-NEXT: vpblendvb %xmm2, %xmm0, %xmm1, %xmm0
|
||||
; AVX1-NEXT: retq
|
||||
|
|
|
|||
Loading…
Reference in New Issue