forked from OSchip/llvm-project
[X86] Add NoAVX predicates to the patterns for the legacy encoded PCLMUL and AES instructions.
Previously we were just relying on pattern order to define precedence. Which works, but isn't the best way. llvm-svn: 313471
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@ -839,18 +839,18 @@ class AVX512<bits<8> o, Format F, dag outs, dag ins, string asm,
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class AES8I<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag>pattern, InstrItinClass itin = IIC_AES>
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: I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
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Requires<[HasAES]>;
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Requires<[NoAVX, HasAES]>;
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class AESAI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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: Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
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Requires<[HasAES]>;
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Requires<[NoAVX, HasAES]>;
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// PCLMUL Instruction Templates
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class PCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag>pattern, InstrItinClass itin = NoItinerary>
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: Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
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Requires<[HasPCLMUL]>;
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Requires<[NoAVX, HasPCLMUL]>;
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class AVXPCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag>pattern, InstrItinClass itin = NoItinerary>
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@ -801,6 +801,7 @@ def UseSSE41 : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">;
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def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
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def UseSSE42 : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">;
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def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
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def NoAVX : Predicate<"!Subtarget->hasAVX()">;
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def HasAVX : Predicate<"Subtarget->hasAVX()">;
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def HasAVX2 : Predicate<"Subtarget->hasAVX2()">;
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def HasAVX1Only : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX2()">;
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