forked from OSchip/llvm-project
AMDGPU/GlobalISel: Define instruction mapping for G_SELECT
Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D49737 llvm-svn: 341271
This commit is contained in:
Tom Stellard
parent
61ddb7df82
commit
ffc6bd6f3d
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@ -170,6 +170,42 @@ AMDGPURegisterBankInfo::getInstrAlternativeMappings(
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return AltMappings;
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}
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case TargetOpcode::G_SELECT: {
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unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
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const InstructionMapping &SSMapping = getInstructionMapping(1, 1,
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getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
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AMDGPU::getValueMapping(AMDGPU::SCCRegBankID, 1),
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AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
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AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size)}),
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4); // Num Operands
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AltMappings.push_back(&SSMapping);
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const InstructionMapping &SVMapping = getInstructionMapping(2, 1,
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getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),
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AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 1),
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AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
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AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size)}),
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4); // Num Operands
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AltMappings.push_back(&SVMapping);
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const InstructionMapping &VSMapping = getInstructionMapping(2, 1,
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getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),
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AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 1),
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AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),
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AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size)}),
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4); // Num Operands
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AltMappings.push_back(&VSMapping);
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const InstructionMapping &VVMapping = getInstructionMapping(2, 1,
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getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),
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AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 1),
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AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),
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AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size)}),
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4); // Num Operands
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AltMappings.push_back(&VVMapping);
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return AltMappings;
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}
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default:
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break;
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}
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@ -542,6 +578,24 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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}
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break;
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}
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case AMDGPU::G_SELECT: {
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unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
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unsigned Op1Bank = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI,
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AMDGPU::SGPRRegBankID);
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unsigned Op2Bank = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI);
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unsigned Op3Bank = getRegBankID(MI.getOperand(3).getReg(), MRI, *TRI);
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bool SGPRSrcs = Op1Bank == AMDGPU::SCCRegBankID &&
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Op2Bank == AMDGPU::SGPRRegBankID &&
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Op3Bank == AMDGPU::SGPRRegBankID;
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unsigned Bank = SGPRSrcs ? AMDGPU::SGPRRegBankID : AMDGPU::VGPRRegBankID;
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Op1Bank = SGPRSrcs ? AMDGPU::SCCRegBankID : AMDGPU::SGPRRegBankID;
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OpdsMapping[0] = AMDGPU::getValueMapping(Bank, Size);
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OpdsMapping[1] = AMDGPU::getValueMapping(Op1Bank, 1);
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OpdsMapping[2] = AMDGPU::getValueMapping(Bank, Size);
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OpdsMapping[3] = AMDGPU::getValueMapping(Bank, Size);
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break;
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}
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case AMDGPU::G_LOAD:
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return getInstrMappingForLoad(MI);
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}
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@ -0,0 +1,214 @@
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# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -global-isel %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck --check-prefixes=GCN,FAST %s
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# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -global-isel %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck --check-prefixes=GCN,GREEDY %s
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# REQUIRES: global-isel
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--- |
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define void @select_sss() { ret void }
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define void @select_ssv() { ret void }
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define void @select_svs() { ret void }
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define void @select_svv() { ret void }
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define void @select_vss() { ret void }
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define void @select_vsv() { ret void }
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define void @select_vvs() { ret void }
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define void @select_vvv() { ret void }
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...
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---
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name: select_sss
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legalized: true
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# GCN-LABEL: name: select_sss
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# GCN: [[SGPR0:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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# GCN: [[SGPR1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
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# GCN: [[SGPR2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
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# GCN: [[SGPR3:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
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# GCN: [[SCC:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[SGPR0]](s32), [[SGPR1]]
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# GCN: {{%[0-9]+}}:sgpr(s32) = G_SELECT [[SCC]](s1), [[SGPR2]], [[SGPR3]]
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3
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%0:_(s32) = COPY $sgpr0
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%1:_(s32) = COPY $sgpr1
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%2:_(s32) = COPY $sgpr2
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%3:_(s32) = COPY $sgpr3
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%4:_(s1) = G_ICMP intpred(ne), %0, %1
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%5:_(s32) = G_SELECT %4, %2, %3
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...
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---
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name: select_ssv
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legalized: true
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# GCN-LABEL: name: select_ssv
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# GCN: [[SGPR0:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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# GCN: [[SGPR1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
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# GCN: [[SGPR2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
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# GCN: [[VGPR0:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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# GCN: [[SCC:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[SGPR0]](s32), [[SGPR1]]
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# GCN: [[SCC_S:%[0-9]+]]:sgpr(s1) = COPY [[SCC]]
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# FAST: [[SGPR2_V:%[0-9]+]]:vgpr(s32) = COPY [[SGPR2]]
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# FAST: {{%[0-9]+}}:vgpr(s32) = G_SELECT [[SCC_S]](s1), [[SGPR2_V]], [[VGPR0]]
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# GREEDY: {{%[0-9]+}}:vgpr(s32) = G_SELECT [[SCC_S]](s1), [[SGPR2]], [[VGPR0]]
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0
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%0:_(s32) = COPY $sgpr0
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%1:_(s32) = COPY $sgpr1
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%2:_(s32) = COPY $sgpr2
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%3:_(s32) = COPY $vgpr0
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%4:_(s1) = G_ICMP intpred(ne), %0, %1
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%5:_(s32) = G_SELECT %4, %2, %3
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...
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---
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name: select_svs
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legalized: true
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# GCN-LABEL: name: select_svs
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# GCN: [[SGPR0:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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# GCN: [[SGPR1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
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# GCN: [[SGPR2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
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# GCN: [[VGPR0:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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# GCN: [[SCC:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[SGPR0]](s32), [[SGPR1]]
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# GCN: [[SCC_S:%[0-9]+]]:sgpr(s1) = COPY [[SCC]]
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# FAST: [[SGPR2_V:%[0-9]+]]:vgpr(s32) = COPY [[SGPR2]]
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# FAST: {{%[0-9]+}}:vgpr(s32) = G_SELECT [[SCC_S]](s1), [[VGPR0]], [[SGPR2_V]]
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# GREEDY: {{%[0-9]+}}:vgpr(s32) = G_SELECT [[SCC_S]](s1), [[VGPR0]], [[SGPR2]]
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0
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%0:_(s32) = COPY $sgpr0
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%1:_(s32) = COPY $sgpr1
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%2:_(s32) = COPY $sgpr2
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%3:_(s32) = COPY $vgpr0
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%4:_(s1) = G_ICMP intpred(ne), %0, %1
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%5:_(s32) = G_SELECT %4, %3, %2
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...
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---
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name: select_svv
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legalized: true
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# GCN-LABEL: name: select_svv
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# GCN: [[SGPR0:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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# GCN: [[SGPR1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
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# GCN: [[VGPR0:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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# GCN: [[VGPR1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
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# GCN: [[SCC:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[SGPR0]](s32), [[SGPR1]]
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# GCN: [[SCC_S:%[0-9]+]]:sgpr(s1) = COPY [[SCC]]
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# GCN: {{%[0-9]+}}:vgpr(s32) = G_SELECT [[SCC_S]](s1), [[VGPR0]], [[VGPR1]]
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1
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%0:_(s32) = COPY $sgpr0
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%1:_(s32) = COPY $sgpr1
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%2:_(s32) = COPY $vgpr0
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%3:_(s32) = COPY $vgpr1
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%4:_(s1) = G_ICMP intpred(ne), %0, %1
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%5:_(s32) = G_SELECT %4, %2, %3
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...
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---
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name: select_vss
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legalized: true
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# GCN-LABEL: name: select_vss
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# GCN: [[SGPR0:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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# GCN: [[SGPR1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
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# GCN: [[VGPR0:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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# GCN: [[VGPR1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
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# GCN: [[VCC:%[0-9]+]]:sgpr(s1) = G_ICMP intpred(ne), [[VGPR0]](s32), [[VGPR1]]
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# FAST: [[SGPR0_V:%[0-9]+]]:vgpr(s32) = COPY [[SGPR0]]
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# GCN: [[SGPR1_V:%[0-9]+]]:vgpr(s32) = COPY [[SGPR1]]
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# FAST: {{%[0-9]+}}:vgpr(s32) = G_SELECT [[VCC]](s1), [[SGPR0_V]], [[SGPR1_V]]
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# GREDY: {{%[0-9]+}}:vgpr(s32) = G_SELECT [[VCC]](s1), [[SGPR0]], [[SGPR1_V]]
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1
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%0:_(s32) = COPY $sgpr0
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%1:_(s32) = COPY $sgpr1
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%2:_(s32) = COPY $vgpr0
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%3:_(s32) = COPY $vgpr1
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%4:_(s1) = G_ICMP intpred(ne), %2, %3
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%5:_(s32) = G_SELECT %4, %0, %1
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...
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---
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name: select_vsv
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legalized: true
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# GCN-LABEL: name: select_vsv
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# GCN: [[SGPR0:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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# GCN: [[VGPR0:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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# GCN: [[VGPR1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
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# GCN: [[VGPR2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
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# GCN: [[VCC:%[0-9]+]]:sgpr(s1) = G_ICMP intpred(ne), [[VGPR0]](s32), [[VGPR1]]
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# FAST: [[SGPR0_V:%[0-9]+]]:vgpr(s32) = COPY [[SGPR0]]
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# FAST: {{%[0-9]+}}:vgpr(s32) = G_SELECT [[VCC]](s1), [[SGPR0_V]], [[VGPR2]]
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# GREEDY: {{%[0-9]+}}:vgpr(s32) = G_SELECT [[VCC]](s1), [[SGPR0]], [[VGPR2]]
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body: |
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bb.0:
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liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2
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%0:_(s32) = COPY $sgpr0
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%1:_(s32) = COPY $vgpr0
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%2:_(s32) = COPY $vgpr1
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%3:_(s32) = COPY $vgpr2
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%4:_(s1) = G_ICMP intpred(ne), %1, %2
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%5:_(s32) = G_SELECT %4, %0, %3
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...
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---
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name: select_vvs
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legalized: true
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# GCN-LABEL: name: select_vvs
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# GCN: [[SGPR0:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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# GCN: [[VGPR0:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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# GCN: [[VGPR1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
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# GCN: [[VGPR2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
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# GCN: [[VCC:%[0-9]+]]:sgpr(s1) = G_ICMP intpred(ne), [[VGPR0]](s32), [[VGPR1]]
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# FAST: [[SGPR0_V:%[0-9]+]]:vgpr(s32) = COPY [[SGPR0]]
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# FAST: {{%[0-9]+}}:vgpr(s32) = G_SELECT [[VCC]](s1), [[VGPR2]], [[SGPR0_V]]
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# GREEDY: {{%[0-9]+}}:vgpr(s32) = G_SELECT [[VCC]](s1), [[VGPR2]], [[SGPR0]]
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body: |
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bb.0:
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liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2
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%0:_(s32) = COPY $sgpr0
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%1:_(s32) = COPY $vgpr0
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%2:_(s32) = COPY $vgpr1
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%3:_(s32) = COPY $vgpr2
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%4:_(s1) = G_ICMP intpred(ne), %1, %2
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%5:_(s32) = G_SELECT %4, %3, %0
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...
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---
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name: select_vvv
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legalized: true
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# GCN-LABEL: name: select_vvv
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# GCN: [[VGPR0:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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# GCN: [[VGPR1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
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# GCN: [[VGPR2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
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# GCN: [[VGPR3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
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# GCN: [[VCC:%[0-9]+]]:sgpr(s1) = G_ICMP intpred(ne), [[VGPR0]](s32), [[VGPR1]]
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# GCN: {{%[0-9]+}}:vgpr(s32) = G_SELECT [[VCC]](s1), [[VGPR2]], [[VGPR3]]
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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%2:_(s32) = COPY $vgpr2
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%3:_(s32) = COPY $vgpr3
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%4:_(s1) = G_ICMP intpred(ne), %0, %1
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%5:_(s32) = G_SELECT %4, %2, %3
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...
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