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[AArch64] Use \t in AsmStreamer to match the prevailing style

This commit is contained in:
Fangrui Song 2021-05-23 11:35:42 -07:00
parent 9a6eb4968e
commit ff8be66c02
2 changed files with 21 additions and 21 deletions
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30
llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
View File

@ -50,51 +50,51 @@ class AArch64TargetAsmStreamer : public AArch64TargetStreamer {
void emitInst(uint32_t Inst) override; void emitInst(uint32_t Inst) override;
void emitDirectiveVariantPCS(MCSymbol *Symbol) override { void emitDirectiveVariantPCS(MCSymbol *Symbol) override {
OS << "\t.variant_pcs " << Symbol->getName() << "\n"; OS << "\t.variant_pcs\t" << Symbol->getName() << "\n";
} }
void EmitARM64WinCFIAllocStack(unsigned Size) override { void EmitARM64WinCFIAllocStack(unsigned Size) override {
OS << "\t.seh_stackalloc " << Size << "\n"; OS << "\t.seh_stackalloc\t" << Size << "\n";
} }
void EmitARM64WinCFISaveR19R20X(int Offset) override { void EmitARM64WinCFISaveR19R20X(int Offset) override {
OS << "\t.seh_save_r19r20_x " << Offset << "\n"; OS << "\t.seh_save_r19r20_x\t" << Offset << "\n";
} }
void EmitARM64WinCFISaveFPLR(int Offset) override { void EmitARM64WinCFISaveFPLR(int Offset) override {
OS << "\t.seh_save_fplr " << Offset << "\n"; OS << "\t.seh_save_fplr\t" << Offset << "\n";
} }
void EmitARM64WinCFISaveFPLRX(int Offset) override { void EmitARM64WinCFISaveFPLRX(int Offset) override {
OS << "\t.seh_save_fplr_x " << Offset << "\n"; OS << "\t.seh_save_fplr_x\t" << Offset << "\n";
} }
void EmitARM64WinCFISaveReg(unsigned Reg, int Offset) override { void EmitARM64WinCFISaveReg(unsigned Reg, int Offset) override {
OS << "\t.seh_save_reg x" << Reg << ", " << Offset << "\n"; OS << "\t.seh_save_reg\tx" << Reg << ", " << Offset << "\n";
} }
void EmitARM64WinCFISaveRegX(unsigned Reg, int Offset) override { void EmitARM64WinCFISaveRegX(unsigned Reg, int Offset) override {
OS << "\t.seh_save_reg_x x" << Reg << ", " << Offset << "\n"; OS << "\t.seh_save_reg_x\tx" << Reg << ", " << Offset << "\n";
} }
void EmitARM64WinCFISaveRegP(unsigned Reg, int Offset) override { void EmitARM64WinCFISaveRegP(unsigned Reg, int Offset) override {
OS << "\t.seh_save_regp x" << Reg << ", " << Offset << "\n"; OS << "\t.seh_save_regp\tx" << Reg << ", " << Offset << "\n";
} }
void EmitARM64WinCFISaveRegPX(unsigned Reg, int Offset) override { void EmitARM64WinCFISaveRegPX(unsigned Reg, int Offset) override {
OS << "\t.seh_save_regp_x x" << Reg << ", " << Offset << "\n"; OS << "\t.seh_save_regp_x\tx" << Reg << ", " << Offset << "\n";
} }
void EmitARM64WinCFISaveLRPair(unsigned Reg, int Offset) override { void EmitARM64WinCFISaveLRPair(unsigned Reg, int Offset) override {
OS << "\t.seh_save_lrpair x" << Reg << ", " << Offset << "\n"; OS << "\t.seh_save_lrpair\tx" << Reg << ", " << Offset << "\n";
} }
void EmitARM64WinCFISaveFReg(unsigned Reg, int Offset) override { void EmitARM64WinCFISaveFReg(unsigned Reg, int Offset) override {
OS << "\t.seh_save_freg d" << Reg << ", " << Offset << "\n"; OS << "\t.seh_save_freg\td" << Reg << ", " << Offset << "\n";
} }
void EmitARM64WinCFISaveFRegX(unsigned Reg, int Offset) override { void EmitARM64WinCFISaveFRegX(unsigned Reg, int Offset) override {
OS << "\t.seh_save_freg_x d" << Reg << ", " << Offset << "\n"; OS << "\t.seh_save_freg_x\td" << Reg << ", " << Offset << "\n";
} }
void EmitARM64WinCFISaveFRegP(unsigned Reg, int Offset) override { void EmitARM64WinCFISaveFRegP(unsigned Reg, int Offset) override {
OS << "\t.seh_save_fregp d" << Reg << ", " << Offset << "\n"; OS << "\t.seh_save_fregp\td" << Reg << ", " << Offset << "\n";
} }
void EmitARM64WinCFISaveFRegPX(unsigned Reg, int Offset) override { void EmitARM64WinCFISaveFRegPX(unsigned Reg, int Offset) override {
OS << "\t.seh_save_fregp_x d" << Reg << ", " << Offset << "\n"; OS << "\t.seh_save_fregp_x\td" << Reg << ", " << Offset << "\n";
} }
void EmitARM64WinCFISetFP() override { OS << "\t.seh_set_fp\n"; } void EmitARM64WinCFISetFP() override { OS << "\t.seh_set_fp\n"; }
void EmitARM64WinCFIAddFP(unsigned Size) override { void EmitARM64WinCFIAddFP(unsigned Size) override {
OS << "\t.seh_add_fp " << Size << "\n"; OS << "\t.seh_add_fp\t" << Size << "\n";
} }
void EmitARM64WinCFINop() override { OS << "\t.seh_nop\n"; } void EmitARM64WinCFINop() override { OS << "\t.seh_nop\n"; }
void EmitARM64WinCFISaveNext() override { OS << "\t.seh_save_next\n"; } void EmitARM64WinCFISaveNext() override { OS << "\t.seh_save_next\n"; }

12
llvm/test/CodeGen/AArch64/variant-pcs.ll
View File

@ -1,4 +1,4 @@
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -o - %s | FileCheck %s --check-prefix=CHECK-ASM ; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -o - %s | FileCheck %s --check-prefix=CHECK-ASM --strict-whitespace
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -filetype=obj -o - %s \ ; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -filetype=obj -o - %s \
; RUN: | llvm-readobj --symbols - | FileCheck %s --check-prefix=CHECK-OBJ ; RUN: | llvm-readobj --symbols - | FileCheck %s --check-prefix=CHECK-OBJ
@ -11,7 +11,7 @@ define i32 @base_pcs() {
} }
define aarch64_vector_pcs <4 x i32> @neon_vector_pcs_1(<4 x i32> %arg) { define aarch64_vector_pcs <4 x i32> @neon_vector_pcs_1(<4 x i32> %arg) {
; CHECK-ASM: .variant_pcs neon_vector_pcs_1 ; CHECK-ASM: .variant_pcs neon_vector_pcs_1
; CHECK-ASM-NEXT: neon_vector_pcs_1: ; CHECK-ASM-NEXT: neon_vector_pcs_1:
; CHECK-OBJ-LABEL: Name: neon_vector_pcs_1 ; CHECK-OBJ-LABEL: Name: neon_vector_pcs_1
; CHECK-OBJ: Other [ (0x80) ; CHECK-OBJ: Other [ (0x80)
@ -19,7 +19,7 @@ define aarch64_vector_pcs <4 x i32> @neon_vector_pcs_1(<4 x i32> %arg) {
} }
define <vscale x 4 x i32> @sve_vector_pcs_1() { define <vscale x 4 x i32> @sve_vector_pcs_1() {
; CHECK-ASM: .variant_pcs sve_vector_pcs_1 ; CHECK-ASM: .variant_pcs sve_vector_pcs_1
; CHECK-ASM-NEXT: sve_vector_pcs_1: ; CHECK-ASM-NEXT: sve_vector_pcs_1:
; CHECK-OBJ-LABEL: Name: sve_vector_pcs_1 ; CHECK-OBJ-LABEL: Name: sve_vector_pcs_1
; CHECK-OBJ: Other [ (0x80) ; CHECK-OBJ: Other [ (0x80)
@ -27,7 +27,7 @@ define <vscale x 4 x i32> @sve_vector_pcs_1() {
} }
define <vscale x 4 x i1> @sve_vector_pcs_2() { define <vscale x 4 x i1> @sve_vector_pcs_2() {
; CHECK-ASM: .variant_pcs sve_vector_pcs_2 ; CHECK-ASM: .variant_pcs sve_vector_pcs_2
; CHECK-ASM-NEXT: sve_vector_pcs_2: ; CHECK-ASM-NEXT: sve_vector_pcs_2:
; CHECK-OBJ-LABEL: Name: sve_vector_pcs_2 ; CHECK-OBJ-LABEL: Name: sve_vector_pcs_2
; CHECK-OBJ: Other [ (0x80) ; CHECK-OBJ: Other [ (0x80)
@ -35,7 +35,7 @@ define <vscale x 4 x i1> @sve_vector_pcs_2() {
} }
define void @sve_vector_pcs_3(<vscale x 4 x i32> %arg) { define void @sve_vector_pcs_3(<vscale x 4 x i32> %arg) {
; CHECK-ASM: .variant_pcs sve_vector_pcs_3 ; CHECK-ASM: .variant_pcs sve_vector_pcs_3
; CHECK-ASM-NEXT: sve_vector_pcs_3: ; CHECK-ASM-NEXT: sve_vector_pcs_3:
; CHECK-OBJ-LABEL: Name: sve_vector_pcs_3 ; CHECK-OBJ-LABEL: Name: sve_vector_pcs_3
; CHECK-OBJ: Other [ (0x80) ; CHECK-OBJ: Other [ (0x80)
@ -43,7 +43,7 @@ define void @sve_vector_pcs_3(<vscale x 4 x i32> %arg) {
} }
define void @sve_vector_pcs_4(<vscale x 4 x i1> %arg) { define void @sve_vector_pcs_4(<vscale x 4 x i1> %arg) {
; CHECK-ASM: .variant_pcs sve_vector_pcs_4 ; CHECK-ASM: .variant_pcs sve_vector_pcs_4
; CHECK-ASM-NEXT: sve_vector_pcs_4: ; CHECK-ASM-NEXT: sve_vector_pcs_4:
; CHECK-OBJ-LABEL: Name: sve_vector_pcs_4 ; CHECK-OBJ-LABEL: Name: sve_vector_pcs_4
; CHECK-OBJ: Other [ (0x80) ; CHECK-OBJ: Other [ (0x80)