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[Target] Use range-based for loops (NFC)

This commit is contained in:
Kazu Hirata 2021-11-27 11:16:18 -08:00
parent 7d5d063c77
commit ff649e0802
17 changed files with 23 additions and 39 deletions
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3
llvm/lib/Target/Lanai/LanaiDelaySlotFiller.cpp
View File

@ -199,8 +199,7 @@ bool Filler::delayHasHazard(MachineBasicBlock::instr_iterator MI, bool &SawLoad,
assert((!MI->isCall() && !MI->isReturn()) &&
"Cannot put calls or returns in delay slot.");
for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
const MachineOperand &MO = MI->getOperand(I);
for (const MachineOperand &MO : MI->operands()) {
unsigned Reg;
if (!MO.isReg() || !(Reg = MO.getReg()))

3
llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
View File

@ -467,8 +467,7 @@ static MachineInstr *canFoldIntoSelect(Register Reg,
return nullptr;
// Check if MI has any non-dead defs or physreg uses. This also detects
// predicated instructions which will be reading SR.
for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
for (const MachineOperand &MO : llvm::drop_begin(MI->operands(), 1)) {
// Reject frame index operands.
if (MO.isFI() || MO.isCPI() || MO.isJTI())
return nullptr;

4
llvm/lib/Target/Lanai/LanaiMCInstLower.cpp
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@ -93,9 +93,7 @@ MCOperand LanaiMCInstLower::LowerSymbolOperand(const MachineOperand &MO,
void LanaiMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
OutMI.setOpcode(MI->getOpcode());
for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
const MachineOperand &MO = MI->getOperand(I);
for (const MachineOperand &MO : MI->operands()) {
MCOperand MCOp;
switch (MO.getType()) {
case MachineOperand::MO_Register:

4
llvm/lib/Target/MSP430/MSP430MCInstLower.cpp
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@ -115,9 +115,7 @@ LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const {
void MSP430MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
OutMI.setOpcode(MI->getOpcode());
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
for (const MachineOperand &MO : MI->operands()) {
MCOperand MCOp;
switch (MO.getType()) {
default:

5
llvm/lib/Target/Mips/MipsAsmPrinter.cpp
View File

@ -163,9 +163,8 @@ static void emitDirectiveRelocJalr(const MachineInstr &MI,
TargetMachine &TM,
MCStreamer &OutStreamer,
const MipsSubtarget &Subtarget) {
for (unsigned int I = MI.getDesc().getNumOperands(), E = MI.getNumOperands();
I < E; ++I) {
MachineOperand MO = MI.getOperand(I);
for (const MachineOperand &MO :
llvm::drop_begin(MI.operands(), MI.getDesc().getNumOperands())) {
if (MO.isMCSymbol() && (MO.getTargetFlags() & MipsII::MO_JALR)) {
MCSymbol *Callee = MO.getMCSymbol();
if (Callee && !Callee->getName().empty()) {

6
llvm/lib/Target/Mips/MipsConstantIslandPass.cpp
View File

@ -730,8 +730,8 @@ initializeFunctionInfo(const std::vector<MachineInstr*> &CPEMIs) {
continue;
// Scan the instructions for constant pool operands.
for (unsigned op = 0, e = MI.getNumOperands(); op != e; ++op)
if (MI.getOperand(op).isCPI()) {
for (const MachineOperand &MO : MI.operands())
if (MO.isCPI()) {
// We found one. The addressing mode tells us the max displacement
// from the PC that this instruction permits.
@ -759,7 +759,7 @@ initializeFunctionInfo(const std::vector<MachineInstr*> &CPEMIs) {
break;
}
// Remember that this is a user of a CP entry.
unsigned CPI = MI.getOperand(op).getIndex();
unsigned CPI = MO.getIndex();
MachineInstr *CPEMI = CPEMIs[CPI];
unsigned MaxOffs = ((1 << Bits)-1) * Scale;
unsigned LongFormMaxOffs = ((1 << LongFormBits)-1) * LongFormScale;

3
llvm/lib/Target/Mips/MipsMCInstLower.cpp
View File

@ -318,8 +318,7 @@ void MipsMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
OutMI.setOpcode(MI->getOpcode());
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
for (const MachineOperand &MO : MI->operands()) {
MCOperand MCOp = LowerOperand(MO);
if (MCOp.isValid())

4
llvm/lib/Target/Mips/MipsSEISelLowering.cpp
View File

@ -3581,8 +3581,8 @@ MipsSETargetLowering::emitLD_F16_PSEUDO(MachineInstr &MI,
MachineInstrBuilder MIB =
BuildMI(*BB, MI, DL, TII->get(UsingMips32 ? Mips::LH : Mips::LH64), Rt);
for (unsigned i = 1; i < MI.getNumOperands(); i++)
MIB.add(MI.getOperand(i));
for (const MachineOperand &MO : llvm::drop_begin(MI.operands()))
MIB.add(MO);
if(!UsingMips32) {
Register Tmp = RegInfo.createVirtualRegister(&Mips::GPR32RegClass);

3
llvm/lib/Target/PowerPC/PPCCTRLoops.cpp
View File

@ -81,8 +81,7 @@ FunctionPass *llvm::createPPCCTRLoopsVerify() {
}
static bool clobbersCTR(const MachineInstr &MI) {
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI.getOperand(i);
for (const MachineOperand &MO : MI.operands()) {
if (MO.isReg()) {
if (MO.isDef() && (MO.getReg() == PPC::CTR || MO.getReg() == PPC::CTR8))
return true;

3
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
View File

@ -2330,8 +2330,7 @@ bool PPCInstrInfo::ClobbersPredicate(MachineInstr &MI,
&PPC::CTRRCRegClass, &PPC::CTRRC8RegClass };
bool Found = false;
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI.getOperand(i);
for (const MachineOperand &MO : MI.operands()) {
for (unsigned c = 0; c < array_lengthof(RCs) && !Found; ++c) {
const TargetRegisterClass *RC = RCs[c];
if (MO.isReg()) {

4
llvm/lib/Target/PowerPC/PPCMCInstLower.cpp
View File

@ -152,9 +152,9 @@ void llvm::LowerPPCMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
AsmPrinter &AP) {
OutMI.setOpcode(MI->getOpcode());
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
for (const MachineOperand &MO : MI->operands()) {
MCOperand MCOp;
if (LowerPPCMachineOperandToMCOperand(MI->getOperand(i), MCOp, AP))
if (LowerPPCMachineOperandToMCOperand(MO, MCOp, AP))
OutMI.addOperand(MCOp);
}
}

3
llvm/lib/Target/Sparc/DelaySlotFiller.cpp
View File

@ -318,8 +318,7 @@ void Filler::insertDefsUses(MachineBasicBlock::iterator MI,
SmallSet<unsigned, 32>& RegDefs,
SmallSet<unsigned, 32>& RegUses)
{
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
for (const MachineOperand &MO : MI->operands()) {
if (!MO.isReg())
continue;

3
llvm/lib/Target/Sparc/SparcMCInstLower.cpp
View File

@ -97,8 +97,7 @@ void llvm::LowerSparcMachineInstrToMCInst(const MachineInstr *MI,
OutMI.setOpcode(MI->getOpcode());
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
for (const MachineOperand &MO : MI->operands()) {
MCOperand MCOp = LowerOperand(MI, MO, AP);
if (MCOp.isValid())

3
llvm/lib/Target/SystemZ/SystemZElimCompare.cpp
View File

@ -144,8 +144,7 @@ Reference SystemZElimCompare::getRegReferences(MachineInstr &MI, unsigned Reg) {
if (MI.isDebugInstr())
return Ref;
for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {
const MachineOperand &MO = MI.getOperand(I);
for (const MachineOperand &MO : MI.operands()) {
if (MO.isReg()) {
if (Register MOReg = MO.getReg()) {
if (TRI->regsOverlap(MOReg, Reg)) {

4
llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
View File

@ -203,8 +203,8 @@ void SystemZInstrInfo::expandZExtPseudo(MachineInstr &MI, unsigned LowOpcode,
Size, MI.getOperand(1).isKill(), MI.getOperand(1).isUndef());
// Keep the remaining operands as-is.
for (unsigned I = 2; I < MI.getNumOperands(); ++I)
MIB.add(MI.getOperand(I));
for (const MachineOperand &MO : llvm::drop_begin(MI.operands(), 2))
MIB.add(MO);
MI.eraseFromParent();
}

4
llvm/lib/Target/SystemZ/SystemZMCInstLower.cpp
View File

@ -93,10 +93,8 @@ MCOperand SystemZMCInstLower::lowerOperand(const MachineOperand &MO) const {
void SystemZMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
OutMI.setOpcode(MI->getOpcode());
for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
const MachineOperand &MO = MI->getOperand(I);
for (const MachineOperand &MO : MI->operands())
// Ignore all implicit register operands.
if (!MO.isReg() || !MO.isImplicit())
OutMI.addOperand(lowerOperand(MO));
}
}

3
llvm/lib/Target/XCore/XCoreMCInstLower.cpp
View File

@ -103,8 +103,7 @@ MCOperand XCoreMCInstLower::LowerOperand(const MachineOperand &MO,
void XCoreMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
OutMI.setOpcode(MI->getOpcode());
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
for (const MachineOperand &MO : MI->operands()) {
MCOperand MCOp = LowerOperand(MO);
if (MCOp.isValid())